// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from stm32g050.svd, see https://github.com/tinygo-org/stm32-svd

//go:build stm32 && stm32g050

/*
// STM32G050
*/

package stm32

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "STM32G050"
	CPU          = "CM0"
	FPUPresent   = false
	NVICPrioBits = 2
)

// Interrupt numbers.
const (
	// System window watchdog
	IRQ_WWDG = 0

	// Real-time clock
	IRQ_RTC_STAMP = 2

	// Flash
	IRQ_FLASH = 3

	// Reset and clock control
	IRQ_RCC = 4

	// External interrupt/event controller
	IRQ_EXTI0_1 = 5

	// External interrupt/event controller
	IRQ_EXTI2_3 = 6

	// External interrupt/event controller
	IRQ_EXTI4_15 = 7

	// DMA controller
	IRQ_DMA1_Channel1 = 9

	// DMA controller
	IRQ_DMA1_Channel2_3 = 10

	// DMA controller
	IRQ_DMA1_Channel4_5_6_7_DMAMUX = 11

	// Analog to Digital ConverteR
	IRQ_ADC = 12

	// Advanced-timers
	IRQ_TIM1_BRK_UP_TRG_COM = 13

	// Advanced-timers
	IRQ_TIM1_CC = 14

	// General-purpose-timers
	IRQ_TIM3 = 16

	// Basic timers
	IRQ_TIM6 = 17

	IRQ_TIM7 = 18

	// General purpose timers
	IRQ_TIM14 = 19

	// General purpose timers
	IRQ_TIM15 = 20

	// General purpose timers
	IRQ_TIM16 = 21

	IRQ_TIM17 = 22

	// Inter-integrated circuit
	IRQ_I2C1 = 23

	IRQ_I2C2 = 24

	// Serial peripheral interface/Inter-IC sound
	IRQ_SPI1 = 25

	IRQ_SPI2_SPI3 = 26

	// Universal synchronous asynchronous receiver transmitter
	IRQ_USART1 = 27

	IRQ_USART2 = 28

	// Highest interrupt number on this device.
	IRQ_max = 28
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)

//export WWDG_IRQHandler
func interruptWWDG() {
	callHandlers(IRQ_WWDG)
}

//export RTC_STAMP_IRQHandler
func interruptRTC_STAMP() {
	callHandlers(IRQ_RTC_STAMP)
}

//export FLASH_IRQHandler
func interruptFLASH() {
	callHandlers(IRQ_FLASH)
}

//export RCC_IRQHandler
func interruptRCC() {
	callHandlers(IRQ_RCC)
}

//export EXTI0_1_IRQHandler
func interruptEXTI0_1() {
	callHandlers(IRQ_EXTI0_1)
}

//export EXTI2_3_IRQHandler
func interruptEXTI2_3() {
	callHandlers(IRQ_EXTI2_3)
}

//export EXTI4_15_IRQHandler
func interruptEXTI4_15() {
	callHandlers(IRQ_EXTI4_15)
}

//export DMA1_Channel1_IRQHandler
func interruptDMA1_Channel1() {
	callHandlers(IRQ_DMA1_Channel1)
}

//export DMA1_Channel2_3_IRQHandler
func interruptDMA1_Channel2_3() {
	callHandlers(IRQ_DMA1_Channel2_3)
}

//export DMA1_Channel4_5_6_7_DMAMUX_IRQHandler
func interruptDMA1_Channel4_5_6_7_DMAMUX() {
	callHandlers(IRQ_DMA1_Channel4_5_6_7_DMAMUX)
}

//export ADC_IRQHandler
func interruptADC() {
	callHandlers(IRQ_ADC)
}

//export TIM1_BRK_UP_TRG_COM_IRQHandler
func interruptTIM1_BRK_UP_TRG_COM() {
	callHandlers(IRQ_TIM1_BRK_UP_TRG_COM)
}

//export TIM1_CC_IRQHandler
func interruptTIM1_CC() {
	callHandlers(IRQ_TIM1_CC)
}

//export TIM3_IRQHandler
func interruptTIM3() {
	callHandlers(IRQ_TIM3)
}

//export TIM6_IRQHandler
func interruptTIM6() {
	callHandlers(IRQ_TIM6)
}

//export TIM7_IRQHandler
func interruptTIM7() {
	callHandlers(IRQ_TIM7)
}

//export TIM14_IRQHandler
func interruptTIM14() {
	callHandlers(IRQ_TIM14)
}

//export TIM15_IRQHandler
func interruptTIM15() {
	callHandlers(IRQ_TIM15)
}

//export TIM16_IRQHandler
func interruptTIM16() {
	callHandlers(IRQ_TIM16)
}

//export TIM17_IRQHandler
func interruptTIM17() {
	callHandlers(IRQ_TIM17)
}

//export I2C1_IRQHandler
func interruptI2C1() {
	callHandlers(IRQ_I2C1)
}

//export I2C2_IRQHandler
func interruptI2C2() {
	callHandlers(IRQ_I2C2)
}

//export SPI1_IRQHandler
func interruptSPI1() {
	callHandlers(IRQ_SPI1)
}

//export SPI2_SPI3_IRQHandler
func interruptSPI2_SPI3() {
	callHandlers(IRQ_SPI2_SPI3)
}

//export USART1_IRQHandler
func interruptUSART1() {
	callHandlers(IRQ_USART1)
}

//export USART2_IRQHandler
func interruptUSART2() {
	callHandlers(IRQ_USART2)
}

// Peripherals.
var (
	// Analog to Digital ConverteR
	ADC = (*ADC_Type)(unsafe.Pointer(uintptr(0x40012400)))

	// Cyclic redundancy check calculation unit
	CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x40023000)))

	// Debug support
	DBG = (*DBG_Type)(unsafe.Pointer(uintptr(0x40015800)))

	// DMA controller
	DMA1 = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020000)))

	// DMAMUX
	DMAMUX = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x40020800)))

	// External interrupt/event controller
	EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x40021800)))

	// Flash
	FLASH = (*Flash_Type)(unsafe.Pointer(uintptr(0x40022000)))

	// General-purpose I/Os
	GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x50000000)))

	// General-purpose I/Os
	GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x50000400)))

	// General-purpose I/Os
	GPIOC = (*GPIO_Type)(unsafe.Pointer(uintptr(0x50000800)))

	// General-purpose I/Os
	GPIOD = (*GPIO_Type)(unsafe.Pointer(uintptr(0x50000c00)))

	// General-purpose I/Os
	GPIOE = (*GPIO_Type)(unsafe.Pointer(uintptr(0x50001000)))

	// General-purpose I/Os
	GPIOF = (*GPIO_Type)(unsafe.Pointer(uintptr(0x50001400)))

	// Inter-integrated circuit
	I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005400)))

	// Inter-integrated circuit
	I2C2 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005800)))

	// Independent watchdog
	IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Power control
	PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x40007000)))

	// Reset and clock control
	RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x40021000)))

	// Real-time clock
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x40002800)))

	// Serial peripheral interface/Inter-IC sound
	SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013000)))

	// Serial peripheral interface/Inter-IC sound
	SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// System configuration controller
	SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x40010000)))

	// Tamper and backup registers
	TAMP = (*TAMP_Type)(unsafe.Pointer(uintptr(0x4000b000)))

	// Advanced-timers
	TIM1 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40012c00)))

	// General-purpose-timers
	TIM3 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000400)))

	// General purpose timers
	TIM15 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014000)))

	// Basic timers
	TIM6 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001000)))

	// Basic timers
	TIM7 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001400)))

	// General purpose timers
	TIM14 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40002000)))

	// General purpose timers
	TIM16 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014400)))

	// General purpose timers
	TIM17 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014800)))

	// Universal synchronous asynchronous receiver transmitter
	USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x40013800)))

	// Universal synchronous asynchronous receiver transmitter
	USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004400)))

	// System window watchdog
	WWDG = (*WWDG_Type)(unsafe.Pointer(uintptr(0x40002c00)))
)

// Analog to Digital ConverteR
type ADC_Type struct {
	ISR     volatile.Register32 // 0x0
	IER     volatile.Register32 // 0x4
	CR      volatile.Register32 // 0x8
	CFGR1   volatile.Register32 // 0xC
	CFGR2   volatile.Register32 // 0x10
	SMPR    volatile.Register32 // 0x14
	_       [8]byte
	AWD1TR  volatile.Register32 // 0x20
	AWD2TR  volatile.Register32 // 0x24
	CHSELR0 volatile.Register32 // 0x28
	AWD3TR  volatile.Register32 // 0x2C
	_       [16]byte
	DR      volatile.Register32 // 0x40
	_       [92]byte
	AWD2CR  volatile.Register32 // 0xA0
	AWD3CR  volatile.Register32 // 0xA4
	_       [12]byte
	CALFACT volatile.Register32 // 0xB4
	_       [592]byte
	CCR     volatile.Register32 // 0x308
}

// ADC.ISR: ADC interrupt and status register
func (o *ADC_Type) SetISR_ADRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetISR_ADRDY() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *ADC_Type) SetISR_EOSMP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetISR_EOSMP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetISR_EOC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetISR_EOC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetISR_EOS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetISR_EOS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetISR_AWD1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetISR_AWD1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetISR_AWD2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetISR_AWD2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetISR_AWD3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetISR_AWD3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetISR_EOCAL(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetISR_EOCAL() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetISR_CCRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetISR_CCRDY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}

// ADC.IER: ADC interrupt enable register
func (o *ADC_Type) SetIER_ADRDYIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIER_ADRDYIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *ADC_Type) SetIER_EOSMPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIER_EOSMPIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIER_EOCIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetIER_EOCIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetIER_EOSIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIER_EOSIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIER_OVRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIER_OVRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIER_AWD1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetIER_AWD1IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetIER_AWD2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetIER_AWD2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetIER_AWD3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIER_AWD3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIER_EOCALIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetIER_EOCALIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetIER_CCRDYIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetIER_CCRDYIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}

// ADC.CR: ADC control register
func (o *ADC_Type) SetCR_ADEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCR_ADEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *ADC_Type) SetCR_ADDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCR_ADDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCR_ADSTART(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCR_ADSTART() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCR_ADSTP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCR_ADSTP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCR_ADVREGEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetCR_ADVREGEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetCR_ADCAL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetCR_ADCAL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// ADC.CFGR1: ADC configuration register 1
func (o *ADC_Type) SetCFGR1_DMAEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCFGR1_DMAEN() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x1
}
func (o *ADC_Type) SetCFGR1_DMACFG(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCFGR1_DMACFG() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCFGR1_SCANDIR(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCFGR1_SCANDIR() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCFGR1_RES(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x18)|value<<3)
}
func (o *ADC_Type) GetCFGR1_RES() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x18) >> 3
}
func (o *ADC_Type) SetCFGR1_ALIGN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCFGR1_ALIGN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCFGR1_EXTSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1c0)|value<<6)
}
func (o *ADC_Type) GetCFGR1_EXTSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1c0) >> 6
}
func (o *ADC_Type) SetCFGR1_EXTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetCFGR1_EXTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetCFGR1_OVRMOD(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCFGR1_OVRMOD() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCFGR1_CONT(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCFGR1_CONT() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCFGR1_WAIT(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCFGR1_WAIT() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCFGR1_AUTOFF(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCFGR1_AUTOFF() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetCFGR1_DISCEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCFGR1_DISCEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCFGR1_CHSELRMOD(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *ADC_Type) GetCFGR1_CHSELRMOD() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200000) >> 21
}
func (o *ADC_Type) SetCFGR1_AWD1SGL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetCFGR1_AWD1SGL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetCFGR1_AWD1EN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetCFGR1_AWD1EN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetCFGR1_AWD1CH(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetCFGR1_AWD1CH() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x7c000000) >> 26
}

// ADC.CFGR2: ADC configuration register 2
func (o *ADC_Type) SetCFGR2_OVSE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCFGR2_OVSE() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}
func (o *ADC_Type) SetCFGR2_OVSR(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1c)|value<<2)
}
func (o *ADC_Type) GetCFGR2_OVSR() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x1c) >> 2
}
func (o *ADC_Type) SetCFGR2_OVSS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1e0)|value<<5)
}
func (o *ADC_Type) GetCFGR2_OVSS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x1e0) >> 5
}
func (o *ADC_Type) SetCFGR2_TOVS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCFGR2_TOVS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCFGR2_LFTRIG(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetCFGR2_LFTRIG() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetCFGR2_CKMODE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetCFGR2_CKMODE() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0xc0000000) >> 30
}

// ADC.SMPR: ADC sampling time register
func (o *ADC_Type) SetSMPR_SMP1(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x70)|value<<4)
}
func (o *ADC_Type) GetSMPR_SMP1() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x70) >> 4
}
func (o *ADC_Type) SetSMPR_SMP2(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x700)|value<<8)
}
func (o *ADC_Type) GetSMPR_SMP2() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x700) >> 8
}
func (o *ADC_Type) SetSMPR_SMPSEL0(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetSMPR_SMPSEL0() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetSMPR_SMPSEL1(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetSMPR_SMPSEL1() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetSMPR_SMPSEL2(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetSMPR_SMPSEL2() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetSMPR_SMPSEL3(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetSMPR_SMPSEL3() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetSMPR_SMPSEL4(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetSMPR_SMPSEL4() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetSMPR_SMPSEL5(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetSMPR_SMPSEL5() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetSMPR_SMPSEL6(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetSMPR_SMPSEL6() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetSMPR_SMPSEL7(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetSMPR_SMPSEL7() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetSMPR_SMPSEL8(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetSMPR_SMPSEL8() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetSMPR_SMPSEL9(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetSMPR_SMPSEL9() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetSMPR_SMPSEL10(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetSMPR_SMPSEL10() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetSMPR_SMPSEL11(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetSMPR_SMPSEL11() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x100000) >> 20
}
func (o *ADC_Type) SetSMPR_SMPSEL12(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x200000)|value<<21)
}
func (o *ADC_Type) GetSMPR_SMPSEL12() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x200000) >> 21
}
func (o *ADC_Type) SetSMPR_SMPSEL13(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetSMPR_SMPSEL13() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetSMPR_SMPSEL14(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetSMPR_SMPSEL14() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetSMPR_SMPSEL15(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetSMPR_SMPSEL15() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetSMPR_SMPSEL16(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetSMPR_SMPSEL16() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetSMPR_SMPSEL17(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetSMPR_SMPSEL17() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetSMPR_SMPSEL18(value uint32) {
	volatile.StoreUint32(&o.SMPR.Reg, volatile.LoadUint32(&o.SMPR.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetSMPR_SMPSEL18() uint32 {
	return (volatile.LoadUint32(&o.SMPR.Reg) & 0x8000000) >> 27
}

// ADC.AWD1TR: ADC watchdog threshold register
func (o *ADC_Type) SetAWD1TR_LT1(value uint32) {
	volatile.StoreUint32(&o.AWD1TR.Reg, volatile.LoadUint32(&o.AWD1TR.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetAWD1TR_LT1() uint32 {
	return volatile.LoadUint32(&o.AWD1TR.Reg) & 0xfff
}
func (o *ADC_Type) SetAWD1TR_HT1(value uint32) {
	volatile.StoreUint32(&o.AWD1TR.Reg, volatile.LoadUint32(&o.AWD1TR.Reg)&^(0xfff0000)|value<<16)
}
func (o *ADC_Type) GetAWD1TR_HT1() uint32 {
	return (volatile.LoadUint32(&o.AWD1TR.Reg) & 0xfff0000) >> 16
}

// ADC.AWD2TR: ADC watchdog threshold register
func (o *ADC_Type) SetAWD2TR_LT2(value uint32) {
	volatile.StoreUint32(&o.AWD2TR.Reg, volatile.LoadUint32(&o.AWD2TR.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetAWD2TR_LT2() uint32 {
	return volatile.LoadUint32(&o.AWD2TR.Reg) & 0xfff
}
func (o *ADC_Type) SetAWD2TR_HT2(value uint32) {
	volatile.StoreUint32(&o.AWD2TR.Reg, volatile.LoadUint32(&o.AWD2TR.Reg)&^(0xfff0000)|value<<16)
}
func (o *ADC_Type) GetAWD2TR_HT2() uint32 {
	return (volatile.LoadUint32(&o.AWD2TR.Reg) & 0xfff0000) >> 16
}

// ADC.CHSELR0: ADC channel selection register [alternate]
func (o *ADC_Type) SetCHSELR0_CHSEL0(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCHSELR0_CHSEL0() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCHSELR0_CHSEL1(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCHSELR0_CHSEL1() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCHSELR0_CHSEL2(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCHSELR0_CHSEL2() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCHSELR0_CHSEL3(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCHSELR0_CHSEL3() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCHSELR0_CHSEL4(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCHSELR0_CHSEL4() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCHSELR0_CHSEL5(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetCHSELR0_CHSEL5() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetCHSELR0_CHSEL6(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetCHSELR0_CHSEL6() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetCHSELR0_CHSEL7(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetCHSELR0_CHSEL7() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetCHSELR0_CHSEL8(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCHSELR0_CHSEL8() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCHSELR0_CHSEL9(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCHSELR0_CHSEL9() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCHSELR0_CHSEL10(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetCHSELR0_CHSEL10() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetCHSELR0_CHSEL11(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCHSELR0_CHSEL11() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCHSELR0_CHSEL12(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCHSELR0_CHSEL12() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCHSELR0_CHSEL13(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCHSELR0_CHSEL13() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCHSELR0_CHSEL14(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCHSELR0_CHSEL14() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetCHSELR0_CHSEL15(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCHSELR0_CHSEL15() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCHSELR0_CHSEL16(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetCHSELR0_CHSEL16() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetCHSELR0_CHSEL17(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetCHSELR0_CHSEL17() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetCHSELR0_CHSEL18(value uint32) {
	volatile.StoreUint32(&o.CHSELR0.Reg, volatile.LoadUint32(&o.CHSELR0.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetCHSELR0_CHSEL18() uint32 {
	return (volatile.LoadUint32(&o.CHSELR0.Reg) & 0x80000) >> 19
}

// ADC.AWD3TR: ADC watchdog threshold register
func (o *ADC_Type) SetAWD3TR_LT3(value uint32) {
	volatile.StoreUint32(&o.AWD3TR.Reg, volatile.LoadUint32(&o.AWD3TR.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetAWD3TR_LT3() uint32 {
	return volatile.LoadUint32(&o.AWD3TR.Reg) & 0xfff
}
func (o *ADC_Type) SetAWD3TR_HT3(value uint32) {
	volatile.StoreUint32(&o.AWD3TR.Reg, volatile.LoadUint32(&o.AWD3TR.Reg)&^(0xfff0000)|value<<16)
}
func (o *ADC_Type) GetAWD3TR_HT3() uint32 {
	return (volatile.LoadUint32(&o.AWD3TR.Reg) & 0xfff0000) >> 16
}

// ADC.DR: ADC data register
func (o *ADC_Type) SetDR_DATA(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetDR_DATA() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xffff
}

// ADC.AWD2CR: ADC Analog Watchdog 2 Configuration register
func (o *ADC_Type) SetAWD2CR_AWD2CH0(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH0() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetAWD2CR_AWD2CH1(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH1() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetAWD2CR_AWD2CH2(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH2() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetAWD2CR_AWD2CH3(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH3() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetAWD2CR_AWD2CH4(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH4() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetAWD2CR_AWD2CH5(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH5() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetAWD2CR_AWD2CH6(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH6() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetAWD2CR_AWD2CH7(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH7() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetAWD2CR_AWD2CH8(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH8() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetAWD2CR_AWD2CH9(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH9() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetAWD2CR_AWD2CH10(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH10() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetAWD2CR_AWD2CH11(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH11() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetAWD2CR_AWD2CH12(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH12() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetAWD2CR_AWD2CH13(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH13() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetAWD2CR_AWD2CH14(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH14() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetAWD2CR_AWD2CH15(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH15() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetAWD2CR_AWD2CH16(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH16() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetAWD2CR_AWD2CH17(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH17() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetAWD2CR_AWD2CH18(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH18() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x80000) >> 19
}

// ADC.AWD3CR: ADC Analog Watchdog 3 Configuration register
func (o *ADC_Type) SetAWD3CR_AWD3CH0(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH0() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetAWD3CR_AWD3CH1(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH1() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetAWD3CR_AWD3CH2(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH2() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetAWD3CR_AWD3CH3(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH3() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetAWD3CR_AWD3CH4(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH4() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetAWD3CR_AWD3CH5(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH5() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetAWD3CR_AWD3CH6(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH6() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetAWD3CR_AWD3CH7(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH7() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetAWD3CR_AWD3CH8(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH8() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetAWD3CR_AWD3CH9(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH9() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetAWD3CR_AWD3CH10(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH10() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetAWD3CR_AWD3CH11(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH11() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetAWD3CR_AWD3CH12(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH12() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetAWD3CR_AWD3CH13(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH13() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetAWD3CR_AWD3CH14(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH14() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetAWD3CR_AWD3CH15(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH15() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetAWD3CR_AWD3CH16(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH16() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetAWD3CR_AWD3CH17(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH17() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetAWD3CR_AWD3CH18(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH18() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x80000) >> 19
}

// ADC.CALFACT: ADC Calibration factor
func (o *ADC_Type) SetCALFACT(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0x7f)|value)
}
func (o *ADC_Type) GetCALFACT() uint32 {
	return volatile.LoadUint32(&o.CALFACT.Reg) & 0x7f
}

// ADC.CCR: ADC common configuration register
func (o *ADC_Type) SetCCR_PRESC(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x3c0000)|value<<18)
}
func (o *ADC_Type) GetCCR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x3c0000) >> 18
}
func (o *ADC_Type) SetCCR_VREFEN(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetCCR_VREFEN() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetCCR_TSEN(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetCCR_TSEN() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetCCR_VBATEN(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCCR_VBATEN() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x1000000) >> 24
}

// Cyclic redundancy check calculation unit
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	_    [4]byte
	INIT volatile.Register32 // 0x10
	POL  volatile.Register32 // 0x14
}

// CRC.DR: Data register
func (o *CRC_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *CRC_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// CRC.IDR: Independent data register
func (o *CRC_Type) SetIDR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, value)
}
func (o *CRC_Type) GetIDR() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg)
}

// CRC.CR: Control register
func (o *CRC_Type) SetCR_REV_OUT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *CRC_Type) GetCR_REV_OUT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *CRC_Type) SetCR_REV_IN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60)|value<<5)
}
func (o *CRC_Type) GetCR_REV_IN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60) >> 5
}
func (o *CRC_Type) SetCR_POLYSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x18)|value<<3)
}
func (o *CRC_Type) GetCR_POLYSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x18) >> 3
}
func (o *CRC_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *CRC_Type) GetCR_RESET() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// CRC.INIT: Initial CRC value
func (o *CRC_Type) SetINIT(value uint32) {
	volatile.StoreUint32(&o.INIT.Reg, value)
}
func (o *CRC_Type) GetINIT() uint32 {
	return volatile.LoadUint32(&o.INIT.Reg)
}

// CRC.POL: polynomial
func (o *CRC_Type) SetPOL(value uint32) {
	volatile.StoreUint32(&o.POL.Reg, value)
}
func (o *CRC_Type) GetPOL() uint32 {
	return volatile.LoadUint32(&o.POL.Reg)
}

// Debug support
type DBG_Type struct {
	IDCODE  volatile.Register32 // 0x0
	CR      volatile.Register32 // 0x4
	APB_FZ1 volatile.Register32 // 0x8
	APB_FZ2 volatile.Register32 // 0xC
}

// DBG.IDCODE: MCU Device ID Code Register
func (o *DBG_Type) SetIDCODE_DEV_ID(value uint32) {
	volatile.StoreUint32(&o.IDCODE.Reg, volatile.LoadUint32(&o.IDCODE.Reg)&^(0xfff)|value)
}
func (o *DBG_Type) GetIDCODE_DEV_ID() uint32 {
	return volatile.LoadUint32(&o.IDCODE.Reg) & 0xfff
}
func (o *DBG_Type) SetIDCODE_REV_ID(value uint32) {
	volatile.StoreUint32(&o.IDCODE.Reg, volatile.LoadUint32(&o.IDCODE.Reg)&^(0xffff0000)|value<<16)
}
func (o *DBG_Type) GetIDCODE_REV_ID() uint32 {
	return (volatile.LoadUint32(&o.IDCODE.Reg) & 0xffff0000) >> 16
}

// DBG.CR: DBG configuration register
func (o *DBG_Type) SetCR_DBG_STOP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DBG_Type) GetCR_DBG_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DBG_Type) SetCR_DBG_STANDBY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DBG_Type) GetCR_DBG_STANDBY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}

// DBG.APB_FZ1: DBG APB freeze register 1
func (o *DBG_Type) SetAPB_FZ1_DBG_TIM3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x2)|value<<1)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_TIM3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x2) >> 1
}
func (o *DBG_Type) SetAPB_FZ1_DBG_TIM6_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x10)|value<<4)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_TIM6_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x10) >> 4
}
func (o *DBG_Type) SetAPB_FZ1_DBG_TIM7_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x20)|value<<5)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_TIM7_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x20) >> 5
}
func (o *DBG_Type) SetAPB_FZ1_DBG_RTC_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x400)|value<<10)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_RTC_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x400) >> 10
}
func (o *DBG_Type) SetAPB_FZ1_DBG_WWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x800)|value<<11)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_WWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x800) >> 11
}
func (o *DBG_Type) SetAPB_FZ1_DBG_IWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x1000)|value<<12)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_IWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x1000) >> 12
}
func (o *DBG_Type) SetAPB_FZ1_DBG_I2C1_SMBUS_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x200000)|value<<21)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_I2C1_SMBUS_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x200000) >> 21
}
func (o *DBG_Type) SetAPB_FZ1_DBG_I2C2_SMBUS_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.APB_FZ1.Reg, volatile.LoadUint32(&o.APB_FZ1.Reg)&^(0x400000)|value<<22)
}
func (o *DBG_Type) GetAPB_FZ1_DBG_I2C2_SMBUS_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ1.Reg) & 0x400000) >> 22
}

// DBG.APB_FZ2: DBG APB freeze register 2
func (o *DBG_Type) SetAPB_FZ2_DBG_TIM1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ2.Reg, volatile.LoadUint32(&o.APB_FZ2.Reg)&^(0x800)|value<<11)
}
func (o *DBG_Type) GetAPB_FZ2_DBG_TIM1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ2.Reg) & 0x800) >> 11
}
func (o *DBG_Type) SetAPB_FZ2_DBG_TIM14_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ2.Reg, volatile.LoadUint32(&o.APB_FZ2.Reg)&^(0x8000)|value<<15)
}
func (o *DBG_Type) GetAPB_FZ2_DBG_TIM14_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ2.Reg) & 0x8000) >> 15
}
func (o *DBG_Type) SetAPB_FZ2_DBG_TIM15_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ2.Reg, volatile.LoadUint32(&o.APB_FZ2.Reg)&^(0x10000)|value<<16)
}
func (o *DBG_Type) GetAPB_FZ2_DBG_TIM15_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ2.Reg) & 0x10000) >> 16
}
func (o *DBG_Type) SetAPB_FZ2_DBG_TIM16_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ2.Reg, volatile.LoadUint32(&o.APB_FZ2.Reg)&^(0x20000)|value<<17)
}
func (o *DBG_Type) GetAPB_FZ2_DBG_TIM16_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ2.Reg) & 0x20000) >> 17
}
func (o *DBG_Type) SetAPB_FZ2_DBG_TIM17_STOP(value uint32) {
	volatile.StoreUint32(&o.APB_FZ2.Reg, volatile.LoadUint32(&o.APB_FZ2.Reg)&^(0x40000)|value<<18)
}
func (o *DBG_Type) GetAPB_FZ2_DBG_TIM17_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB_FZ2.Reg) & 0x40000) >> 18
}

// DMA controller
type DMA_Type struct {
	ISR  volatile.Register32 // 0x0
	IFCR volatile.Register32 // 0x4
	CH   [7]DMA_CH_Type      // 0x8
}

// DMA.ISR: DMA interrupt status register
func (o *DMA_Type) SetISR_GIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_Type) GetISR_GIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *DMA_Type) SetISR_GIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetISR_GIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetISR_GIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA_Type) GetISR_GIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *DMA_Type) SetISR_GIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetISR_GIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *DMA_Type) SetISR_GIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_Type) GetISR_GIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *DMA_Type) SetISR_GIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMA_Type) GetISR_GIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *DMA_Type) SetISR_GIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMA_Type) GetISR_GIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000000) >> 28
}
func (o *DMA_Type) SetISR_TCIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_Type) GetISR_TCIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *DMA_Type) SetISR_TCIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *DMA_Type) GetISR_TCIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *DMA_Type) SetISR_TCIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA_Type) GetISR_TCIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *DMA_Type) SetISR_TCIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_Type) GetISR_TCIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *DMA_Type) SetISR_TCIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA_Type) GetISR_TCIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *DMA_Type) SetISR_TCIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMA_Type) GetISR_TCIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *DMA_Type) SetISR_TCIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMA_Type) GetISR_TCIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000000) >> 29
}
func (o *DMA_Type) SetISR_HTIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_Type) GetISR_HTIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *DMA_Type) SetISR_HTIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *DMA_Type) GetISR_HTIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *DMA_Type) SetISR_HTIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_Type) GetISR_HTIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *DMA_Type) SetISR_HTIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_Type) GetISR_HTIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *DMA_Type) SetISR_HTIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *DMA_Type) GetISR_HTIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *DMA_Type) SetISR_HTIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMA_Type) GetISR_HTIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *DMA_Type) SetISR_HTIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000000)|value<<30)
}
func (o *DMA_Type) GetISR_HTIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000000) >> 30
}
func (o *DMA_Type) SetISR_TEIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_Type) GetISR_TEIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *DMA_Type) SetISR_TEIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *DMA_Type) GetISR_TEIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *DMA_Type) SetISR_TEIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_Type) GetISR_TEIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *DMA_Type) SetISR_TEIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_Type) GetISR_TEIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *DMA_Type) SetISR_TEIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *DMA_Type) GetISR_TEIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *DMA_Type) SetISR_TEIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMA_Type) GetISR_TEIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *DMA_Type) SetISR_TEIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000000)|value<<31)
}
func (o *DMA_Type) GetISR_TEIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000000) >> 31
}

// DMA.IFCR: DMA interrupt flag clear register
func (o *DMA_Type) SetIFCR_CGIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_Type) GetIFCR_CGIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10) >> 4
}
func (o *DMA_Type) SetIFCR_CGIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetIFCR_CGIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetIFCR_CGIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA_Type) GetIFCR_CGIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x1000) >> 12
}
func (o *DMA_Type) SetIFCR_CGIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetIFCR_CGIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10000) >> 16
}
func (o *DMA_Type) SetIFCR_CGIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_Type) GetIFCR_CGIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100000) >> 20
}
func (o *DMA_Type) SetIFCR_CGIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMA_Type) GetIFCR_CGIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x1000000) >> 24
}
func (o *DMA_Type) SetIFCR_CGIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMA_Type) GetIFCR_CGIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10000000) >> 28
}
func (o *DMA_Type) SetIFCR_CTCIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_Type) GetIFCR_CTCIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20) >> 5
}
func (o *DMA_Type) SetIFCR_CTCIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200)|value<<9)
}
func (o *DMA_Type) GetIFCR_CTCIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200) >> 9
}
func (o *DMA_Type) SetIFCR_CTCIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA_Type) GetIFCR_CTCIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2000) >> 13
}
func (o *DMA_Type) SetIFCR_CTCIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_Type) GetIFCR_CTCIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20000) >> 17
}
func (o *DMA_Type) SetIFCR_CTCIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA_Type) GetIFCR_CTCIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200000) >> 21
}
func (o *DMA_Type) SetIFCR_CTCIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMA_Type) GetIFCR_CTCIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2000000) >> 25
}
func (o *DMA_Type) SetIFCR_CTCIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMA_Type) GetIFCR_CTCIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20000000) >> 29
}
func (o *DMA_Type) SetIFCR_CHTIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_Type) GetIFCR_CHTIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40) >> 6
}
func (o *DMA_Type) SetIFCR_CHTIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x400)|value<<10)
}
func (o *DMA_Type) GetIFCR_CHTIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x400) >> 10
}
func (o *DMA_Type) SetIFCR_CHTIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_Type) GetIFCR_CHTIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4000) >> 14
}
func (o *DMA_Type) SetIFCR_CHTIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_Type) GetIFCR_CHTIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40000) >> 18
}
func (o *DMA_Type) SetIFCR_CHTIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x400000)|value<<22)
}
func (o *DMA_Type) GetIFCR_CHTIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x400000) >> 22
}
func (o *DMA_Type) SetIFCR_CHTIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMA_Type) GetIFCR_CHTIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4000000) >> 26
}
func (o *DMA_Type) SetIFCR_CHTIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40000000)|value<<30)
}
func (o *DMA_Type) GetIFCR_CHTIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40000000) >> 30
}
func (o *DMA_Type) SetIFCR_CTEIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_Type) GetIFCR_CTEIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80) >> 7
}
func (o *DMA_Type) SetIFCR_CTEIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800)|value<<11)
}
func (o *DMA_Type) GetIFCR_CTEIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800) >> 11
}
func (o *DMA_Type) SetIFCR_CTEIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_Type) GetIFCR_CTEIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8000) >> 15
}
func (o *DMA_Type) SetIFCR_CTEIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_Type) GetIFCR_CTEIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80000) >> 19
}
func (o *DMA_Type) SetIFCR_CTEIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800000)|value<<23)
}
func (o *DMA_Type) GetIFCR_CTEIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800000) >> 23
}
func (o *DMA_Type) SetIFCR_CTEIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMA_Type) GetIFCR_CTEIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8000000) >> 27
}
func (o *DMA_Type) SetIFCR_CTEIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80000000)|value<<31)
}
func (o *DMA_Type) GetIFCR_CTEIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80000000) >> 31
}

// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
type DMA_CH_Type struct {
	CR   volatile.Register32 // 0x8
	NDTR volatile.Register32 // 0xC
	PAR  volatile.Register32 // 0x10
	MAR  volatile.Register32 // 0x14
	_    [4]byte
}

// DMA_CH.CR: DMA channel 1 configuration register
func (o *DMA_CH_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DMA_CH_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *DMA_CH_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DMA_CH_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DMA_CH_Type) SetCR_HTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DMA_CH_Type) GetCR_HTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DMA_CH_Type) SetCR_TEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *DMA_CH_Type) GetCR_TEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *DMA_CH_Type) SetCR_DIR(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_CH_Type) GetCR_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *DMA_CH_Type) SetCR_CIRC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_CH_Type) GetCR_CIRC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *DMA_CH_Type) SetCR_PINC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_CH_Type) GetCR_PINC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *DMA_CH_Type) SetCR_MINC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_CH_Type) GetCR_MINC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *DMA_CH_Type) SetCR_PSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x300)|value<<8)
}
func (o *DMA_CH_Type) GetCR_PSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x300) >> 8
}
func (o *DMA_CH_Type) SetCR_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *DMA_CH_Type) GetCR_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *DMA_CH_Type) SetCR_PL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3000)|value<<12)
}
func (o *DMA_CH_Type) GetCR_PL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3000) >> 12
}
func (o *DMA_CH_Type) SetCR_MEM2MEM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_CH_Type) GetCR_MEM2MEM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}

// DMA_CH.NDTR: DMA channel x number of data register
func (o *DMA_CH_Type) SetNDTR_NDT(value uint32) {
	volatile.StoreUint32(&o.NDTR.Reg, volatile.LoadUint32(&o.NDTR.Reg)&^(0xffff)|value)
}
func (o *DMA_CH_Type) GetNDTR_NDT() uint32 {
	return volatile.LoadUint32(&o.NDTR.Reg) & 0xffff
}

// DMA_CH.PAR: DMA channel x peripheral address register
func (o *DMA_CH_Type) SetPAR(value uint32) {
	volatile.StoreUint32(&o.PAR.Reg, value)
}
func (o *DMA_CH_Type) GetPAR() uint32 {
	return volatile.LoadUint32(&o.PAR.Reg)
}

// DMA_CH.MAR: DMA channel x memory address register
func (o *DMA_CH_Type) SetMAR(value uint32) {
	volatile.StoreUint32(&o.MAR.Reg, value)
}
func (o *DMA_CH_Type) GetMAR() uint32 {
	return volatile.LoadUint32(&o.MAR.Reg)
}

// DMAMUX
type DMAMUX_Type struct {
	CCR0  volatile.Register32 // 0x0
	CCR1  volatile.Register32 // 0x4
	CCR2  volatile.Register32 // 0x8
	CCR3  volatile.Register32 // 0xC
	CCR4  volatile.Register32 // 0x10
	CCR5  volatile.Register32 // 0x14
	CCR6  volatile.Register32 // 0x18
	CCR7  volatile.Register32 // 0x1C
	CCR8  volatile.Register32 // 0x20
	CCR9  volatile.Register32 // 0x24
	CCR10 volatile.Register32 // 0x28
	CCR11 volatile.Register32 // 0x2C
	_     [80]byte
	CSR   volatile.Register32 // 0x80
	CFR   volatile.Register32 // 0x84
	_     [120]byte
	RGCR0 volatile.Register32 // 0x100
	RGCR1 volatile.Register32 // 0x104
	RGCR2 volatile.Register32 // 0x108
	RGCR3 volatile.Register32 // 0x10C
	_     [48]byte
	RGSR  volatile.Register32 // 0x140
	RGCFR volatile.Register32 // 0x144
}

// DMAMUX.CCR0: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR0_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR0_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR0.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR0_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR0_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR0_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR0_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR0_SE(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR0_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR0_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR0_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR0_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR0_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR0_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR0_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR1: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR1_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR1_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR1_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR1_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR1_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR1_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR1_SE(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR1_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR1_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR1_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR1_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR1_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR1_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR1_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR2: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR2_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR2_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR2_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR2_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR2_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR2_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR2_SE(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR2_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR2_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR2_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR2_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR2_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR2_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR2_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR3: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR3_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR3_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR3.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR3_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR3_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR3_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR3_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR3_SE(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR3_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR3_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR3_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR3_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR3_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR3_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR3_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR4: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR4_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR4_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR4.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR4_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR4_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR4_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR4_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR4_SE(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR4_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR4_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR4_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR4_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR4_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR4_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR4_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR5: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR5_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR5_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR5.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR5_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR5_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR5_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR5_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR5_SE(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR5_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR5_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR5_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR5_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR5_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR5_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR5_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR6: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR6_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR6_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR6.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR6_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR6_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR6_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR6_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR6_SE(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR6_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR6_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR6_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR6_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR6_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR6_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR6_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR7: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR7_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR7_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR7.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR7_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR7_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR7_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR7_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR7_SE(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR7_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR7_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR7_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR7_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR7_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR7_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR7_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR8: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR8_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR8_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR8.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR8_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR8_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR8_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR8_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR8_SE(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR8_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR8_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR8_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR8_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR8_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR8_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR8_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR9: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR9_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR9_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR9.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR9_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR9_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR9_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR9_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR9_SE(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR9_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR9_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR9_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR9_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR9_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR9_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR9_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR10: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR10_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR10_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR10.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR10_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR10_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR10_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR10_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR10_SE(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR10_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR10_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR10_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR10_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR10_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR10_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR10_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CCR11: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR11_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x3f)|value)
}
func (o *DMAMUX_Type) GetCCR11_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR11.Reg) & 0x3f
}
func (o *DMAMUX_Type) SetCCR11_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR11_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR11_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR11_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR11_SE(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR11_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR11_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR11_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR11_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR11_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR11_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR11_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x1f000000) >> 24
}

// DMAMUX.CSR: DMAMUX request line multiplexer interrupt channel status register
func (o *DMAMUX_Type) SetCSR_SOF0(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetCSR_SOF0() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetCSR_SOF1(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetCSR_SOF1() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetCSR_SOF2(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetCSR_SOF2() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetCSR_SOF3(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetCSR_SOF3() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10) >> 4
}
func (o *DMAMUX_Type) SetCSR_SOF4(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20)|value<<5)
}
func (o *DMAMUX_Type) GetCSR_SOF4() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20) >> 5
}
func (o *DMAMUX_Type) SetCSR_SOF5(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40)|value<<6)
}
func (o *DMAMUX_Type) GetCSR_SOF5() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40) >> 6
}
func (o *DMAMUX_Type) SetCSR_SOF6(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80)|value<<7)
}
func (o *DMAMUX_Type) GetCSR_SOF6() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80) >> 7
}
func (o *DMAMUX_Type) SetCSR_SOF7(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCSR_SOF7() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCSR_SOF8(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCSR_SOF8() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCSR_SOF9(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x400)|value<<10)
}
func (o *DMAMUX_Type) GetCSR_SOF9() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x400) >> 10
}
func (o *DMAMUX_Type) SetCSR_SOF10(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800)|value<<11)
}
func (o *DMAMUX_Type) GetCSR_SOF10() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800) >> 11
}
func (o *DMAMUX_Type) SetCSR_SOF11(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAMUX_Type) GetCSR_SOF11() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x1000) >> 12
}

// DMAMUX.CFR: DMAMUX request line multiplexer interrupt clear flag register
func (o *DMAMUX_Type) SetCFR_CSOF0(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetCFR_CSOF0() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetCFR_CSOF1(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetCFR_CSOF1() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetCFR_CSOF2(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetCFR_CSOF2() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetCFR_CSOF3(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetCFR_CSOF3() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x10) >> 4
}
func (o *DMAMUX_Type) SetCFR_CSOF4(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x20)|value<<5)
}
func (o *DMAMUX_Type) GetCFR_CSOF4() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x20) >> 5
}
func (o *DMAMUX_Type) SetCFR_CSOF5(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x40)|value<<6)
}
func (o *DMAMUX_Type) GetCFR_CSOF5() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x40) >> 6
}
func (o *DMAMUX_Type) SetCFR_CSOF6(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x80)|value<<7)
}
func (o *DMAMUX_Type) GetCFR_CSOF6() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x80) >> 7
}
func (o *DMAMUX_Type) SetCFR_CSOF7(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCFR_CSOF7() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCFR_CSOF8(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCFR_CSOF8() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCFR_CSOF9(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x400)|value<<10)
}
func (o *DMAMUX_Type) GetCFR_CSOF9() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x400) >> 10
}
func (o *DMAMUX_Type) SetCFR_CSOF10(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x800)|value<<11)
}
func (o *DMAMUX_Type) GetCFR_CSOF10() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x800) >> 11
}
func (o *DMAMUX_Type) SetCFR_CSOF11(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAMUX_Type) GetCFR_CSOF11() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x1000) >> 12
}

// DMAMUX.RGCR0: DMAMUX request generator channel x configuration register
func (o *DMAMUX_Type) SetRGCR0_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR0_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR0.Reg) & 0x1f
}
func (o *DMAMUX_Type) SetRGCR0_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR0_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR0_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR0_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR0_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR0_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR0_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR0_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0xf80000) >> 19
}

// DMAMUX.RGCR1: DMAMUX request generator channel x configuration register
func (o *DMAMUX_Type) SetRGCR1_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR1_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR1.Reg) & 0x1f
}
func (o *DMAMUX_Type) SetRGCR1_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR1_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR1_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR1_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR1_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR1_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR1_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR1_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0xf80000) >> 19
}

// DMAMUX.RGCR2: DMAMUX request generator channel x configuration register
func (o *DMAMUX_Type) SetRGCR2_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR2_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR2.Reg) & 0x1f
}
func (o *DMAMUX_Type) SetRGCR2_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR2_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR2_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR2_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR2_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR2_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR2_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR2_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0xf80000) >> 19
}

// DMAMUX.RGCR3: DMAMUX request generator channel x configuration register
func (o *DMAMUX_Type) SetRGCR3_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR3_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR3.Reg) & 0x1f
}
func (o *DMAMUX_Type) SetRGCR3_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR3_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR3_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR3_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR3_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR3_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR3_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR3_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0xf80000) >> 19
}

// DMAMUX.RGSR: DMAMUX request generator interrupt status register
func (o *DMAMUX_Type) SetRGSR_OF0(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetRGSR_OF0() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetRGSR_OF1(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetRGSR_OF1() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetRGSR_OF2(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetRGSR_OF2() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetRGSR_OF3(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetRGSR_OF3() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x10) >> 4
}

// DMAMUX.RGCFR: DMAMUX request generator interrupt clear flag register
func (o *DMAMUX_Type) SetRGCFR_COF0(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetRGCFR_COF0() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetRGCFR_COF1(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetRGCFR_COF1() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetRGCFR_COF2(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetRGCFR_COF2() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetRGCFR_COF3(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetRGCFR_COF3() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x10) >> 4
}

// External interrupt/event controller
type EXTI_Type struct {
	RTSR1   volatile.Register32 // 0x0
	FTSR1   volatile.Register32 // 0x4
	SWIER1  volatile.Register32 // 0x8
	RPR1    volatile.Register32 // 0xC
	FPR1    volatile.Register32 // 0x10
	_       [76]byte
	EXTICR1 volatile.Register32 // 0x60
	EXTICR2 volatile.Register32 // 0x64
	EXTICR3 volatile.Register32 // 0x68
	EXTICR4 volatile.Register32 // 0x6C
	_       [16]byte
	IMR1    volatile.Register32 // 0x80
	EMR1    volatile.Register32 // 0x84
}

// EXTI.RTSR1: EXTI rising trigger selection register
func (o *EXTI_Type) SetRTSR1_RT0(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetRTSR1_RT0() uint32 {
	return volatile.LoadUint32(&o.RTSR1.Reg) & 0x1
}
func (o *EXTI_Type) SetRTSR1_RT1(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetRTSR1_RT1() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetRTSR1_RT2(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetRTSR1_RT2() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetRTSR1_RT3(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRTSR1_RT3() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRTSR1_RT4(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRTSR1_RT4() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRTSR1_RT5(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRTSR1_RT5() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRTSR1_RT6(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRTSR1_RT6() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetRTSR1_RT7(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetRTSR1_RT7() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetRTSR1_RT8(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetRTSR1_RT8() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetRTSR1_RT9(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetRTSR1_RT9() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetRTSR1_RT10(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetRTSR1_RT10() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetRTSR1_RT11(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetRTSR1_RT11() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetRTSR1_RT12(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetRTSR1_RT12() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetRTSR1_RT13(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetRTSR1_RT13() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetRTSR1_RT14(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetRTSR1_RT14() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetRTSR1_RT15(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetRTSR1_RT15() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x8000) >> 15
}

// EXTI.FTSR1: EXTI falling trigger selection register
func (o *EXTI_Type) SetFTSR1_FT0(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetFTSR1_FT0() uint32 {
	return volatile.LoadUint32(&o.FTSR1.Reg) & 0x1
}
func (o *EXTI_Type) SetFTSR1_FT1(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetFTSR1_FT1() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetFTSR1_FT2(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetFTSR1_FT2() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetFTSR1_FT3(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFTSR1_FT3() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFTSR1_FT4(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFTSR1_FT4() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFTSR1_FT5(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFTSR1_FT5() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFTSR1_FT6(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFTSR1_FT6() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetFTSR1_FT7(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetFTSR1_FT7() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetFTSR1_FT8(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetFTSR1_FT8() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetFTSR1_FT9(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetFTSR1_FT9() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetFTSR1_FT10(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetFTSR1_FT10() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetFTSR1_FT11(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetFTSR1_FT11() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetFTSR1_FT12(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetFTSR1_FT12() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetFTSR1_FT13(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetFTSR1_FT13() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetFTSR1_FT14(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetFTSR1_FT14() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetFTSR1_FT15(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetFTSR1_FT15() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x8000) >> 15
}

// EXTI.SWIER1: EXTI software interrupt event register
func (o *EXTI_Type) SetSWIER1_SWI0(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetSWIER1_SWI0() uint32 {
	return volatile.LoadUint32(&o.SWIER1.Reg) & 0x1
}
func (o *EXTI_Type) SetSWIER1_SWI1(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetSWIER1_SWI1() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetSWIER1_SWI2(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetSWIER1_SWI2() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetSWIER1_SWI3(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSWIER1_SWI3() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSWIER1_SWI4(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSWIER1_SWI4() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSWIER1_SWI5(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSWIER1_SWI5() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSWIER1_SWI6(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSWIER1_SWI6() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetSWIER1_SWI7(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetSWIER1_SWI7() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetSWIER1_SWI8(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetSWIER1_SWI8() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetSWIER1_SWI9(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetSWIER1_SWI9() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetSWIER1_SWI10(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetSWIER1_SWI10() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetSWIER1_SWI11(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetSWIER1_SWI11() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetSWIER1_SWI12(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetSWIER1_SWI12() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetSWIER1_SWI13(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetSWIER1_SWI13() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetSWIER1_SWI14(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetSWIER1_SWI14() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetSWIER1_SWI15(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetSWIER1_SWI15() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x8000) >> 15
}

// EXTI.RPR1: EXTI rising edge pending register
func (o *EXTI_Type) SetRPR1_RPIF0(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetRPR1_RPIF0() uint32 {
	return volatile.LoadUint32(&o.RPR1.Reg) & 0x1
}
func (o *EXTI_Type) SetRPR1_RPIF1(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetRPR1_RPIF1() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetRPR1_RPIF2(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetRPR1_RPIF2() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetRPR1_RPIF3(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRPR1_RPIF3() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRPR1_RPIF4(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRPR1_RPIF4() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRPR1_RPIF5(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRPR1_RPIF5() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRPR1_RPIF6(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRPR1_RPIF6() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetRPR1_RPIF7(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetRPR1_RPIF7() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetRPR1_RPIF8(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetRPR1_RPIF8() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetRPR1_RPIF9(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetRPR1_RPIF9() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetRPR1_RPIF10(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetRPR1_RPIF10() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetRPR1_RPIF11(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetRPR1_RPIF11() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetRPR1_RPIF12(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetRPR1_RPIF12() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetRPR1_RPIF13(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetRPR1_RPIF13() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetRPR1_RPIF14(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetRPR1_RPIF14() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetRPR1_RPIF15(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetRPR1_RPIF15() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x8000) >> 15
}

// EXTI.FPR1: EXTI falling edge pending register
func (o *EXTI_Type) SetFPR1_FPIF0(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetFPR1_FPIF0() uint32 {
	return volatile.LoadUint32(&o.FPR1.Reg) & 0x1
}
func (o *EXTI_Type) SetFPR1_FPIF1(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetFPR1_FPIF1() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetFPR1_FPIF2(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetFPR1_FPIF2() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetFPR1_FPIF3(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFPR1_FPIF3() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFPR1_FPIF4(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFPR1_FPIF4() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFPR1_FPIF5(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFPR1_FPIF5() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFPR1_FPIF6(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFPR1_FPIF6() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetFPR1_FPIF7(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetFPR1_FPIF7() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetFPR1_FPIF8(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetFPR1_FPIF8() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetFPR1_FPIF9(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetFPR1_FPIF9() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetFPR1_FPIF10(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetFPR1_FPIF10() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetFPR1_FPIF11(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetFPR1_FPIF11() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetFPR1_FPIF12(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetFPR1_FPIF12() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetFPR1_FPIF13(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetFPR1_FPIF13() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetFPR1_FPIF14(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetFPR1_FPIF14() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetFPR1_FPIF15(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetFPR1_FPIF15() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x8000) >> 15
}

// EXTI.EXTICR1: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR1_EXTI0(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR1_EXTI0() uint32 {
	return volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR1_EXTI1(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR1_EXTI1() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR1_EXTI2(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR1_EXTI2() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR1_EXTI3(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR1_EXTI3() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR2: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR2_EXTI4(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR2_EXTI4() uint32 {
	return volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR2_EXTI5(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR2_EXTI5() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR2_EXTI6(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR2_EXTI6() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR2_EXTI7(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR2_EXTI7() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR3: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR3_EXTI8(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR3_EXTI8() uint32 {
	return volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR3_EXTI9(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR3_EXTI9() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR3_EXTI10(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR3_EXTI10() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR3_EXTI11(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR3_EXTI11() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR4: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR4_EXTI12(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR4_EXTI12() uint32 {
	return volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR4_EXTI13(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR4_EXTI13() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR4_EXTI14(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR4_EXTI14() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR4_EXTI15(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR4_EXTI15() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff000000) >> 24
}

// EXTI.IMR1: EXTI CPU wakeup with interrupt mask register
func (o *EXTI_Type) SetIMR1_IM0(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetIMR1_IM0() uint32 {
	return volatile.LoadUint32(&o.IMR1.Reg) & 0x1
}
func (o *EXTI_Type) SetIMR1_IM1(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetIMR1_IM1() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetIMR1_IM2(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetIMR1_IM2() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetIMR1_IM3(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetIMR1_IM3() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetIMR1_IM4(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetIMR1_IM4() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetIMR1_IM5(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetIMR1_IM5() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetIMR1_IM6(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetIMR1_IM6() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetIMR1_IM7(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetIMR1_IM7() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetIMR1_IM8(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetIMR1_IM8() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetIMR1_IM9(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetIMR1_IM9() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetIMR1_IM10(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetIMR1_IM10() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetIMR1_IM11(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetIMR1_IM11() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetIMR1_IM12(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetIMR1_IM12() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetIMR1_IM13(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetIMR1_IM13() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetIMR1_IM14(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetIMR1_IM14() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetIMR1_IM15(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetIMR1_IM15() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetIMR1_IM19(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetIMR1_IM19() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetIMR1_IM21(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetIMR1_IM21() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetIMR1_IM22(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetIMR1_IM22() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetIMR1_IM23(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetIMR1_IM23() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetIMR1_IM24(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetIMR1_IM24() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetIMR1_IM25(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetIMR1_IM25() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2000000) >> 25
}
func (o *EXTI_Type) SetIMR1_IM26(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EXTI_Type) GetIMR1_IM26() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4000000) >> 26
}
func (o *EXTI_Type) SetIMR1_IM31(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80000000)|value<<31)
}
func (o *EXTI_Type) GetIMR1_IM31() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80000000) >> 31
}

// EXTI.EMR1: EXTI CPU wakeup with event mask register
func (o *EXTI_Type) SetEMR1_EM0(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetEMR1_EM0() uint32 {
	return volatile.LoadUint32(&o.EMR1.Reg) & 0x1
}
func (o *EXTI_Type) SetEMR1_EM1(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetEMR1_EM1() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetEMR1_EM2(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetEMR1_EM2() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetEMR1_EM3(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetEMR1_EM3() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetEMR1_EM4(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetEMR1_EM4() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetEMR1_EM5(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetEMR1_EM5() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetEMR1_EM6(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetEMR1_EM6() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetEMR1_EM7(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetEMR1_EM7() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetEMR1_EM8(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetEMR1_EM8() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetEMR1_EM9(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetEMR1_EM9() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetEMR1_EM10(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetEMR1_EM10() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetEMR1_EM11(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetEMR1_EM11() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetEMR1_EM12(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetEMR1_EM12() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetEMR1_EM13(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetEMR1_EM13() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetEMR1_EM14(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetEMR1_EM14() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetEMR1_EM15(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetEMR1_EM15() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetEMR1_EM19(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetEMR1_EM19() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetEMR1_EM21(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetEMR1_EM21() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetEMR1_EM23(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetEMR1_EM23() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetEMR1_EM25(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetEMR1_EM25() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2000000) >> 25
}
func (o *EXTI_Type) SetEMR1_EM26(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EXTI_Type) GetEMR1_EM26() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4000000) >> 26
}
func (o *EXTI_Type) SetEMR1_EM31(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80000000)|value<<31)
}
func (o *EXTI_Type) GetEMR1_EM31() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80000000) >> 31
}

// Flash
type Flash_Type struct {
	ACR     volatile.Register32 // 0x0
	_       [4]byte
	KEYR    volatile.Register32 // 0x8
	OPTKEYR volatile.Register32 // 0xC
	SR      volatile.Register32 // 0x10
	CR      volatile.Register32 // 0x14
	ECCR    volatile.Register32 // 0x18
	_       [4]byte
	OPTR    volatile.Register32 // 0x20
	_       [8]byte
	WRP1AR  volatile.Register32 // 0x2C
	WRP1BR  volatile.Register32 // 0x30
	_       [24]byte
	WRP2AR  volatile.Register32 // 0x4C
	WRP2BR  volatile.Register32 // 0x50
}

// Flash.ACR: Access control register
func (o *Flash_Type) SetACR_LATENCY(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x7)|value)
}
func (o *Flash_Type) GetACR_LATENCY() uint32 {
	return volatile.LoadUint32(&o.ACR.Reg) & 0x7
}
func (o *Flash_Type) SetACR_PRFTEN(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetACR_PRFTEN() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetACR_ICEN(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetACR_ICEN() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetACR_ICRST(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetACR_ICRST() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetACR_EMPTY(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetACR_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x10000) >> 16
}

// Flash.KEYR: Flash key register
func (o *Flash_Type) SetKEYR(value uint32) {
	volatile.StoreUint32(&o.KEYR.Reg, value)
}
func (o *Flash_Type) GetKEYR() uint32 {
	return volatile.LoadUint32(&o.KEYR.Reg)
}

// Flash.OPTKEYR: Option byte key register
func (o *Flash_Type) SetOPTKEYR(value uint32) {
	volatile.StoreUint32(&o.OPTKEYR.Reg, value)
}
func (o *Flash_Type) GetOPTKEYR() uint32 {
	return volatile.LoadUint32(&o.OPTKEYR.Reg)
}

// Flash.SR: Status register
func (o *Flash_Type) SetSR_EOP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSR_EOP() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *Flash_Type) SetSR_OPERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSR_OPERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSR_PROGERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSR_PROGERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSR_WRPERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSR_WRPERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSR_PGAERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSR_PGAERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSR_SIZERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSR_SIZERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSR_PGSERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSR_PGSERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSR_MISSERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSR_MISSERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSR_FASTERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSR_FASTERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSR_OPTVERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSR_OPTVERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSR_BSY1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSR_BSY1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSR_BSY2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSR_BSY2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSR_CFGBSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSR_CFGBSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000) >> 18
}

// Flash.CR: Flash control register
func (o *Flash_Type) SetCR_PG(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetCR_PG() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *Flash_Type) SetCR_PER(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetCR_PER() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetCR_MER1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetCR_MER1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetCR_PNB(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1ff8)|value<<3)
}
func (o *Flash_Type) GetCR_PNB() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1ff8) >> 3
}
func (o *Flash_Type) SetCR_BKER(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetCR_BKER() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetCR_MER2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetCR_MER2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetCR_STRT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetCR_STRT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetCR_OPTSTRT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetCR_OPTSTRT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetCR_FSTPG(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetCR_FSTPG() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetCR_EOPIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetCR_EOPIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetCR_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetCR_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetCR_OBL_LAUNCH(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetCR_OBL_LAUNCH() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetCR_OPTLOCK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetCR_OPTLOCK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetCR_LOCK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetCR_LOCK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// Flash.ECCR: Flash ECC register
func (o *Flash_Type) SetECCR_ADDR_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x3fff)|value)
}
func (o *Flash_Type) GetECCR_ADDR_ECC() uint32 {
	return volatile.LoadUint32(&o.ECCR.Reg) & 0x3fff
}
func (o *Flash_Type) SetECCR_SYSF_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetECCR_SYSF_ECC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetECCR_ECCIE(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetECCR_ECCIE() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetECCR_ECCC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetECCR_ECCC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetECCR_ECCD(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetECCR_ECCD() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x80000000) >> 31
}

// Flash.OPTR: Flash option register
func (o *Flash_Type) SetOPTR_RDP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetOPTR_RDP() uint32 {
	return volatile.LoadUint32(&o.OPTR.Reg) & 0xff
}
func (o *Flash_Type) SetOPTR_NRST_STOP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetOPTR_NRST_STOP() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetOPTR_NRST_STDBY(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetOPTR_NRST_STDBY() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetOPTR_IWDG_SW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetOPTR_IWDG_SW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetOPTR_IWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetOPTR_IWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetOPTR_IWDG_STDBY(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetOPTR_IWDG_STDBY() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetOPTR_WWDG_SW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetOPTR_WWDG_SW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetOPTR_NSWAP_BANK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetOPTR_NSWAP_BANK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetOPTR_DUAL_BANK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetOPTR_DUAL_BANK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetOPTR_RAM_PARITY_CHECK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetOPTR_RAM_PARITY_CHECK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetOPTR_NBOOT_SEL(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetOPTR_NBOOT_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetOPTR_NBOOT1(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetOPTR_NBOOT1() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetOPTR_NBOOT0(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetOPTR_NBOOT0() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x4000000) >> 26
}

// Flash.WRP1AR: Flash WRP area A address register
func (o *Flash_Type) SetWRP1AR_WRP1A_STRT(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP1AR_WRP1A_STRT() uint32 {
	return volatile.LoadUint32(&o.WRP1AR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP1AR_WRP1A_END(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP1AR_WRP1A_END() uint32 {
	return (volatile.LoadUint32(&o.WRP1AR.Reg) & 0x7f0000) >> 16
}

// Flash.WRP1BR: Flash WRP area B address register
func (o *Flash_Type) SetWRP1BR_WRP1B_STRT(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP1BR_WRP1B_STRT() uint32 {
	return volatile.LoadUint32(&o.WRP1BR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP1BR_WRP1B_END(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP1BR_WRP1B_END() uint32 {
	return (volatile.LoadUint32(&o.WRP1BR.Reg) & 0x7f0000) >> 16
}

// Flash.WRP2AR: FLASH WRP2 area A address register
func (o *Flash_Type) SetWRP2AR_WRP2A_STRT(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP2AR_WRP2A_STRT() uint32 {
	return volatile.LoadUint32(&o.WRP2AR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP2AR_WRP2A_END(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP2AR_WRP2A_END() uint32 {
	return (volatile.LoadUint32(&o.WRP2AR.Reg) & 0x7f0000) >> 16
}

// Flash.WRP2BR: FLASH WRP2 area B address register
func (o *Flash_Type) SetWRP2BR_WRP2B_STRT(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP2BR_WRP2B_STRT() uint32 {
	return volatile.LoadUint32(&o.WRP2BR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP2BR_WRP2B_END(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP2BR_WRP2B_END() uint32 {
	return (volatile.LoadUint32(&o.WRP2BR.Reg) & 0x7f0000) >> 16
}

// General-purpose I/Os
type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
	BRR     volatile.Register32 // 0x28
}

// GPIO.MODER: GPIO port mode register
func (o *GPIO_Type) SetMODER_MODER0(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetMODER_MODER0() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetMODER_MODER1(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetMODER_MODER1() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetMODER_MODER2(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetMODER_MODER2() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetMODER_MODER3(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetMODER_MODER3() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetMODER_MODER4(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetMODER_MODER4() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetMODER_MODER5(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetMODER_MODER5() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetMODER_MODER6(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetMODER_MODER6() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetMODER_MODER7(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetMODER_MODER7() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetMODER_MODER8(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetMODER_MODER8() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetMODER_MODER9(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetMODER_MODER9() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetMODER_MODER10(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetMODER_MODER10() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetMODER_MODER11(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetMODER_MODER11() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetMODER_MODER12(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetMODER_MODER12() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetMODER_MODER13(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetMODER_MODER13() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetMODER_MODER14(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetMODER_MODER14() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetMODER_MODER15(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetMODER_MODER15() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x0) >> 32
}

// GPIO.OTYPER: GPIO port output type register
func (o *GPIO_Type) SetOTYPER_OT0(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetOTYPER_OT0() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetOTYPER_OT1(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetOTYPER_OT1() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetOTYPER_OT2(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetOTYPER_OT2() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetOTYPER_OT3(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetOTYPER_OT3() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetOTYPER_OT4(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetOTYPER_OT4() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetOTYPER_OT5(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetOTYPER_OT5() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetOTYPER_OT6(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetOTYPER_OT6() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetOTYPER_OT7(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetOTYPER_OT7() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetOTYPER_OT8(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetOTYPER_OT8() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetOTYPER_OT9(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetOTYPER_OT9() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetOTYPER_OT10(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetOTYPER_OT10() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetOTYPER_OT11(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetOTYPER_OT11() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetOTYPER_OT12(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetOTYPER_OT12() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetOTYPER_OT13(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetOTYPER_OT13() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetOTYPER_OT14(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetOTYPER_OT14() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetOTYPER_OT15(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetOTYPER_OT15() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10000) >> 16
}

// GPIO.OSPEEDR: GPIO port output speed register
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR0(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR0() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR1(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR1() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR2(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR2() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR3(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR3() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR4(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR4() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR5(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR5() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR6(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR6() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR7(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR7() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR8(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR8() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR9(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR9() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR10(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR10() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR11(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR11() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR12(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR12() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR13(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR13() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR14(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR14() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR15(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR15() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x0) >> 32
}

// GPIO.PUPDR: GPIO port pull-up/pull-down register
func (o *GPIO_Type) SetPUPDR_PUPDR0(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetPUPDR_PUPDR0() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetPUPDR_PUPDR1(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetPUPDR_PUPDR1() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetPUPDR_PUPDR2(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetPUPDR_PUPDR2() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetPUPDR_PUPDR3(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetPUPDR_PUPDR3() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetPUPDR_PUPDR4(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetPUPDR_PUPDR4() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetPUPDR_PUPDR5(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetPUPDR_PUPDR5() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetPUPDR_PUPDR6(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetPUPDR_PUPDR6() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetPUPDR_PUPDR7(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetPUPDR_PUPDR7() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetPUPDR_PUPDR8(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetPUPDR_PUPDR8() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetPUPDR_PUPDR9(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetPUPDR_PUPDR9() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetPUPDR_PUPDR10(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetPUPDR_PUPDR10() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetPUPDR_PUPDR11(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetPUPDR_PUPDR11() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetPUPDR_PUPDR12(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetPUPDR_PUPDR12() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetPUPDR_PUPDR13(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetPUPDR_PUPDR13() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetPUPDR_PUPDR14(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetPUPDR_PUPDR14() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetPUPDR_PUPDR15(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetPUPDR_PUPDR15() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x0) >> 32
}

// GPIO.IDR: GPIO port input data register
func (o *GPIO_Type) SetIDR_IDR0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetIDR_IDR0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetIDR_IDR1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetIDR_IDR1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetIDR_IDR2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetIDR_IDR2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetIDR_IDR3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetIDR_IDR3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetIDR_IDR4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetIDR_IDR4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetIDR_IDR5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetIDR_IDR5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetIDR_IDR6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetIDR_IDR6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetIDR_IDR7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetIDR_IDR7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetIDR_IDR8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetIDR_IDR8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetIDR_IDR9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetIDR_IDR9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetIDR_IDR10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetIDR_IDR10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetIDR_IDR11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetIDR_IDR11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetIDR_IDR12(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetIDR_IDR12() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetIDR_IDR13(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetIDR_IDR13() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetIDR_IDR14(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetIDR_IDR14() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetIDR_IDR15(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetIDR_IDR15() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}

// GPIO.ODR: GPIO port output data register
func (o *GPIO_Type) SetODR_ODR0(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetODR_ODR0() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetODR_ODR1(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetODR_ODR1() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetODR_ODR2(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetODR_ODR2() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetODR_ODR3(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetODR_ODR3() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetODR_ODR4(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetODR_ODR4() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetODR_ODR5(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetODR_ODR5() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetODR_ODR6(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetODR_ODR6() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetODR_ODR7(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetODR_ODR7() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetODR_ODR8(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetODR_ODR8() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetODR_ODR9(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetODR_ODR9() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetODR_ODR10(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetODR_ODR10() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetODR_ODR11(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetODR_ODR11() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetODR_ODR12(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetODR_ODR12() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetODR_ODR13(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetODR_ODR13() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetODR_ODR14(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetODR_ODR14() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetODR_ODR15(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetODR_ODR15() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10000) >> 16
}

// GPIO.BSRR: GPIO port bit set/reset register
func (o *GPIO_Type) SetBSRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000)|value<<17)
}
func (o *GPIO_Type) GetBSRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000) >> 17
}
func (o *GPIO_Type) SetBSRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000)|value<<18)
}
func (o *GPIO_Type) GetBSRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000) >> 18
}
func (o *GPIO_Type) SetBSRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000)|value<<19)
}
func (o *GPIO_Type) GetBSRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000) >> 19
}
func (o *GPIO_Type) SetBSRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100000)|value<<20)
}
func (o *GPIO_Type) GetBSRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100000) >> 20
}
func (o *GPIO_Type) SetBSRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200000)|value<<21)
}
func (o *GPIO_Type) GetBSRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200000) >> 21
}
func (o *GPIO_Type) SetBSRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400000)|value<<22)
}
func (o *GPIO_Type) GetBSRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400000) >> 22
}
func (o *GPIO_Type) SetBSRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800000)|value<<23)
}
func (o *GPIO_Type) GetBSRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800000) >> 23
}
func (o *GPIO_Type) SetBSRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIO_Type) GetBSRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000000) >> 24
}
func (o *GPIO_Type) SetBSRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000000)|value<<25)
}
func (o *GPIO_Type) GetBSRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000000) >> 25
}
func (o *GPIO_Type) SetBSRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000000)|value<<26)
}
func (o *GPIO_Type) GetBSRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000000) >> 26
}
func (o *GPIO_Type) SetBSRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000000)|value<<27)
}
func (o *GPIO_Type) GetBSRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000000) >> 27
}
func (o *GPIO_Type) SetBSRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000000)|value<<28)
}
func (o *GPIO_Type) GetBSRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000000) >> 28
}
func (o *GPIO_Type) SetBSRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPIO_Type) GetBSRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000000) >> 29
}
func (o *GPIO_Type) SetBSRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000000)|value<<30)
}
func (o *GPIO_Type) GetBSRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000000) >> 30
}
func (o *GPIO_Type) SetBSRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPIO_Type) GetBSRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000000) >> 31
}
func (o *GPIO_Type) SetBSRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetBSRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x0) >> 32
}
func (o *GPIO_Type) SetBSRR_BS0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBSRR_BS0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBSRR_BS1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBSRR_BS1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBSRR_BS2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBSRR_BS2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBSRR_BS3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBSRR_BS3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBSRR_BS4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBSRR_BS4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBSRR_BS5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBSRR_BS5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBSRR_BS6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBSRR_BS6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBSRR_BS7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBSRR_BS7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBSRR_BS8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBSRR_BS8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBSRR_BS9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBSRR_BS9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBSRR_BS10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBSRR_BS10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBSRR_BS11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBSRR_BS11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBSRR_BS12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetBSRR_BS12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetBSRR_BS13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetBSRR_BS13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetBSRR_BS14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetBSRR_BS14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetBSRR_BS15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetBSRR_BS15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000) >> 16
}

// GPIO.LCKR: GPIO port configuration lock register
func (o *GPIO_Type) SetLCKR_LCKK(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCKK() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}
func (o *GPIO_Type) SetLCKR_LCK0(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetLCKR_LCK0() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetLCKR_LCK1(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetLCKR_LCK1() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetLCKR_LCK2(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetLCKR_LCK2() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetLCKR_LCK3(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetLCKR_LCK3() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetLCKR_LCK4(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetLCKR_LCK4() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetLCKR_LCK5(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetLCKR_LCK5() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetLCKR_LCK6(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetLCKR_LCK6() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetLCKR_LCK7(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetLCKR_LCK7() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetLCKR_LCK8(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetLCKR_LCK8() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetLCKR_LCK9(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetLCKR_LCK9() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetLCKR_LCK10(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetLCKR_LCK10() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetLCKR_LCK11(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetLCKR_LCK11() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetLCKR_LCK12(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetLCKR_LCK12() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetLCKR_LCK13(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetLCKR_LCK13() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetLCKR_LCK14(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetLCKR_LCK14() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetLCKR_LCK15(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCK15() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}

// GPIO.AFRL: GPIO alternate function low register
func (o *GPIO_Type) SetAFRL_AFREL0(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRL_AFREL0() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRL_AFREL1(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRL_AFREL1() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRL_AFREL2(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRL_AFREL2() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRL_AFREL3(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRL_AFREL3() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000) >> 16
}
func (o *GPIO_Type) SetAFRL_AFREL4(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00000)|value<<20)
}
func (o *GPIO_Type) GetAFRL_AFREL4() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00000) >> 20
}
func (o *GPIO_Type) SetAFRL_AFREL5(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000000)|value<<24)
}
func (o *GPIO_Type) GetAFRL_AFREL5() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000000) >> 24
}
func (o *GPIO_Type) SetAFRL_AFREL6(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000000)|value<<28)
}
func (o *GPIO_Type) GetAFRL_AFREL6() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000000) >> 28
}
func (o *GPIO_Type) SetAFRL_AFREL7(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetAFRL_AFREL7() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0x0) >> 32
}

// GPIO.AFRH: GPIO alternate function high register
func (o *GPIO_Type) SetAFRH_AFREL8(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRH_AFREL8() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRH_AFREL9(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRH_AFREL9() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRH_AFREL10(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRH_AFREL10() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRH_AFREL11(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRH_AFREL11() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000) >> 16
}
func (o *GPIO_Type) SetAFRH_AFREL12(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00000)|value<<20)
}
func (o *GPIO_Type) GetAFRH_AFREL12() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00000) >> 20
}
func (o *GPIO_Type) SetAFRH_AFREL13(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000000)|value<<24)
}
func (o *GPIO_Type) GetAFRH_AFREL13() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000000) >> 24
}
func (o *GPIO_Type) SetAFRH_AFREL14(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000000)|value<<28)
}
func (o *GPIO_Type) GetAFRH_AFREL14() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000000) >> 28
}
func (o *GPIO_Type) SetAFRH_AFREL15(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetAFRH_AFREL15() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0x0) >> 32
}

// GPIO.BRR: port bit reset register
func (o *GPIO_Type) SetBRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetBRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetBRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetBRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetBRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetBRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetBRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetBRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10000) >> 16
}

// Inter-integrated circuit
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
}

// I2C.CR1: Control register 1
func (o *I2C_Type) SetCR1_PE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetCR1_PE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *I2C_Type) SetCR1_TXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetCR1_TXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetCR1_RXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetCR1_RXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetCR1_ADDRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetCR1_ADDRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetCR1_NACKIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetCR1_NACKIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetCR1_STOPIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetCR1_STOPIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetCR1_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetCR1_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetCR1_DNF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xf00)|value<<8)
}
func (o *I2C_Type) GetCR1_DNF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xf00) >> 8
}
func (o *I2C_Type) SetCR1_ANFOFF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR1_ANFOFF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR1_SBC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetCR1_SBC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetCR1_NOSTRETCH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetCR1_NOSTRETCH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetCR1_WUPEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetCR1_WUPEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *I2C_Type) SetCR1_GCEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *I2C_Type) GetCR1_GCEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *I2C_Type) SetCR1_SMBHEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *I2C_Type) GetCR1_SMBHEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *I2C_Type) SetCR1_SMBDEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *I2C_Type) GetCR1_SMBDEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}
func (o *I2C_Type) SetCR1_ALERTEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400000)|value<<22)
}
func (o *I2C_Type) GetCR1_ALERTEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400000) >> 22
}
func (o *I2C_Type) SetCR1_PECEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800000)|value<<23)
}
func (o *I2C_Type) GetCR1_PECEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800000) >> 23
}

// I2C.CR2: Control register 2
func (o *I2C_Type) SetCR2_SADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetCR2_SADD() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x3ff
}
func (o *I2C_Type) SetCR2_RD_WRN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetCR2_RD_WRN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetCR2_ADD10(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetCR2_ADD10() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetCR2_HEAD10R(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR2_HEAD10R() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR2_START(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetCR2_START() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR2_NACK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR2_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR2_NBYTES(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff0000)|value<<16)
}
func (o *I2C_Type) GetCR2_NBYTES() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff0000) >> 16
}
func (o *I2C_Type) SetCR2_RELOAD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *I2C_Type) GetCR2_RELOAD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *I2C_Type) SetCR2_AUTOEND(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *I2C_Type) GetCR2_AUTOEND() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *I2C_Type) SetCR2_PECBYTE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *I2C_Type) GetCR2_PECBYTE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}

// I2C.OAR1: Own address register 1
func (o *I2C_Type) SetOAR1_OA1(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetOAR1_OA1() uint32 {
	return volatile.LoadUint32(&o.OAR1.Reg) & 0x3ff
}
func (o *I2C_Type) SetOAR1_OA1MODE(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetOAR1_OA1MODE() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetOAR1_OA1EN(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR1_OA1EN() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x8000) >> 15
}

// I2C.OAR2: Own address register 2
func (o *I2C_Type) SetOAR2_OA2(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0xfe)|value<<1)
}
func (o *I2C_Type) GetOAR2_OA2() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0xfe) >> 1
}
func (o *I2C_Type) SetOAR2_OA2MSK(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x700)|value<<8)
}
func (o *I2C_Type) GetOAR2_OA2MSK() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x700) >> 8
}
func (o *I2C_Type) SetOAR2_OA2EN(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR2_OA2EN() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x8000) >> 15
}

// I2C.TIMINGR: Timing register
func (o *I2C_Type) SetTIMINGR_SCLL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTIMINGR_SCLL() uint32 {
	return volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff
}
func (o *I2C_Type) SetTIMINGR_SCLH(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff00)|value<<8)
}
func (o *I2C_Type) GetTIMINGR_SCLH() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff00) >> 8
}
func (o *I2C_Type) SetTIMINGR_SDADEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000)|value<<16)
}
func (o *I2C_Type) GetTIMINGR_SDADEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000) >> 16
}
func (o *I2C_Type) SetTIMINGR_SCLDEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf00000)|value<<20)
}
func (o *I2C_Type) GetTIMINGR_SCLDEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf00000) >> 20
}
func (o *I2C_Type) SetTIMINGR_PRESC(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000000)|value<<28)
}
func (o *I2C_Type) GetTIMINGR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000000) >> 28
}

// I2C.TIMEOUTR: Status register 1
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTA(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff)|value)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTA() uint32 {
	return volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff
}
func (o *I2C_Type) SetTIMEOUTR_TIDLE(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetTIMEOUTR_TIDLE() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetTIMEOUTR_TIMOUTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetTIMEOUTR_TIMOUTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTB(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff0000)|value<<16)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTB() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff0000) >> 16
}
func (o *I2C_Type) SetTIMEOUTR_TEXTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetTIMEOUTR_TEXTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x80000000) >> 31
}

// I2C.ISR: Interrupt and Status register
func (o *I2C_Type) SetISR_ADDCODE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xfe0000)|value<<17)
}
func (o *I2C_Type) GetISR_ADDCODE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xfe0000) >> 17
}
func (o *I2C_Type) SetISR_DIR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetISR_DIR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetISR_ALERT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetISR_ALERT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetISR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetISR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetISR_PECERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetISR_PECERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetISR_ARLO(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetISR_ARLO() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetISR_BERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetISR_BERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetISR_TCR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetISR_TCR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetISR_STOPF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetISR_STOPF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetISR_NACKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetISR_NACKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetISR_ADDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetISR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetISR_TXIS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetISR_TXIS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetISR_TXE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// I2C.ICR: Interrupt clear register
func (o *I2C_Type) SetICR_ALERTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetICR_ALERTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetICR_TIMOUTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetICR_TIMOUTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetICR_PECCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetICR_PECCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetICR_OVRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetICR_OVRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetICR_ARLOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetICR_ARLOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetICR_BERRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetICR_BERRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetICR_STOPCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetICR_STOPCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetICR_NACKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetICR_NACKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetICR_ADDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetICR_ADDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}

// I2C.PECR: PEC register
func (o *I2C_Type) SetPECR_PEC(value uint32) {
	volatile.StoreUint32(&o.PECR.Reg, volatile.LoadUint32(&o.PECR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetPECR_PEC() uint32 {
	return volatile.LoadUint32(&o.PECR.Reg) & 0xff
}

// I2C.RXDR: Receive data register
func (o *I2C_Type) SetRXDR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, volatile.LoadUint32(&o.RXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetRXDR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg) & 0xff
}

// I2C.TXDR: Transmit data register
func (o *I2C_Type) SetTXDR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, volatile.LoadUint32(&o.TXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTXDR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg) & 0xff
}

// Independent watchdog
type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
}

// IWDG.KR: Key register
func (o *IWDG_Type) SetKR_KEY(value uint32) {
	volatile.StoreUint32(&o.KR.Reg, volatile.LoadUint32(&o.KR.Reg)&^(0xffff)|value)
}
func (o *IWDG_Type) GetKR_KEY() uint32 {
	return volatile.LoadUint32(&o.KR.Reg) & 0xffff
}

// IWDG.PR: Prescaler register
func (o *IWDG_Type) SetPR(value uint32) {
	volatile.StoreUint32(&o.PR.Reg, volatile.LoadUint32(&o.PR.Reg)&^(0x7)|value)
}
func (o *IWDG_Type) GetPR() uint32 {
	return volatile.LoadUint32(&o.PR.Reg) & 0x7
}

// IWDG.RLR: Reload register
func (o *IWDG_Type) SetRLR_RL(value uint32) {
	volatile.StoreUint32(&o.RLR.Reg, volatile.LoadUint32(&o.RLR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetRLR_RL() uint32 {
	return volatile.LoadUint32(&o.RLR.Reg) & 0xfff
}

// IWDG.SR: Status register
func (o *IWDG_Type) SetSR_PVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *IWDG_Type) GetSR_PVU() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *IWDG_Type) SetSR_RVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *IWDG_Type) GetSR_RVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *IWDG_Type) SetSR_WVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *IWDG_Type) GetSR_WVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}

// IWDG.WINR: Window register
func (o *IWDG_Type) SetWINR_WIN(value uint32) {
	volatile.StoreUint32(&o.WINR.Reg, volatile.LoadUint32(&o.WINR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetWINR_WIN() uint32 {
	return volatile.LoadUint32(&o.WINR.Reg) & 0xfff
}

// Power control
type PWR_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	CR4   volatile.Register32 // 0xC
	SR1   volatile.Register32 // 0x10
	SR2   volatile.Register32 // 0x14
	SCR   volatile.Register32 // 0x18
	_     [4]byte
	PUCRA volatile.Register32 // 0x20
	PDCRA volatile.Register32 // 0x24
	PUCRB volatile.Register32 // 0x28
	PDCRB volatile.Register32 // 0x2C
	PUCRC volatile.Register32 // 0x30
	PDCRC volatile.Register32 // 0x34
	PUCRD volatile.Register32 // 0x38
	PDCRD volatile.Register32 // 0x3C
	PUCRE volatile.Register32 // 0x40
	PDCRE volatile.Register32 // 0x44
	PUCRF volatile.Register32 // 0x48
	PDCRF volatile.Register32 // 0x4C
}

// PWR.CR1: Power control register 1
func (o *PWR_Type) SetCR1_LPR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetCR1_LPR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetCR1_VOS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x600)|value<<9)
}
func (o *PWR_Type) GetCR1_VOS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x600) >> 9
}
func (o *PWR_Type) SetCR1_DBP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR1_DBP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR1_FPD_LPSLP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR1_FPD_LPSLP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR1_FPD_LPRUN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR1_FPD_LPRUN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR1_FPD_STOP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetCR1_FPD_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetCR1_LPMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x7)|value)
}
func (o *PWR_Type) GetCR1_LPMS() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x7
}

// PWR.CR2: Power control register 2
func (o *PWR_Type) SetCR2_USV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR2_USV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}

// PWR.CR3: Power control register 3
func (o *PWR_Type) SetCR3_EWUP1(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR3_EWUP1() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *PWR_Type) SetCR3_EWUP2(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR3_EWUP2() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR3_EWUP3(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR3_EWUP3() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetCR3_EWUP4(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetCR3_EWUP4() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetCR3_EWUP5(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR3_EWUP5() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR3_EWUP6(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR3_EWUP6() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR3_APC(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR3_APC() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetCR3_EIWUL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetCR3_EIWUL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}

// PWR.CR4: Power control register 4
func (o *PWR_Type) SetCR4_WP1(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR4_WP1() uint32 {
	return volatile.LoadUint32(&o.CR4.Reg) & 0x1
}
func (o *PWR_Type) SetCR4_WP2(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR4_WP2() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR4_WP3(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR4_WP3() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetCR4_WP4(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetCR4_WP4() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetCR4_WP5(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR4_WP5() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR4_WP6(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR4_WP6() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR4_VBE(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR4_VBE() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR4_VBRS(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetCR4_VBRS() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x200) >> 9
}

// PWR.SR1: Power status register 1
func (o *PWR_Type) SetSR1_WUF1(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSR1_WUF1() uint32 {
	return volatile.LoadUint32(&o.SR1.Reg) & 0x1
}
func (o *PWR_Type) SetSR1_WUF2(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSR1_WUF2() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSR1_WUF3(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSR1_WUF3() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetSR1_WUF4(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetSR1_WUF4() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetSR1_WUF5(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSR1_WUF5() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSR1_WUF6(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetSR1_WUF6() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetSR1_SBF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSR1_SBF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetSR1_WUFI(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetSR1_WUFI() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8000) >> 15
}

// PWR.SR2: Power status register 2
func (o *PWR_Type) SetSR2_VOSF(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetSR2_VOSF() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetSR2_REGLPF(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetSR2_REGLPF() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetSR2_REGLPS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSR2_REGLPS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetSR2_FLASH_RDY(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetSR2_FLASH_RDY() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x80) >> 7
}

// PWR.SCR: Power status clear register
func (o *PWR_Type) SetSCR_CSBF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSCR_CSBF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetSCR_CWUF6(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetSCR_CWUF6() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetSCR_CWUF5(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSCR_CWUF5() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSCR_CWUF4(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetSCR_CWUF4() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetSCR_CWUF3(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSCR_CWUF3() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetSCR_CWUF2(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSCR_CWUF2() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSCR_CWUF1(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSCR_CWUF1() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}

// PWR.PUCRA: Power Port A pull-up control register
func (o *PWR_Type) SetPUCRA_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRA_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRA_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRA_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRA_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRA_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRA_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRA_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRA_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRA_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRA_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRA_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRA_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRA_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRA_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRA_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRA_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRA_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRA_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRA_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRA_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRA_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRA_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRA_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRA_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRA_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRA_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRA_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRA_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRA_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRA_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRA_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRA.Reg) & 0x1
}

// PWR.PDCRA: Power Port A pull-down control register
func (o *PWR_Type) SetPDCRA_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRA_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRA_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRA_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRA_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRA_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRA_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRA_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRA_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRA_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRA_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRA_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRA_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRA_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRA_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRA_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRA_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRA_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRA_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRA_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRA_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRA_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRA_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRA_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRA_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRA_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRA_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRA_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRA_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRA_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRA_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRA_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRA.Reg) & 0x1
}

// PWR.PUCRB: Power Port B pull-up control register
func (o *PWR_Type) SetPUCRB_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRB_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRB_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRB_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRB_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRB_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRB_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRB_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRB_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRB_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRB_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRB_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRB_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRB_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRB_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRB_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRB_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRB_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRB_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRB_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRB_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRB_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRB_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRB_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRB_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRB_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRB_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRB_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRB_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRB_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRB_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRB_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRB.Reg) & 0x1
}

// PWR.PDCRB: Power Port B pull-down control register
func (o *PWR_Type) SetPDCRB_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRB_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRB_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRB_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRB_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRB_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRB_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRB_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRB_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRB_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRB_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRB_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRB_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRB_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRB_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRB_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRB_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRB_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRB_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRB_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRB_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRB_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRB_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRB_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRB_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRB_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRB_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRB_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRB_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRB_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRB_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRB_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRB.Reg) & 0x1
}

// PWR.PUCRC: Power Port C pull-up control register
func (o *PWR_Type) SetPUCRC_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRC_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRC_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRC_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRC_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRC_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRC_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRC_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRC_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRC_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRC_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRC_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRC_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRC_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRC_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRC_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRC_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRC_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRC_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRC_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRC_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRC_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRC_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRC_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRC_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRC_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRC_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRC_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRC_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRC_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRC_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRC_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRC.Reg) & 0x1
}

// PWR.PDCRC: Power Port C pull-down control register
func (o *PWR_Type) SetPDCRC_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRC_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRC_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRC_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRC_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRC_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRC_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRC_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRC_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRC_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRC_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRC_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRC_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRC_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRC_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRC_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRC_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRC_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRC_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRC_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRC_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRC_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRC_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRC_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRC_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRC_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRC_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRC_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRC_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRC_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRC_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRC_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRC.Reg) & 0x1
}

// PWR.PUCRD: Power Port D pull-up control register
func (o *PWR_Type) SetPUCRD_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRD_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRD_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRD_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRD_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRD_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRD_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRD_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRD_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRD_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRD_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRD_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRD_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRD_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRD_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRD_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRD_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRD_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRD_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRD_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRD_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRD_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRD_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRD_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRD_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRD_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRD_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRD_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRD_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRD_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRD_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRD_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRD.Reg) & 0x1
}

// PWR.PDCRD: Power Port D pull-down control register
func (o *PWR_Type) SetPDCRD_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRD_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRD_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRD_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRD_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRD_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRD_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRD_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRD_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRD_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRD_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRD_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRD_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRD_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRD_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRD_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRD_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRD_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRD_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRD_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRD_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRD_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRD_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRD_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRD_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRD_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRD_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRD_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRD_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRD_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRD_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRD_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRD.Reg) & 0x1
}

// PWR.PUCRE: Power Port E pull-UP control register
func (o *PWR_Type) SetPUCRE_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRE_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRE_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRE_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRE_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRE_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRE_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRE_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRE_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRE_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRE_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRE_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRE_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRE_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRE_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRE_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRE_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRE_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRE_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRE_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRE_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRE_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRE_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRE_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRE_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRE_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRE_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRE_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRE_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRE_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRE_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRE_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRE.Reg) & 0x1
}

// PWR.PDCRE: Power Port E pull-down control register
func (o *PWR_Type) SetPDCRE_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRE_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRE_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRE_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRE_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRE_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRE_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRE_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRE_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRE_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRE_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRE_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRE_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRE_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRE_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRE_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRE_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRE_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRE_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRE_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRE_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRE_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRE_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRE_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRE_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRE_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRE_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRE_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRE_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRE_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRE_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRE_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRE.Reg) & 0x1
}

// PWR.PUCRF: Power Port F pull-up control register
func (o *PWR_Type) SetPUCRF_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRF_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRF_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRF_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRF_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRF_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRF_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRF_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRF_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRF_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRF_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRF_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRF_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRF_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRF_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRF_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRF_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRF_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRF_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRF_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRF_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRF_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRF_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRF_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRF_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRF_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRF_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRF_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRF.Reg) & 0x1
}

// PWR.PDCRF: Power Port F pull-down control register
func (o *PWR_Type) SetPDCRF_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRF_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRF_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRF_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRF_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRF_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRF_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRF_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRF_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRF_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRF_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRF_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRF_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRF_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRF_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRF_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRF_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRF_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRF_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRF_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRF_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRF_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRF_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRF_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRF_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRF_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRF_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRF_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRF.Reg) & 0x1
}

// Reset and clock control
type RCC_Type struct {
	CR        volatile.Register32 // 0x0
	ICSCR     volatile.Register32 // 0x4
	CFGR      volatile.Register32 // 0x8
	PLLCFGR   volatile.Register32 // 0xC
	_         [8]byte
	CIER      volatile.Register32 // 0x18
	CIFR      volatile.Register32 // 0x1C
	CICR      volatile.Register32 // 0x20
	IOPRSTR   volatile.Register32 // 0x24
	AHBRSTR   volatile.Register32 // 0x28
	APBRSTR1  volatile.Register32 // 0x2C
	APBRSTR2  volatile.Register32 // 0x30
	IOPENR    volatile.Register32 // 0x34
	AHBENR    volatile.Register32 // 0x38
	APBENR1   volatile.Register32 // 0x3C
	APBENR2   volatile.Register32 // 0x40
	IOPSMENR  volatile.Register32 // 0x44
	AHBSMENR  volatile.Register32 // 0x48
	APBSMENR1 volatile.Register32 // 0x4C
	APBSMENR2 volatile.Register32 // 0x50
	CCIPR     volatile.Register32 // 0x54
	_         [4]byte
	BDCR      volatile.Register32 // 0x5C
	CSR       volatile.Register32 // 0x60
}

// RCC.CR: Clock control register
func (o *RCC_Type) SetCR_HSION(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCR_HSION() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCR_HSIKERON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCR_HSIKERON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetCR_HSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCR_HSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetCR_HSIDIV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3800)|value<<11)
}
func (o *RCC_Type) GetCR_HSIDIV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3800) >> 11
}
func (o *RCC_Type) SetCR_HSEON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetCR_HSEON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetCR_HSERDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCR_HSERDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetCR_HSEBYP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetCR_HSEBYP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetCR_CSSON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetCR_CSSON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetCR_PLLON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetCR_PLLON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetCR_PLLRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetCR_PLLRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}

// RCC.ICSCR: Internal clock sources calibration register
func (o *RCC_Type) SetICSCR_HSICAL(value uint32) {
	volatile.StoreUint32(&o.ICSCR.Reg, volatile.LoadUint32(&o.ICSCR.Reg)&^(0xff)|value)
}
func (o *RCC_Type) GetICSCR_HSICAL() uint32 {
	return volatile.LoadUint32(&o.ICSCR.Reg) & 0xff
}
func (o *RCC_Type) SetICSCR_HSITRIM(value uint32) {
	volatile.StoreUint32(&o.ICSCR.Reg, volatile.LoadUint32(&o.ICSCR.Reg)&^(0x7f00)|value<<8)
}
func (o *RCC_Type) GetICSCR_HSITRIM() uint32 {
	return (volatile.LoadUint32(&o.ICSCR.Reg) & 0x7f00) >> 8
}

// RCC.CFGR: Clock configuration register
func (o *RCC_Type) SetCFGR_MCOPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xf0000000)|value<<28)
}
func (o *RCC_Type) GetCFGR_MCOPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xf0000000) >> 28
}
func (o *RCC_Type) SetCFGR_MCOSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xf000000)|value<<24)
}
func (o *RCC_Type) GetCFGR_MCOSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xf000000) >> 24
}
func (o *RCC_Type) SetCFGR_PPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x7000)|value<<12)
}
func (o *RCC_Type) GetCFGR_PPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x7000) >> 12
}
func (o *RCC_Type) SetCFGR_HPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xf00)|value<<8)
}
func (o *RCC_Type) GetCFGR_HPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xf00) >> 8
}
func (o *RCC_Type) SetCFGR_SWS(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x38)|value<<3)
}
func (o *RCC_Type) GetCFGR_SWS() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x38) >> 3
}
func (o *RCC_Type) SetCFGR_SW(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x7)|value)
}
func (o *RCC_Type) GetCFGR_SW() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0x7
}

// RCC.PLLCFGR: PLL configuration register
func (o *RCC_Type) SetPLLCFGR_PLLSRC(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLLCFGR_PLLSRC() uint32 {
	return volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x3
}
func (o *RCC_Type) SetPLLCFGR_PLLM(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x70)|value<<4)
}
func (o *RCC_Type) GetPLLCFGR_PLLM() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x70) >> 4
}
func (o *RCC_Type) SetPLLCFGR_PLLN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0xff00)|value<<8)
}
func (o *RCC_Type) GetPLLCFGR_PLLN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0xff00) >> 8
}
func (o *RCC_Type) SetPLLCFGR_PLLPEN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLLCFGR_PLLPEN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLLCFGR_PLLP(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x3e0000)|value<<17)
}
func (o *RCC_Type) GetPLLCFGR_PLLP() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x3e0000) >> 17
}
func (o *RCC_Type) SetPLLCFGR_PLLQEN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetPLLCFGR_PLLQEN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetPLLCFGR_PLLQ(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0xe000000)|value<<25)
}
func (o *RCC_Type) GetPLLCFGR_PLLQ() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0xe000000) >> 25
}
func (o *RCC_Type) SetPLLCFGR_PLLREN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetPLLCFGR_PLLREN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetPLLCFGR_PLLR(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0xe0000000)|value<<29)
}
func (o *RCC_Type) GetPLLCFGR_PLLR() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0xe0000000) >> 29
}

// RCC.CIER: Clock interrupt enable register
func (o *RCC_Type) SetCIER_LSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIER_LSIRDYIE() uint32 {
	return volatile.LoadUint32(&o.CIER.Reg) & 0x1
}
func (o *RCC_Type) SetCIER_LSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIER_LSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIER_HSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIER_HSIRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIER_HSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIER_HSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIER_PLLSYSRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIER_PLLSYSRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x20) >> 5
}

// RCC.CIFR: Clock interrupt flag register
func (o *RCC_Type) SetCIFR_LSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIFR_LSIRDYF() uint32 {
	return volatile.LoadUint32(&o.CIFR.Reg) & 0x1
}
func (o *RCC_Type) SetCIFR_LSERDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIFR_LSERDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIFR_HSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIFR_HSIRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIFR_HSERDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIFR_HSERDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIFR_PLLSYSRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIFR_PLLSYSRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIFR_CSSF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCIFR_CSSF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCIFR_LSECSSF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCIFR_LSECSSF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x200) >> 9
}

// RCC.CICR: Clock interrupt clear register
func (o *RCC_Type) SetCICR_LSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCICR_LSIRDYC() uint32 {
	return volatile.LoadUint32(&o.CICR.Reg) & 0x1
}
func (o *RCC_Type) SetCICR_LSERDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCICR_LSERDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCICR_HSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCICR_HSIRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCICR_HSERDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCICR_HSERDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCICR_PLLSYSRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCICR_PLLSYSRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCICR_CSSC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCICR_CSSC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCICR_LSECSSC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCICR_LSECSSC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x200) >> 9
}

// RCC.IOPRSTR: I/O port reset register
func (o *RCC_Type) SetIOPRSTR_GPIOARST(value uint32) {
	volatile.StoreUint32(&o.IOPRSTR.Reg, volatile.LoadUint32(&o.IOPRSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetIOPRSTR_GPIOARST() uint32 {
	return volatile.LoadUint32(&o.IOPRSTR.Reg) & 0x1
}
func (o *RCC_Type) SetIOPRSTR_GPIOBRST(value uint32) {
	volatile.StoreUint32(&o.IOPRSTR.Reg, volatile.LoadUint32(&o.IOPRSTR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetIOPRSTR_GPIOBRST() uint32 {
	return (volatile.LoadUint32(&o.IOPRSTR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetIOPRSTR_GPIOCRST(value uint32) {
	volatile.StoreUint32(&o.IOPRSTR.Reg, volatile.LoadUint32(&o.IOPRSTR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetIOPRSTR_GPIOCRST() uint32 {
	return (volatile.LoadUint32(&o.IOPRSTR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetIOPRSTR_GPIODRST(value uint32) {
	volatile.StoreUint32(&o.IOPRSTR.Reg, volatile.LoadUint32(&o.IOPRSTR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetIOPRSTR_GPIODRST() uint32 {
	return (volatile.LoadUint32(&o.IOPRSTR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetIOPRSTR_GPIOERST(value uint32) {
	volatile.StoreUint32(&o.IOPRSTR.Reg, volatile.LoadUint32(&o.IOPRSTR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetIOPRSTR_GPIOERST() uint32 {
	return (volatile.LoadUint32(&o.IOPRSTR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetIOPRSTR_GPIOFRST(value uint32) {
	volatile.StoreUint32(&o.IOPRSTR.Reg, volatile.LoadUint32(&o.IOPRSTR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetIOPRSTR_GPIOFRST() uint32 {
	return (volatile.LoadUint32(&o.IOPRSTR.Reg) & 0x20) >> 5
}

// RCC.AHBRSTR: AHB peripheral reset register
func (o *RCC_Type) SetAHBRSTR_DMA1RST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHBRSTR_DMA1RST() uint32 {
	return volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHBRSTR_FLASHRST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHBRSTR_FLASHRST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHBRSTR_CRCRST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHBRSTR_CRCRST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x1000) >> 12
}

// RCC.APBRSTR1: APB peripheral reset register 1
func (o *RCC_Type) SetAPBRSTR1_TIM3RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPBRSTR1_TIM3RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPBRSTR1_TIM6RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPBRSTR1_TIM6RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPBRSTR1_TIM7RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPBRSTR1_TIM7RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPBRSTR1_SPI2RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPBRSTR1_SPI2RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPBRSTR1_USART2RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPBRSTR1_USART2RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPBRSTR1_I2C1RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPBRSTR1_I2C1RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPBRSTR1_I2C2RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPBRSTR1_I2C2RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPBRSTR1_DBGRST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAPBRSTR1_DBGRST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetAPBRSTR1_PWRRST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR1.Reg, volatile.LoadUint32(&o.APBRSTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPBRSTR1_PWRRST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR1.Reg) & 0x10000000) >> 28
}

// RCC.APBRSTR2: APB peripheral reset register 2
func (o *RCC_Type) SetAPBRSTR2_SYSCFGRST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPBRSTR2_SYSCFGRST() uint32 {
	return volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x1
}
func (o *RCC_Type) SetAPBRSTR2_TIM1RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPBRSTR2_TIM1RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPBRSTR2_SPI1RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPBRSTR2_SPI1RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPBRSTR2_USART1RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPBRSTR2_USART1RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPBRSTR2_TIM14RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPBRSTR2_TIM14RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPBRSTR2_TIM15RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPBRSTR2_TIM15RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPBRSTR2_TIM16RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPBRSTR2_TIM16RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPBRSTR2_TIM17RST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPBRSTR2_TIM17RST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPBRSTR2_ADCRST(value uint32) {
	volatile.StoreUint32(&o.APBRSTR2.Reg, volatile.LoadUint32(&o.APBRSTR2.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPBRSTR2_ADCRST() uint32 {
	return (volatile.LoadUint32(&o.APBRSTR2.Reg) & 0x100000) >> 20
}

// RCC.IOPENR: GPIO clock enable register
func (o *RCC_Type) SetIOPENR_GPIOAEN(value uint32) {
	volatile.StoreUint32(&o.IOPENR.Reg, volatile.LoadUint32(&o.IOPENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetIOPENR_GPIOAEN() uint32 {
	return volatile.LoadUint32(&o.IOPENR.Reg) & 0x1
}
func (o *RCC_Type) SetIOPENR_GPIOBEN(value uint32) {
	volatile.StoreUint32(&o.IOPENR.Reg, volatile.LoadUint32(&o.IOPENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetIOPENR_GPIOBEN() uint32 {
	return (volatile.LoadUint32(&o.IOPENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetIOPENR_GPIOCEN(value uint32) {
	volatile.StoreUint32(&o.IOPENR.Reg, volatile.LoadUint32(&o.IOPENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetIOPENR_GPIOCEN() uint32 {
	return (volatile.LoadUint32(&o.IOPENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetIOPENR_GPIODEN(value uint32) {
	volatile.StoreUint32(&o.IOPENR.Reg, volatile.LoadUint32(&o.IOPENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetIOPENR_GPIODEN() uint32 {
	return (volatile.LoadUint32(&o.IOPENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetIOPENR_GPIOEEN(value uint32) {
	volatile.StoreUint32(&o.IOPENR.Reg, volatile.LoadUint32(&o.IOPENR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetIOPENR_GPIOEEN() uint32 {
	return (volatile.LoadUint32(&o.IOPENR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetIOPENR_GPIOFEN(value uint32) {
	volatile.StoreUint32(&o.IOPENR.Reg, volatile.LoadUint32(&o.IOPENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetIOPENR_GPIOFEN() uint32 {
	return (volatile.LoadUint32(&o.IOPENR.Reg) & 0x20) >> 5
}

// RCC.AHBENR: AHB peripheral clock enable register
func (o *RCC_Type) SetAHBENR_DMA1EN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHBENR_DMA1EN() uint32 {
	return volatile.LoadUint32(&o.AHBENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHBENR_FLASHEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHBENR_FLASHEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHBENR_CRCEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHBENR_CRCEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x1000) >> 12
}

// RCC.APBENR1: APB peripheral clock enable register 1
func (o *RCC_Type) SetAPBENR1_TIM3EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPBENR1_TIM3EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPBENR1_TIM6EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPBENR1_TIM6EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPBENR1_TIM7EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPBENR1_TIM7EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPBENR1_RTCAPBEN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPBENR1_RTCAPBEN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPBENR1_WWDGEN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPBENR1_WWDGEN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPBENR1_SPI2EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPBENR1_SPI2EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPBENR1_USART2EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPBENR1_USART2EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPBENR1_I2C1EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPBENR1_I2C1EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPBENR1_I2C2EN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPBENR1_I2C2EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPBENR1_DBGEN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAPBENR1_DBGEN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetAPBENR1_PWREN(value uint32) {
	volatile.StoreUint32(&o.APBENR1.Reg, volatile.LoadUint32(&o.APBENR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPBENR1_PWREN() uint32 {
	return (volatile.LoadUint32(&o.APBENR1.Reg) & 0x10000000) >> 28
}

// RCC.APBENR2: APB peripheral clock enable register 2
func (o *RCC_Type) SetAPBENR2_SYSCFGEN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPBENR2_SYSCFGEN() uint32 {
	return volatile.LoadUint32(&o.APBENR2.Reg) & 0x1
}
func (o *RCC_Type) SetAPBENR2_TIM1EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPBENR2_TIM1EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPBENR2_SPI1EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPBENR2_SPI1EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPBENR2_USART1EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPBENR2_USART1EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPBENR2_TIM14EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPBENR2_TIM14EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPBENR2_TIM15EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPBENR2_TIM15EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPBENR2_TIM16EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPBENR2_TIM16EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPBENR2_TIM17EN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPBENR2_TIM17EN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPBENR2_ADCEN(value uint32) {
	volatile.StoreUint32(&o.APBENR2.Reg, volatile.LoadUint32(&o.APBENR2.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPBENR2_ADCEN() uint32 {
	return (volatile.LoadUint32(&o.APBENR2.Reg) & 0x100000) >> 20
}

// RCC.IOPSMENR: GPIO in Sleep mode clock enable register
func (o *RCC_Type) SetIOPSMENR_GPIOASMEN(value uint32) {
	volatile.StoreUint32(&o.IOPSMENR.Reg, volatile.LoadUint32(&o.IOPSMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetIOPSMENR_GPIOASMEN() uint32 {
	return volatile.LoadUint32(&o.IOPSMENR.Reg) & 0x1
}
func (o *RCC_Type) SetIOPSMENR_GPIOBSMEN(value uint32) {
	volatile.StoreUint32(&o.IOPSMENR.Reg, volatile.LoadUint32(&o.IOPSMENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetIOPSMENR_GPIOBSMEN() uint32 {
	return (volatile.LoadUint32(&o.IOPSMENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetIOPSMENR_GPIOCSMEN(value uint32) {
	volatile.StoreUint32(&o.IOPSMENR.Reg, volatile.LoadUint32(&o.IOPSMENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetIOPSMENR_GPIOCSMEN() uint32 {
	return (volatile.LoadUint32(&o.IOPSMENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetIOPSMENR_GPIODSMEN(value uint32) {
	volatile.StoreUint32(&o.IOPSMENR.Reg, volatile.LoadUint32(&o.IOPSMENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetIOPSMENR_GPIODSMEN() uint32 {
	return (volatile.LoadUint32(&o.IOPSMENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetIOPSMENR_GPIOESMEN(value uint32) {
	volatile.StoreUint32(&o.IOPSMENR.Reg, volatile.LoadUint32(&o.IOPSMENR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetIOPSMENR_GPIOESMEN() uint32 {
	return (volatile.LoadUint32(&o.IOPSMENR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetIOPSMENR_GPIOFSMEN(value uint32) {
	volatile.StoreUint32(&o.IOPSMENR.Reg, volatile.LoadUint32(&o.IOPSMENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetIOPSMENR_GPIOFSMEN() uint32 {
	return (volatile.LoadUint32(&o.IOPSMENR.Reg) & 0x20) >> 5
}

// RCC.AHBSMENR: AHB peripheral clock enable in Sleep mode register
func (o *RCC_Type) SetAHBSMENR_DMA1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHBSMENR.Reg, volatile.LoadUint32(&o.AHBSMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHBSMENR_DMA1SMEN() uint32 {
	return volatile.LoadUint32(&o.AHBSMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHBSMENR_FLASHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHBSMENR.Reg, volatile.LoadUint32(&o.AHBSMENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHBSMENR_FLASHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHBSMENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHBSMENR_SRAMSMEN(value uint32) {
	volatile.StoreUint32(&o.AHBSMENR.Reg, volatile.LoadUint32(&o.AHBSMENR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHBSMENR_SRAMSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHBSMENR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHBSMENR_CRCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHBSMENR.Reg, volatile.LoadUint32(&o.AHBSMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHBSMENR_CRCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHBSMENR.Reg) & 0x1000) >> 12
}

// RCC.APBSMENR1: APB peripheral clock enable in Sleep mode register 1
func (o *RCC_Type) SetAPBSMENR1_TIM3SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPBSMENR1_TIM3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPBSMENR1_TIM6SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPBSMENR1_TIM6SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPBSMENR1_TIM7SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPBSMENR1_TIM7SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPBSMENR1_RTCAPBSMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPBSMENR1_RTCAPBSMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPBSMENR1_WWDGSMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPBSMENR1_WWDGSMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPBSMENR1_SPI2SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPBSMENR1_SPI2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPBSMENR1_USART2SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPBSMENR1_USART2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPBSMENR1_I2C1SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPBSMENR1_I2C1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPBSMENR1_I2C2SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPBSMENR1_I2C2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPBSMENR1_DBGSMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAPBSMENR1_DBGSMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetAPBSMENR1_PWRSMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR1.Reg, volatile.LoadUint32(&o.APBSMENR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPBSMENR1_PWRSMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR1.Reg) & 0x10000000) >> 28
}

// RCC.APBSMENR2: APB peripheral clock enable in Sleep mode register 2
func (o *RCC_Type) SetAPBSMENR2_SYSCFGSMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPBSMENR2_SYSCFGSMEN() uint32 {
	return volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x1
}
func (o *RCC_Type) SetAPBSMENR2_TIM1SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPBSMENR2_TIM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPBSMENR2_SPI1SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPBSMENR2_SPI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPBSMENR2_USART1SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPBSMENR2_USART1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPBSMENR2_TIM14SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPBSMENR2_TIM14SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPBSMENR2_TIM15SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPBSMENR2_TIM15SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPBSMENR2_TIM16SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPBSMENR2_TIM16SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPBSMENR2_TIM17SMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPBSMENR2_TIM17SMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPBSMENR2_ADCSMEN(value uint32) {
	volatile.StoreUint32(&o.APBSMENR2.Reg, volatile.LoadUint32(&o.APBSMENR2.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPBSMENR2_ADCSMEN() uint32 {
	return (volatile.LoadUint32(&o.APBSMENR2.Reg) & 0x100000) >> 20
}

// RCC.CCIPR: Peripherals independent clock configuration register
func (o *RCC_Type) SetCCIPR_USART1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetCCIPR_USART1SEL() uint32 {
	return volatile.LoadUint32(&o.CCIPR.Reg) & 0x3
}
func (o *RCC_Type) SetCCIPR_USART2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetCCIPR_USART2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetCCIPR_I2C1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0x3000)|value<<12)
}
func (o *RCC_Type) GetCCIPR_I2C1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR.Reg) & 0x3000) >> 12
}
func (o *RCC_Type) SetCCIPR_I2S1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0xc000)|value<<14)
}
func (o *RCC_Type) GetCCIPR_I2S1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR.Reg) & 0xc000) >> 14
}
func (o *RCC_Type) SetCCIPR_TIM1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetCCIPR_TIM1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetCCIPR_TIM15SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetCCIPR_TIM15SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetCCIPR_ADCSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR.Reg, volatile.LoadUint32(&o.CCIPR.Reg)&^(0xc0000000)|value<<30)
}
func (o *RCC_Type) GetCCIPR_ADCSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR.Reg) & 0xc0000000) >> 30
}

// RCC.BDCR: RTC domain control register
func (o *RCC_Type) SetBDCR_LSEON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetBDCR_LSEON() uint32 {
	return volatile.LoadUint32(&o.BDCR.Reg) & 0x1
}
func (o *RCC_Type) SetBDCR_LSERDY(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetBDCR_LSERDY() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetBDCR_LSEBYP(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetBDCR_LSEBYP() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetBDCR_LSEDRV(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x18)|value<<3)
}
func (o *RCC_Type) GetBDCR_LSEDRV() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x18) >> 3
}
func (o *RCC_Type) SetBDCR_LSECSSON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetBDCR_LSECSSON() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetBDCR_LSECSSD(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetBDCR_LSECSSD() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetBDCR_RTCSEL(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x300)|value<<8)
}
func (o *RCC_Type) GetBDCR_RTCSEL() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x300) >> 8
}
func (o *RCC_Type) SetBDCR_RTCEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetBDCR_RTCEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetBDCR_BDRST(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetBDCR_BDRST() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetBDCR_LSCOEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetBDCR_LSCOEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetBDCR_LSCOSEL(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetBDCR_LSCOSEL() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x2000000) >> 25
}

// RCC.CSR: Control/status register
func (o *RCC_Type) SetCSR_LSION(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCSR_LSION() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0x1
}
func (o *RCC_Type) SetCSR_LSIRDY(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCSR_LSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCSR_RMVF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetCSR_RMVF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetCSR_OBLRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetCSR_OBLRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetCSR_PINRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetCSR_PINRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetCSR_PWRRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetCSR_PWRRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetCSR_SFTRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetCSR_SFTRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetCSR_IWDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetCSR_IWDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetCSR_WWDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetCSR_WWDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetCSR_LPWRRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetCSR_LPWRRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000000) >> 31
}

// Real-time clock
type RTC_Type struct {
	TR       volatile.Register32 // 0x0
	DR       volatile.Register32 // 0x4
	SSR      volatile.Register32 // 0x8
	ICSR     volatile.Register32 // 0xC
	PRER     volatile.Register32 // 0x10
	WUTR     volatile.Register32 // 0x14
	CR       volatile.Register32 // 0x18
	_        [8]byte
	WPR      volatile.Register32 // 0x24
	CALR     volatile.Register32 // 0x28
	SHIFTR   volatile.Register32 // 0x2C
	TSTR     volatile.Register32 // 0x30
	TSDR     volatile.Register32 // 0x34
	TSSSR    volatile.Register32 // 0x38
	_        [4]byte
	ALRMAR   volatile.Register32 // 0x40
	ALRMASSR volatile.Register32 // 0x44
	ALRMBR   volatile.Register32 // 0x48
	ALRMBSSR volatile.Register32 // 0x4C
	SR       volatile.Register32 // 0x50
	MISR     volatile.Register32 // 0x54
	_        [4]byte
	SCR      volatile.Register32 // 0x5C
}

// RTC.TR: RTC time register
func (o *RTC_Type) SetTR_SU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetTR_SU() uint32 {
	return volatile.LoadUint32(&o.TR.Reg) & 0xf
}
func (o *RTC_Type) SetTR_ST(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetTR_ST() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetTR_MNU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetTR_MNU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetTR_MNT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetTR_MNT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetTR_HU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetTR_HU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetTR_HT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetTR_HT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetTR_PM(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetTR_PM() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x400000) >> 22
}

// RTC.DR: RTC date register
func (o *RTC_Type) SetDR_DU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetDR_DU() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xf
}
func (o *RTC_Type) SetDR_DT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetDR_DT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x30) >> 4
}
func (o *RTC_Type) SetDR_MU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetDR_MU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetDR_MT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetDR_MT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetDR_WDU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xe000)|value<<13)
}
func (o *RTC_Type) GetDR_WDU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xe000) >> 13
}
func (o *RTC_Type) SetDR_YU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetDR_YU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetDR_YT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00000)|value<<20)
}
func (o *RTC_Type) GetDR_YT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00000) >> 20
}

// RTC.SSR: RTC sub second register
func (o *RTC_Type) SetSSR_SS(value uint32) {
	volatile.StoreUint32(&o.SSR.Reg, volatile.LoadUint32(&o.SSR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetSSR_SS() uint32 {
	return volatile.LoadUint32(&o.SSR.Reg) & 0xffff
}

// RTC.ICSR: RTC initialization control and status register
func (o *RTC_Type) SetICSR_ALRAWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetICSR_ALRAWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetICSR_ALRBWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetICSR_ALRBWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetICSR_WUTWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetICSR_WUTWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetICSR_SHPF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetICSR_SHPF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetICSR_INITS(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetICSR_INITS() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetICSR_RSF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetICSR_RSF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetICSR_INITF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetICSR_INITF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetICSR_INIT(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetICSR_INIT() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetICSR_RECALPF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetICSR_RECALPF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x10000) >> 16
}

// RTC.PRER: RTC prescaler register
func (o *RTC_Type) SetPRER_PREDIV_S(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetPRER_PREDIV_S() uint32 {
	return volatile.LoadUint32(&o.PRER.Reg) & 0x7fff
}
func (o *RTC_Type) SetPRER_PREDIV_A(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7f0000)|value<<16)
}
func (o *RTC_Type) GetPRER_PREDIV_A() uint32 {
	return (volatile.LoadUint32(&o.PRER.Reg) & 0x7f0000) >> 16
}

// RTC.WUTR: RTC wakeup timer register
func (o *RTC_Type) SetWUTR_WUT(value uint32) {
	volatile.StoreUint32(&o.WUTR.Reg, volatile.LoadUint32(&o.WUTR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetWUTR_WUT() uint32 {
	return volatile.LoadUint32(&o.WUTR.Reg) & 0xffff
}

// RTC.CR: control register
func (o *RTC_Type) SetCR_WUCKSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7)|value)
}
func (o *RTC_Type) GetCR_WUCKSEL() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7
}
func (o *RTC_Type) SetCR_TSEDGE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetCR_TSEDGE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetCR_REFCKON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetCR_REFCKON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetCR_BYPSHAD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetCR_BYPSHAD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetCR_FMT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetCR_FMT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetCR_ALRAE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *RTC_Type) GetCR_ALRAE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *RTC_Type) SetCR_ALRBE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_ALRBE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_WUTE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_WUTE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_TSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *RTC_Type) GetCR_TSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *RTC_Type) SetCR_ALRAIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCR_ALRAIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCR_ALRBIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_ALRBIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_WUTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_WUTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_TSIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCR_TSIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetCR_ADD1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetCR_ADD1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RTC_Type) SetCR_SUB1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RTC_Type) GetCR_SUB1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RTC_Type) SetCR_BKP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RTC_Type) GetCR_BKP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RTC_Type) SetCR_COSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RTC_Type) GetCR_COSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RTC_Type) SetCR_POL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *RTC_Type) GetCR_POL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *RTC_Type) SetCR_OSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x600000)|value<<21)
}
func (o *RTC_Type) GetCR_OSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x600000) >> 21
}
func (o *RTC_Type) SetCR_COE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetCR_COE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetCR_ITSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *RTC_Type) GetCR_ITSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *RTC_Type) SetCR_TAMPTS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *RTC_Type) GetCR_TAMPTS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}
func (o *RTC_Type) SetCR_TAMPOE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000000)|value<<26)
}
func (o *RTC_Type) GetCR_TAMPOE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000000) >> 26
}
func (o *RTC_Type) SetCR_TAMPALRM_PU(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *RTC_Type) GetCR_TAMPALRM_PU() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *RTC_Type) SetCR_TAMPALRM_TYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetCR_TAMPALRM_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetCR_OUT2EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetCR_OUT2EN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// RTC.WPR: write protection register
func (o *RTC_Type) SetWPR_KEY(value uint32) {
	volatile.StoreUint32(&o.WPR.Reg, volatile.LoadUint32(&o.WPR.Reg)&^(0xff)|value)
}
func (o *RTC_Type) GetWPR_KEY() uint32 {
	return volatile.LoadUint32(&o.WPR.Reg) & 0xff
}

// RTC.CALR: RTC calibration register
func (o *RTC_Type) SetCALR_CALM(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x1ff)|value)
}
func (o *RTC_Type) GetCALR_CALM() uint32 {
	return volatile.LoadUint32(&o.CALR.Reg) & 0x1ff
}
func (o *RTC_Type) SetCALR_CALW16(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCALR_CALW16() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCALR_CALW8(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCALR_CALW8() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCALR_CALP(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCALR_CALP() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x8000) >> 15
}

// RTC.SHIFTR: RTC shift control register
func (o *RTC_Type) SetSHIFTR_SUBFS(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetSHIFTR_SUBFS() uint32 {
	return volatile.LoadUint32(&o.SHIFTR.Reg) & 0x7fff
}
func (o *RTC_Type) SetSHIFTR_ADD1S(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetSHIFTR_ADD1S() uint32 {
	return (volatile.LoadUint32(&o.SHIFTR.Reg) & 0x80000000) >> 31
}

// RTC.ALRMAR: Alarm %s register
func (o *RTC_Type) SetALRMAR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMAR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf
}
func (o *RTC_Type) SetALRMAR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMAR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMAR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMAR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMAR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMAR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMAR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMAR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMAR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMAR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMAR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMAR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMAR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMAR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMAR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMAR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMAR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMAR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMAR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMAR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMAR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMAR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMAR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMAR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMAR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMAR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80000000) >> 31
}

// RTC.ALRMASSR: Alarm %s sub-second register
func (o *RTC_Type) SetALRMASSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMASSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMASSR.Reg) & 0x7fff
}
func (o *RTC_Type) SetALRMASSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMASSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMASSR.Reg) & 0xf000000) >> 24
}

// RTC.ALRMBR: Alarm %s register
func (o *RTC_Type) SetALRMBR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMBR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf
}
func (o *RTC_Type) SetALRMBR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMBR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMBR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMBR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMBR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMBR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMBR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMBR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMBR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMBR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMBR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMBR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMBR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMBR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMBR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMBR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMBR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMBR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMBR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMBR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMBR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMBR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMBR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMBR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMBR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMBR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x80000000) >> 31
}

// RTC.ALRMBSSR: Alarm %s sub-second register
func (o *RTC_Type) SetALRMBSSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMBSSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0x7fff
}
func (o *RTC_Type) SetALRMBSSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMBSSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0xf000000) >> 24
}

// RTC.SR: RTC status register
func (o *RTC_Type) SetSR_ALRAF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSR_ALRAF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSR_ALRBF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSR_ALRBF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSR_WUTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSR_WUTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSR_TSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSR_TSF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSR_TSOVF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSR_TSOVF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSR_ITSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSR_ITSF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}

// RTC.MISR: RTC masked interrupt status register
func (o *RTC_Type) SetMISR_ALRAMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetMISR_ALRAMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetMISR_ALRBMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetMISR_ALRBMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetMISR_WUTMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetMISR_WUTMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetMISR_TSMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetMISR_TSMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetMISR_TSOVMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetMISR_TSOVMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetMISR_ITSMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetMISR_ITSMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20) >> 5
}

// RTC.SCR: RTC status clear register
func (o *RTC_Type) SetSCR_CALRAF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSCR_CALRAF() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *RTC_Type) SetSCR_CALRBF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSCR_CALRBF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSCR_CWUTF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSCR_CWUTF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSCR_CTSF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSCR_CTSF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSCR_CTSOVF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSCR_CTSOVF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSCR_CITSF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSCR_CITSF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}

// Serial peripheral interface/Inter-IC sound
type SPI_Type struct {
	CR1     volatile.Register16 // 0x0
	_       [2]byte
	CR2     volatile.Register16 // 0x4
	_       [2]byte
	SR      volatile.Register16 // 0x8
	_       [2]byte
	DR      volatile.Register16 // 0xC
	_       [2]byte
	CRCPR   volatile.Register16 // 0x10
	_       [2]byte
	RXCRCR  volatile.Register16 // 0x14
	_       [2]byte
	TXCRCR  volatile.Register16 // 0x18
	_       [2]byte
	I2SCFGR volatile.Register16 // 0x1C
	_       [2]byte
	I2SPR   volatile.Register16 // 0x20
}

// SPI.CR1
func (o *SPI_Type) SetCR1_CPHA(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR1_CPHA() uint16 {
	return volatile.LoadUint16(&o.CR1.Reg) & 0x1
}
func (o *SPI_Type) SetCR1_CPOL(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR1_CPOL() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR1_MSTR(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCR1_MSTR() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCR1_BR(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x38)|value<<3)
}
func (o *SPI_Type) GetCR1_BR() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x38) >> 3
}
func (o *SPI_Type) SetCR1_SPE(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetCR1_SPE() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetCR1_LSBFIRST(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR1_LSBFIRST() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR1_SSI(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetCR1_SSI() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetCR1_SSM(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetCR1_SSM() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetCR1_RXONLY(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetCR1_RXONLY() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetCR1_CRCL(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetCR1_CRCL() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetCR1_CRCNEXT(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR1_CRCNEXT() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR1_CRCEN(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR1_CRCEN() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR1_BIDIOE(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR1_BIDIOE() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *SPI_Type) SetCR1_BIDIMODE(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetCR1_BIDIMODE() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x8000) >> 15
}

// SPI.CR2
func (o *SPI_Type) SetCR2_RXDMAEN(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR2_RXDMAEN() uint16 {
	return volatile.LoadUint16(&o.CR2.Reg) & 0x1
}
func (o *SPI_Type) SetCR2_TXDMAEN(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR2_TXDMAEN() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR2_SSOE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCR2_SSOE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCR2_NSSP(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetCR2_NSSP() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetCR2_FRF(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetCR2_FRF() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetCR2_ERRIE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetCR2_ERRIE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetCR2_RXNEIE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetCR2_RXNEIE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetCR2_TXEIE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR2_TXEIE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR2_DS(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0xf00)|value<<8)
}
func (o *SPI_Type) GetCR2_DS() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0xf00) >> 8
}
func (o *SPI_Type) SetCR2_FRXTH(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR2_FRXTH() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR2_LDMA_RX(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR2_LDMA_RX() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR2_LDMA_TX(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR2_LDMA_TX() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x4000) >> 14
}

// SPI.SR
func (o *SPI_Type) SetSR_RXNE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetSR_RXNE() uint16 {
	return volatile.LoadUint16(&o.SR.Reg) & 0x1
}
func (o *SPI_Type) SetSR_TXE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetSR_TXE() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetSR_CHSIDE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetSR_CHSIDE() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetSR_UDR(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetSR_UDR() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetSR_CRCERR(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetSR_CRCERR() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetSR_MODF(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetSR_MODF() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetSR_OVR(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetSR_OVR() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetSR_BSY(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetSR_BSY() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetSR_FRE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetSR_FRE() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetSR_FRLVL(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x600)|value<<9)
}
func (o *SPI_Type) GetSR_FRLVL() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x600) >> 9
}
func (o *SPI_Type) SetSR_FTLVL(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x1800)|value<<11)
}
func (o *SPI_Type) GetSR_FTLVL() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x1800) >> 11
}

// SPI.DR
func (o *SPI_Type) SetDR(value uint16) {
	volatile.StoreUint16(&o.DR.Reg, value)
}
func (o *SPI_Type) GetDR() uint16 {
	return volatile.LoadUint16(&o.DR.Reg)
}

// SPI.CRCPR
func (o *SPI_Type) SetCRCPR(value uint16) {
	volatile.StoreUint16(&o.CRCPR.Reg, value)
}
func (o *SPI_Type) GetCRCPR() uint16 {
	return volatile.LoadUint16(&o.CRCPR.Reg)
}

// SPI.RXCRCR
func (o *SPI_Type) SetRXCRCR(value uint16) {
	volatile.StoreUint16(&o.RXCRCR.Reg, value)
}
func (o *SPI_Type) GetRXCRCR() uint16 {
	return volatile.LoadUint16(&o.RXCRCR.Reg)
}

// SPI.TXCRCR
func (o *SPI_Type) SetTXCRCR(value uint16) {
	volatile.StoreUint16(&o.TXCRCR.Reg, value)
}
func (o *SPI_Type) GetTXCRCR() uint16 {
	return volatile.LoadUint16(&o.TXCRCR.Reg)
}

// SPI.I2SCFGR
func (o *SPI_Type) SetI2SCFGR_CHLEN(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetI2SCFGR_CHLEN() uint16 {
	return volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x1
}
func (o *SPI_Type) SetI2SCFGR_DATLEN(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x6)|value<<1)
}
func (o *SPI_Type) GetI2SCFGR_DATLEN() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x6) >> 1
}
func (o *SPI_Type) SetI2SCFGR_CKPOL(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetI2SCFGR_CKPOL() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetI2SCFGR_I2SSTD(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x30)|value<<4)
}
func (o *SPI_Type) GetI2SCFGR_I2SSTD() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x30) >> 4
}
func (o *SPI_Type) SetI2SCFGR_PCMSYNC(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetI2SCFGR_PCMSYNC() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetI2SCFGR_I2SCFG(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x300)|value<<8)
}
func (o *SPI_Type) GetI2SCFGR_I2SCFG() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x300) >> 8
}
func (o *SPI_Type) SetI2SCFGR_I2SE(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetI2SCFGR_I2SE() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetI2SCFGR_I2SMOD(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetI2SCFGR_I2SMOD() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetI2SCFGR_ASTRTEN(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetI2SCFGR_ASTRTEN() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x1000) >> 12
}

// SPI.I2SPR
func (o *SPI_Type) SetI2SPR_I2SDIV(value uint16) {
	volatile.StoreUint16(&o.I2SPR.Reg, volatile.LoadUint16(&o.I2SPR.Reg)&^(0xff)|value)
}
func (o *SPI_Type) GetI2SPR_I2SDIV() uint16 {
	return volatile.LoadUint16(&o.I2SPR.Reg) & 0xff
}
func (o *SPI_Type) SetI2SPR_ODD(value uint16) {
	volatile.StoreUint16(&o.I2SPR.Reg, volatile.LoadUint16(&o.I2SPR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetI2SPR_ODD() uint16 {
	return (volatile.LoadUint16(&o.I2SPR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetI2SPR_MCKOE(value uint16) {
	volatile.StoreUint16(&o.I2SPR.Reg, volatile.LoadUint16(&o.I2SPR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetI2SPR_MCKOE() uint16 {
	return (volatile.LoadUint16(&o.I2SPR.Reg) & 0x200) >> 9
}

// System configuration controller
type SYSCFG_Type struct {
	CFGR1    volatile.Register32 // 0x0
	_        [20]byte
	CFGR2    volatile.Register32 // 0x18
	_        [100]byte
	ITLINE0  volatile.Register32 // 0x80
	_        [4]byte
	ITLINE2  volatile.Register32 // 0x88
	ITLINE3  volatile.Register32 // 0x8C
	ITLINE4  volatile.Register32 // 0x90
	ITLINE5  volatile.Register32 // 0x94
	ITLINE6  volatile.Register32 // 0x98
	ITLINE7  volatile.Register32 // 0x9C
	ITLINE8  volatile.Register32 // 0xA0
	ITLINE9  volatile.Register32 // 0xA4
	ITLINE10 volatile.Register32 // 0xA8
	ITLINE11 volatile.Register32 // 0xAC
	ITLINE12 volatile.Register32 // 0xB0
	ITLINE13 volatile.Register32 // 0xB4
	ITLINE14 volatile.Register32 // 0xB8
	_        [4]byte
	ITLINE16 volatile.Register32 // 0xC0
	ITLINE17 volatile.Register32 // 0xC4
	ITLINE18 volatile.Register32 // 0xC8
	ITLINE19 volatile.Register32 // 0xCC
	ITLINE20 volatile.Register32 // 0xD0
	ITLINE21 volatile.Register32 // 0xD4
	ITLINE22 volatile.Register32 // 0xD8
	ITLINE23 volatile.Register32 // 0xDC
	ITLINE24 volatile.Register32 // 0xE0
	ITLINE25 volatile.Register32 // 0xE4
	ITLINE26 volatile.Register32 // 0xE8
	ITLINE27 volatile.Register32 // 0xEC
	ITLINE28 volatile.Register32 // 0xF0
	ITLINE29 volatile.Register32 // 0xF4
}

// SYSCFG.CFGR1: SYSCFG configuration register 1
func (o *SYSCFG_Type) SetCFGR1_I2C_PBx_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PBx_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000) >> 16
}
func (o *SYSCFG_Type) SetCFGR1_I2C3_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *SYSCFG_Type) GetCFGR1_I2C3_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1000000) >> 24
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PA10_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PA10_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x800000) >> 23
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PA9_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PA9_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400000) >> 22
}
func (o *SYSCFG_Type) SetCFGR1_I2C2_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *SYSCFG_Type) GetCFGR1_I2C2_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200000) >> 21
}
func (o *SYSCFG_Type) SetCFGR1_I2C1_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *SYSCFG_Type) GetCFGR1_I2C1_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100000) >> 20
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB9_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB9_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80000) >> 19
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB8_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB8_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40000) >> 18
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB7_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB7_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20000) >> 17
}
func (o *SYSCFG_Type) SetCFGR1_UCPD1_STROBE(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetCFGR1_UCPD1_STROBE() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200) >> 9
}
func (o *SYSCFG_Type) SetCFGR1_UCPD2_STROBE(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400)|value<<10)
}
func (o *SYSCFG_Type) GetCFGR1_UCPD2_STROBE() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400) >> 10
}
func (o *SYSCFG_Type) SetCFGR1_BOOSTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetCFGR1_BOOSTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetCFGR1_IR_MOD(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc0)|value<<6)
}
func (o *SYSCFG_Type) GetCFGR1_IR_MOD() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc0) >> 6
}
func (o *SYSCFG_Type) SetCFGR1_IR_POL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20)|value<<5)
}
func (o *SYSCFG_Type) GetCFGR1_IR_POL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20) >> 5
}
func (o *SYSCFG_Type) SetCFGR1_PA12_RMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetCFGR1_PA12_RMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10) >> 4
}
func (o *SYSCFG_Type) SetCFGR1_PA11_RMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetCFGR1_PA11_RMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetCFGR1_MEM_MODE(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3)|value)
}
func (o *SYSCFG_Type) GetCFGR1_MEM_MODE() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x3
}

// SYSCFG.CFGR2: SYSCFG configuration register 1
func (o *SYSCFG_Type) SetCFGR2_LOCKUP_LOCK(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCFGR2_LOCKUP_LOCK() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}
func (o *SYSCFG_Type) SetCFGR2_SRAM_PARITY_LOCK(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCFGR2_SRAM_PARITY_LOCK() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetCFGR2_ECC_LOCK(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetCFGR2_ECC_LOCK() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetCFGR2_SRAM_PEF(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetCFGR2_SRAM_PEF() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x100) >> 8
}

// SYSCFG.ITLINE0: interrupt line 0 status register
func (o *SYSCFG_Type) SetITLINE0_WWDG(value uint32) {
	volatile.StoreUint32(&o.ITLINE0.Reg, volatile.LoadUint32(&o.ITLINE0.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE0_WWDG() uint32 {
	return volatile.LoadUint32(&o.ITLINE0.Reg) & 0x1
}

// SYSCFG.ITLINE2: interrupt line 2 status register
func (o *SYSCFG_Type) SetITLINE2_TAMP(value uint32) {
	volatile.StoreUint32(&o.ITLINE2.Reg, volatile.LoadUint32(&o.ITLINE2.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE2_TAMP() uint32 {
	return volatile.LoadUint32(&o.ITLINE2.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE2_RTC(value uint32) {
	volatile.StoreUint32(&o.ITLINE2.Reg, volatile.LoadUint32(&o.ITLINE2.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE2_RTC() uint32 {
	return (volatile.LoadUint32(&o.ITLINE2.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE3: interrupt line 3 status register
func (o *SYSCFG_Type) SetITLINE3_FLASH_ITF(value uint32) {
	volatile.StoreUint32(&o.ITLINE3.Reg, volatile.LoadUint32(&o.ITLINE3.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE3_FLASH_ITF() uint32 {
	return volatile.LoadUint32(&o.ITLINE3.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE3_FLASH_ECC(value uint32) {
	volatile.StoreUint32(&o.ITLINE3.Reg, volatile.LoadUint32(&o.ITLINE3.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE3_FLASH_ECC() uint32 {
	return (volatile.LoadUint32(&o.ITLINE3.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE4: interrupt line 4 status register
func (o *SYSCFG_Type) SetITLINE4_RCC(value uint32) {
	volatile.StoreUint32(&o.ITLINE4.Reg, volatile.LoadUint32(&o.ITLINE4.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE4_RCC() uint32 {
	return volatile.LoadUint32(&o.ITLINE4.Reg) & 0x1
}

// SYSCFG.ITLINE5: interrupt line 5 status register
func (o *SYSCFG_Type) SetITLINE5_EXTI0(value uint32) {
	volatile.StoreUint32(&o.ITLINE5.Reg, volatile.LoadUint32(&o.ITLINE5.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE5_EXTI0() uint32 {
	return volatile.LoadUint32(&o.ITLINE5.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE5_EXTI1(value uint32) {
	volatile.StoreUint32(&o.ITLINE5.Reg, volatile.LoadUint32(&o.ITLINE5.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE5_EXTI1() uint32 {
	return (volatile.LoadUint32(&o.ITLINE5.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE6: interrupt line 6 status register
func (o *SYSCFG_Type) SetITLINE6_EXTI2(value uint32) {
	volatile.StoreUint32(&o.ITLINE6.Reg, volatile.LoadUint32(&o.ITLINE6.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE6_EXTI2() uint32 {
	return volatile.LoadUint32(&o.ITLINE6.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE6_EXTI3(value uint32) {
	volatile.StoreUint32(&o.ITLINE6.Reg, volatile.LoadUint32(&o.ITLINE6.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE6_EXTI3() uint32 {
	return (volatile.LoadUint32(&o.ITLINE6.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE7: interrupt line 7 status register
func (o *SYSCFG_Type) SetITLINE7_EXTI4(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI4() uint32 {
	return volatile.LoadUint32(&o.ITLINE7.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE7_EXTI5(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI5() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetITLINE7_EXTI6(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI6() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetITLINE7_EXTI7(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI7() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetITLINE7_EXTI8(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI8() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x10) >> 4
}
func (o *SYSCFG_Type) SetITLINE7_EXTI9(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x20)|value<<5)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI9() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x20) >> 5
}
func (o *SYSCFG_Type) SetITLINE7_EXTI10(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x40)|value<<6)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI10() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x40) >> 6
}
func (o *SYSCFG_Type) SetITLINE7_EXTI11(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x80)|value<<7)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI11() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x80) >> 7
}
func (o *SYSCFG_Type) SetITLINE7_EXTI12(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI12() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetITLINE7_EXTI13(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI13() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x200) >> 9
}
func (o *SYSCFG_Type) SetITLINE7_EXTI14(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x400)|value<<10)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI14() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x400) >> 10
}
func (o *SYSCFG_Type) SetITLINE7_EXTI15(value uint32) {
	volatile.StoreUint32(&o.ITLINE7.Reg, volatile.LoadUint32(&o.ITLINE7.Reg)&^(0x800)|value<<11)
}
func (o *SYSCFG_Type) GetITLINE7_EXTI15() uint32 {
	return (volatile.LoadUint32(&o.ITLINE7.Reg) & 0x800) >> 11
}

// SYSCFG.ITLINE8: interrupt line 8 status register
func (o *SYSCFG_Type) SetITLINE8_USB(value uint32) {
	volatile.StoreUint32(&o.ITLINE8.Reg, volatile.LoadUint32(&o.ITLINE8.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetITLINE8_USB() uint32 {
	return (volatile.LoadUint32(&o.ITLINE8.Reg) & 0x4) >> 2
}

// SYSCFG.ITLINE9: interrupt line 9 status register
func (o *SYSCFG_Type) SetITLINE9_DMA1_CH1(value uint32) {
	volatile.StoreUint32(&o.ITLINE9.Reg, volatile.LoadUint32(&o.ITLINE9.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE9_DMA1_CH1() uint32 {
	return volatile.LoadUint32(&o.ITLINE9.Reg) & 0x1
}

// SYSCFG.ITLINE10: interrupt line 10 status register
func (o *SYSCFG_Type) SetITLINE10_DMA1_CH2(value uint32) {
	volatile.StoreUint32(&o.ITLINE10.Reg, volatile.LoadUint32(&o.ITLINE10.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE10_DMA1_CH2() uint32 {
	return volatile.LoadUint32(&o.ITLINE10.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE10_DMA1_CH3(value uint32) {
	volatile.StoreUint32(&o.ITLINE10.Reg, volatile.LoadUint32(&o.ITLINE10.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE10_DMA1_CH3() uint32 {
	return (volatile.LoadUint32(&o.ITLINE10.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE11: interrupt line 11 status register
func (o *SYSCFG_Type) SetITLINE11_DMAMUX(value uint32) {
	volatile.StoreUint32(&o.ITLINE11.Reg, volatile.LoadUint32(&o.ITLINE11.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE11_DMAMUX() uint32 {
	return volatile.LoadUint32(&o.ITLINE11.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE11_DMA1_CH4(value uint32) {
	volatile.StoreUint32(&o.ITLINE11.Reg, volatile.LoadUint32(&o.ITLINE11.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE11_DMA1_CH4() uint32 {
	return (volatile.LoadUint32(&o.ITLINE11.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetITLINE11_DMA1_CH5(value uint32) {
	volatile.StoreUint32(&o.ITLINE11.Reg, volatile.LoadUint32(&o.ITLINE11.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetITLINE11_DMA1_CH5() uint32 {
	return (volatile.LoadUint32(&o.ITLINE11.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetITLINE11_DMA1_CH6(value uint32) {
	volatile.StoreUint32(&o.ITLINE11.Reg, volatile.LoadUint32(&o.ITLINE11.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetITLINE11_DMA1_CH6() uint32 {
	return (volatile.LoadUint32(&o.ITLINE11.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetITLINE11_DMA1_CH7(value uint32) {
	volatile.StoreUint32(&o.ITLINE11.Reg, volatile.LoadUint32(&o.ITLINE11.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetITLINE11_DMA1_CH7() uint32 {
	return (volatile.LoadUint32(&o.ITLINE11.Reg) & 0x10) >> 4
}

// SYSCFG.ITLINE12: interrupt line 12 status register
func (o *SYSCFG_Type) SetITLINE12_ADC(value uint32) {
	volatile.StoreUint32(&o.ITLINE12.Reg, volatile.LoadUint32(&o.ITLINE12.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE12_ADC() uint32 {
	return volatile.LoadUint32(&o.ITLINE12.Reg) & 0x1
}

// SYSCFG.ITLINE13: interrupt line 13 status register
func (o *SYSCFG_Type) SetITLINE13_TIM1_CCU(value uint32) {
	volatile.StoreUint32(&o.ITLINE13.Reg, volatile.LoadUint32(&o.ITLINE13.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE13_TIM1_CCU() uint32 {
	return volatile.LoadUint32(&o.ITLINE13.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE13_TIM1_TRG(value uint32) {
	volatile.StoreUint32(&o.ITLINE13.Reg, volatile.LoadUint32(&o.ITLINE13.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE13_TIM1_TRG() uint32 {
	return (volatile.LoadUint32(&o.ITLINE13.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetITLINE13_TIM1_UPD(value uint32) {
	volatile.StoreUint32(&o.ITLINE13.Reg, volatile.LoadUint32(&o.ITLINE13.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetITLINE13_TIM1_UPD() uint32 {
	return (volatile.LoadUint32(&o.ITLINE13.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetITLINE13_TIM1_BRK(value uint32) {
	volatile.StoreUint32(&o.ITLINE13.Reg, volatile.LoadUint32(&o.ITLINE13.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetITLINE13_TIM1_BRK() uint32 {
	return (volatile.LoadUint32(&o.ITLINE13.Reg) & 0x8) >> 3
}

// SYSCFG.ITLINE14: interrupt line 14 status register
func (o *SYSCFG_Type) SetITLINE14_TIM1_CC(value uint32) {
	volatile.StoreUint32(&o.ITLINE14.Reg, volatile.LoadUint32(&o.ITLINE14.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE14_TIM1_CC() uint32 {
	return volatile.LoadUint32(&o.ITLINE14.Reg) & 0x1
}

// SYSCFG.ITLINE16: interrupt line 16 status register
func (o *SYSCFG_Type) SetITLINE16_TIM3(value uint32) {
	volatile.StoreUint32(&o.ITLINE16.Reg, volatile.LoadUint32(&o.ITLINE16.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE16_TIM3() uint32 {
	return volatile.LoadUint32(&o.ITLINE16.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE16_TIM4(value uint32) {
	volatile.StoreUint32(&o.ITLINE16.Reg, volatile.LoadUint32(&o.ITLINE16.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE16_TIM4() uint32 {
	return (volatile.LoadUint32(&o.ITLINE16.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE17: interrupt line 17 status register
func (o *SYSCFG_Type) SetITLINE17_TIM6(value uint32) {
	volatile.StoreUint32(&o.ITLINE17.Reg, volatile.LoadUint32(&o.ITLINE17.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE17_TIM6() uint32 {
	return volatile.LoadUint32(&o.ITLINE17.Reg) & 0x1
}

// SYSCFG.ITLINE18: interrupt line 18 status register
func (o *SYSCFG_Type) SetITLINE18_TIM7(value uint32) {
	volatile.StoreUint32(&o.ITLINE18.Reg, volatile.LoadUint32(&o.ITLINE18.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE18_TIM7() uint32 {
	return volatile.LoadUint32(&o.ITLINE18.Reg) & 0x1
}

// SYSCFG.ITLINE19: interrupt line 19 status register
func (o *SYSCFG_Type) SetITLINE19_TIM14(value uint32) {
	volatile.StoreUint32(&o.ITLINE19.Reg, volatile.LoadUint32(&o.ITLINE19.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE19_TIM14() uint32 {
	return volatile.LoadUint32(&o.ITLINE19.Reg) & 0x1
}

// SYSCFG.ITLINE20: interrupt line 20 status register
func (o *SYSCFG_Type) SetITLINE20_TIM15(value uint32) {
	volatile.StoreUint32(&o.ITLINE20.Reg, volatile.LoadUint32(&o.ITLINE20.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE20_TIM15() uint32 {
	return volatile.LoadUint32(&o.ITLINE20.Reg) & 0x1
}

// SYSCFG.ITLINE21: interrupt line 21 status register
func (o *SYSCFG_Type) SetITLINE21_TIM16(value uint32) {
	volatile.StoreUint32(&o.ITLINE21.Reg, volatile.LoadUint32(&o.ITLINE21.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE21_TIM16() uint32 {
	return volatile.LoadUint32(&o.ITLINE21.Reg) & 0x1
}

// SYSCFG.ITLINE22: interrupt line 22 status register
func (o *SYSCFG_Type) SetITLINE22_TIM17(value uint32) {
	volatile.StoreUint32(&o.ITLINE22.Reg, volatile.LoadUint32(&o.ITLINE22.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE22_TIM17() uint32 {
	return volatile.LoadUint32(&o.ITLINE22.Reg) & 0x1
}

// SYSCFG.ITLINE23: interrupt line 23 status register
func (o *SYSCFG_Type) SetITLINE23_I2C1(value uint32) {
	volatile.StoreUint32(&o.ITLINE23.Reg, volatile.LoadUint32(&o.ITLINE23.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE23_I2C1() uint32 {
	return volatile.LoadUint32(&o.ITLINE23.Reg) & 0x1
}

// SYSCFG.ITLINE24: interrupt line 24 status register
func (o *SYSCFG_Type) SetITLINE24_I2C2(value uint32) {
	volatile.StoreUint32(&o.ITLINE24.Reg, volatile.LoadUint32(&o.ITLINE24.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE24_I2C2() uint32 {
	return volatile.LoadUint32(&o.ITLINE24.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE24_I2C3(value uint32) {
	volatile.StoreUint32(&o.ITLINE24.Reg, volatile.LoadUint32(&o.ITLINE24.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE24_I2C3() uint32 {
	return (volatile.LoadUint32(&o.ITLINE24.Reg) & 0x2) >> 1
}

// SYSCFG.ITLINE25: interrupt line 25 status register
func (o *SYSCFG_Type) SetITLINE25_SPI1(value uint32) {
	volatile.StoreUint32(&o.ITLINE25.Reg, volatile.LoadUint32(&o.ITLINE25.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE25_SPI1() uint32 {
	return volatile.LoadUint32(&o.ITLINE25.Reg) & 0x1
}

// SYSCFG.ITLINE26: interrupt line 26 status register
func (o *SYSCFG_Type) SetITLINE26_SPI2(value uint32) {
	volatile.StoreUint32(&o.ITLINE26.Reg, volatile.LoadUint32(&o.ITLINE26.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE26_SPI2() uint32 {
	return volatile.LoadUint32(&o.ITLINE26.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE26_SPI3(value uint32) {
	volatile.StoreUint32(&o.ITLINE26.Reg, volatile.LoadUint32(&o.ITLINE26.Reg)&^(0x4000)|value<<14)
}
func (o *SYSCFG_Type) GetITLINE26_SPI3() uint32 {
	return (volatile.LoadUint32(&o.ITLINE26.Reg) & 0x4000) >> 14
}

// SYSCFG.ITLINE27: interrupt line 27 status register
func (o *SYSCFG_Type) SetITLINE27_USART1(value uint32) {
	volatile.StoreUint32(&o.ITLINE27.Reg, volatile.LoadUint32(&o.ITLINE27.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE27_USART1() uint32 {
	return volatile.LoadUint32(&o.ITLINE27.Reg) & 0x1
}

// SYSCFG.ITLINE28: interrupt line 28 status register
func (o *SYSCFG_Type) SetITLINE28_USART2(value uint32) {
	volatile.StoreUint32(&o.ITLINE28.Reg, volatile.LoadUint32(&o.ITLINE28.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE28_USART2() uint32 {
	return volatile.LoadUint32(&o.ITLINE28.Reg) & 0x1
}

// SYSCFG.ITLINE29: interrupt line 29 status register
func (o *SYSCFG_Type) SetITLINE29_USART3(value uint32) {
	volatile.StoreUint32(&o.ITLINE29.Reg, volatile.LoadUint32(&o.ITLINE29.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetITLINE29_USART3() uint32 {
	return volatile.LoadUint32(&o.ITLINE29.Reg) & 0x1
}
func (o *SYSCFG_Type) SetITLINE29_USART4(value uint32) {
	volatile.StoreUint32(&o.ITLINE29.Reg, volatile.LoadUint32(&o.ITLINE29.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetITLINE29_USART4() uint32 {
	return (volatile.LoadUint32(&o.ITLINE29.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetITLINE29_USART5(value uint32) {
	volatile.StoreUint32(&o.ITLINE29.Reg, volatile.LoadUint32(&o.ITLINE29.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetITLINE29_USART5() uint32 {
	return (volatile.LoadUint32(&o.ITLINE29.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetITLINE29_USART6(value uint32) {
	volatile.StoreUint32(&o.ITLINE29.Reg, volatile.LoadUint32(&o.ITLINE29.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetITLINE29_USART6() uint32 {
	return (volatile.LoadUint32(&o.ITLINE29.Reg) & 0x10) >> 4
}

// Tamper and backup registers
type TAMP_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	_     [4]byte
	FLTCR volatile.Register32 // 0xC
	_     [28]byte
	IER   volatile.Register32 // 0x2C
	SR    volatile.Register32 // 0x30
	MISR  volatile.Register32 // 0x34
	_     [4]byte
	SCR   volatile.Register32 // 0x3C
	_     [192]byte
	BKP0R volatile.Register32 // 0x100
	BKP1R volatile.Register32 // 0x104
	BKP2R volatile.Register32 // 0x108
	BKP3R volatile.Register32 // 0x10C
	BKP4R volatile.Register32 // 0x110
}

// TAMP.CR1: TAMP control register 1
func (o *TAMP_Type) SetCR1_TAMP1E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR1_TAMP1E() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *TAMP_Type) SetCR1_TAMP2E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR1_TAMP2E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR1_TAMP3E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR1_TAMP3E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR1_ITAMP3E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetCR1_ITAMP3E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetCR1_ITAMP4E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *TAMP_Type) GetCR1_ITAMP4E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *TAMP_Type) SetCR1_ITAMP5E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetCR1_ITAMP5E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetCR1_ITAMP6E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetCR1_ITAMP6E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}

// TAMP.CR2: TAMP control register 2
func (o *TAMP_Type) SetCR2_TAMP1NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR2_TAMP1NOER() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *TAMP_Type) SetCR2_TAMP2NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR2_TAMP2NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR2_TAMP3NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR2_TAMP3NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR2_TAMP1MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetCR2_TAMP1MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetCR2_TAMP2MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetCR2_TAMP2MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetCR2_TAMP3MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetCR2_TAMP3MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetCR2_TAMP1TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetCR2_TAMP1TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetCR2_TAMP2TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *TAMP_Type) GetCR2_TAMP2TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *TAMP_Type) SetCR2_TAMP3TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetCR2_TAMP3TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}

// TAMP.FLTCR: TAMP filter control register
func (o *TAMP_Type) SetFLTCR_TAMPFREQ(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x7)|value)
}
func (o *TAMP_Type) GetFLTCR_TAMPFREQ() uint32 {
	return volatile.LoadUint32(&o.FLTCR.Reg) & 0x7
}
func (o *TAMP_Type) SetFLTCR_TAMPFLT(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x18)|value<<3)
}
func (o *TAMP_Type) GetFLTCR_TAMPFLT() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x18) >> 3
}
func (o *TAMP_Type) SetFLTCR_TAMPPRCH(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x60)|value<<5)
}
func (o *TAMP_Type) GetFLTCR_TAMPPRCH() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x60) >> 5
}
func (o *TAMP_Type) SetFLTCR_TAMPPUDIS(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetFLTCR_TAMPPUDIS() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x80) >> 7
}

// TAMP.IER: TAMP interrupt enable register
func (o *TAMP_Type) SetIER_TAMP1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetIER_TAMP1IE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *TAMP_Type) SetIER_TAMP2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetIER_TAMP2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetIER_TAMP3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetIER_TAMP3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetIER_ITAMP3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetIER_ITAMP3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetIER_ITAMP4IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000)|value<<19)
}
func (o *TAMP_Type) GetIER_ITAMP4IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000) >> 19
}
func (o *TAMP_Type) SetIER_ITAMP5IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetIER_ITAMP5IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetIER_ITAMP6IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetIER_ITAMP6IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200000) >> 21
}

// TAMP.SR: TAMP status register
func (o *TAMP_Type) SetSR_TAMP1F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSR_TAMP1F() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TAMP_Type) SetSR_TAMP2F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSR_TAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSR_TAMP3F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSR_TAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSR_ITAMP3F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSR_ITAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSR_ITAMP4F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000)|value<<19)
}
func (o *TAMP_Type) GetSR_ITAMP4F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000) >> 19
}
func (o *TAMP_Type) SetSR_ITAMP5F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSR_ITAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSR_ITAMP6F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetSR_ITAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}

// TAMP.MISR: TAMP masked interrupt status register
func (o *TAMP_Type) SetMISR_TAMP1MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetMISR_TAMP1MF() uint32 {
	return volatile.LoadUint32(&o.MISR.Reg) & 0x1
}
func (o *TAMP_Type) SetMISR_TAMP2MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetMISR_TAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetMISR_TAMP3MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetMISR_TAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetMISR_ITAMP3MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetMISR_ITAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetMISR_ITAMP4MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x80000)|value<<19)
}
func (o *TAMP_Type) GetMISR_ITAMP4MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x80000) >> 19
}
func (o *TAMP_Type) SetMISR_ITAMP5MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetMISR_ITAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetMISR_ITAMP6MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetMISR_ITAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x200000) >> 21
}

// TAMP.SCR: TAMP status clear register
func (o *TAMP_Type) SetSCR_CTAMP1F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSCR_CTAMP1F() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *TAMP_Type) SetSCR_CTAMP2F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSCR_CTAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSCR_CTAMP3F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSCR_CTAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSCR_CITAMP3F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSCR_CITAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSCR_CITAMP4F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x80000)|value<<19)
}
func (o *TAMP_Type) GetSCR_CITAMP4F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x80000) >> 19
}
func (o *TAMP_Type) SetSCR_CITAMP5F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSCR_CITAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSCR_CITAMP6F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetSCR_CITAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x200000) >> 21
}

// TAMP.BKP0R: TAMP backup %s register
func (o *TAMP_Type) SetBKP0R(value uint32) {
	volatile.StoreUint32(&o.BKP0R.Reg, value)
}
func (o *TAMP_Type) GetBKP0R() uint32 {
	return volatile.LoadUint32(&o.BKP0R.Reg)
}

// TAMP.BKP1R: TAMP backup %s register
func (o *TAMP_Type) SetBKP1R(value uint32) {
	volatile.StoreUint32(&o.BKP1R.Reg, value)
}
func (o *TAMP_Type) GetBKP1R() uint32 {
	return volatile.LoadUint32(&o.BKP1R.Reg)
}

// TAMP.BKP2R: TAMP backup %s register
func (o *TAMP_Type) SetBKP2R(value uint32) {
	volatile.StoreUint32(&o.BKP2R.Reg, value)
}
func (o *TAMP_Type) GetBKP2R() uint32 {
	return volatile.LoadUint32(&o.BKP2R.Reg)
}

// TAMP.BKP3R: TAMP backup %s register
func (o *TAMP_Type) SetBKP3R(value uint32) {
	volatile.StoreUint32(&o.BKP3R.Reg, value)
}
func (o *TAMP_Type) GetBKP3R() uint32 {
	return volatile.LoadUint32(&o.BKP3R.Reg)
}

// TAMP.BKP4R: TAMP backup %s register
func (o *TAMP_Type) SetBKP4R(value uint32) {
	volatile.StoreUint32(&o.BKP4R.Reg, value)
}
func (o *TAMP_Type) GetBKP4R() uint32 {
	return volatile.LoadUint32(&o.BKP4R.Reg)
}

// Advanced-timers
type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	CCMR2_Output volatile.Register32 // 0x1C
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	CCR3         volatile.Register32 // 0x3C
	CCR4         volatile.Register32 // 0x40
	BDTR         volatile.Register32 // 0x44
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	_            [4]byte
	CCMR3_Output volatile.Register32 // 0x54
	CCR5         volatile.Register32 // 0x58
	CCR6         volatile.Register32 // 0x5C
	AF1          volatile.Register32 // 0x60
	AF2          volatile.Register32 // 0x64
	TISEL        volatile.Register32 // 0x68
}

// TIM.CR1: control register 1
func (o *TIM_Type) SetCR1_CEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR1_CEN() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *TIM_Type) SetCR1_UDIS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetCR1_UDIS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetCR1_URS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR1_URS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR1_OPM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR1_OPM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR1_DIR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCR1_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCR1_CMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x60)|value<<5)
}
func (o *TIM_Type) GetCR1_CMS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x60) >> 5
}
func (o *TIM_Type) SetCR1_ARPE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR1_ARPE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR1_CKD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCR1_CKD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCR1_UIFREMAP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR1_UIFREMAP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}

// TIM.CR2: control register 2
func (o *TIM_Type) SetCR2_CCPC(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR2_CCPC() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *TIM_Type) SetCR2_CCUS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR2_CCUS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR2_CCDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR2_CCDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR2_MMS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetCR2_MMS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetCR2_TI1S(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR2_TI1S() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR2_OIS1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCR2_OIS1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCR2_OIS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCR2_OIS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCR2_OIS3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetCR2_OIS3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetCR2_OIS4(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCR2_OIS4() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCR2_OIS5(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCR2_OIS5() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCR2_OIS6(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetCR2_OIS6() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetCR2_OIS1N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR2_OIS1N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCR2_OIS2N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCR2_OIS2N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCR2_OIS3N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCR2_OIS3N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCR2_MMS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xf00000)|value<<20)
}
func (o *TIM_Type) GetCR2_MMS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xf00000) >> 20
}

// TIM.SMCR: slave mode control register
func (o *TIM_Type) SetSMCR_SMS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x7)|value)
}
func (o *TIM_Type) GetSMCR_SMS() uint32 {
	return volatile.LoadUint32(&o.SMCR.Reg) & 0x7
}
func (o *TIM_Type) SetSMCR_OCCS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSMCR_OCCS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSMCR_TS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetSMCR_TS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetSMCR_MSM(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSMCR_MSM() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSMCR_ETF(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetSMCR_ETF() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetSMCR_ETPS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x3000)|value<<12)
}
func (o *TIM_Type) GetSMCR_ETPS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x3000) >> 12
}
func (o *TIM_Type) SetSMCR_ECE(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetSMCR_ECE() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetSMCR_ETP(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetSMCR_ETP() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetSMCR_SMS_3(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSMCR_SMS_3() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetSMCR_TS2(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x300000)|value<<20)
}
func (o *TIM_Type) GetSMCR_TS2() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x300000) >> 20
}

// TIM.DIER: DMA/Interrupt enable register
func (o *TIM_Type) SetDIER_UIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetDIER_UIE() uint32 {
	return volatile.LoadUint32(&o.DIER.Reg) & 0x1
}
func (o *TIM_Type) SetDIER_CC1IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetDIER_CC1IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetDIER_CC2IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetDIER_CC2IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetDIER_CC3IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetDIER_CC3IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetDIER_CC4IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_CC4IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetDIER_COMIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_COMIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetDIER_TIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetDIER_TIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetDIER_BIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetDIER_BIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetDIER_UDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetDIER_UDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetDIER_CC1DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetDIER_CC1DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetDIER_CC2DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetDIER_CC2DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetDIER_CC3DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetDIER_CC3DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetDIER_CC4DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_CC4DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_COMDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_COMDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_TDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetDIER_TDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4000) >> 14
}

// TIM.SR: status register
func (o *TIM_Type) SetSR_UIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetSR_UIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TIM_Type) SetSR_CC1IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetSR_CC1IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetSR_CC2IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSR_CC2IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSR_CC3IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetSR_CC3IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetSR_CC4IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_CC4IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_COMIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_COMIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_TIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetSR_TIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetSR_BIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSR_BIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSR_B2IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetSR_B2IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetSR_CC1OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetSR_CC1OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetSR_CC2OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetSR_CC2OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetSR_CC3OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetSR_CC3OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetSR_CC4OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_CC4OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetSR_SBIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_SBIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetSR_CC5IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSR_CC5IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetSR_CC6IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetSR_CC6IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}

// TIM.EGR: event generation register
func (o *TIM_Type) SetEGR_UG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetEGR_UG() uint32 {
	return volatile.LoadUint32(&o.EGR.Reg) & 0x1
}
func (o *TIM_Type) SetEGR_CC1G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetEGR_CC1G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetEGR_CC2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetEGR_CC2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetEGR_CC3G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetEGR_CC3G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetEGR_CC4G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_CC4G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_COMG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_COMG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_TG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetEGR_TG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetEGR_BG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetEGR_BG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetEGR_B2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetEGR_B2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x100) >> 8
}

// TIM.CCMR1_Output: capture/compare mode register 1 (output mode)
func (o *TIM_Type) SetCCMR1_Output_CC1S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR1_Output_CC1S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR1_Output_CC2S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR1_Output_CC2S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x30000) >> 16
}
func (o *TIM_Type) SetCCMR1_Output_OC1FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR1_Output_OC1FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR1_Output_OC2FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR1_Output_OC2FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR1_Output_OC1PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR1_Output_OC1PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR1_Output_OC2PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR1_Output_OC2PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR1_Output_OC1M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR1_Output_OC2M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR1_Output_OC1CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR1_Output_OC1CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR1_Output_OC2CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR1_Output_OC2CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR1_Output_OC1M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR1_Output_OC2M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x0) >> 32
}

// TIM.CCMR2_Output: capture/compare mode register 2 (output mode)
func (o *TIM_Type) SetCCMR2_Output_CC3S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR2_Output_CC3S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR2_Output_CC4S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR2_Output_CC4S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x30000) >> 16
}
func (o *TIM_Type) SetCCMR2_Output_OC3FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR2_Output_OC3FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR2_Output_OC4FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR2_Output_OC4FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR2_Output_OC3PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR2_Output_OC3PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR2_Output_OC4PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR2_Output_OC4PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR2_Output_OC3M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR2_Output_OC4M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR2_Output_OC3CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR2_Output_OC3CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR2_Output_OC4CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR2_Output_OC4CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR2_Output_OC3M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR2_Output_OC4M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x0) >> 32
}

// TIM.CCER: capture/compare enable register
func (o *TIM_Type) SetCCER_CC1E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCCER_CC1E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCCER_CC2E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetCCER_CC2E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetCCER_CC3E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCCER_CC3E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCCER_CC4E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCCER_CC4E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCCER_CC5E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetCCER_CC5E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetCCER_CC6E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCER_CC6E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCER_CC1P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetCCER_CC1P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetCCER_CC2P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetCCER_CC2P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetCCER_CC3P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCCER_CC3P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCCER_CC4P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetCCER_CC4P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetCCER_CC5P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200000)|value<<21)
}
func (o *TIM_Type) GetCCER_CC5P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200000) >> 21
}
func (o *TIM_Type) SetCCER_CC6P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetCCER_CC6P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetCCER_CC1NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetCCER_CC1NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetCCER_CC2NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCER_CC2NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCER_CC3NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetCCER_CC3NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetCCER_CC1NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCCER_CC1NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCCER_CC2NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCER_CC2NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCER_CC3NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCER_CC3NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCER_CC4NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCER_CC4NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80000) >> 19
}

// TIM.CNT: counter
func (o *TIM_Type) SetCNT(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCNT() uint32 {
	return volatile.LoadUint32(&o.CNT.Reg) & 0xffff
}
func (o *TIM_Type) SetCNT_UIFCPY(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCNT_UIFCPY() uint32 {
	return (volatile.LoadUint32(&o.CNT.Reg) & 0x80000000) >> 31
}

// TIM.PSC: prescaler
func (o *TIM_Type) SetPSC(value uint32) {
	volatile.StoreUint32(&o.PSC.Reg, volatile.LoadUint32(&o.PSC.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetPSC() uint32 {
	return volatile.LoadUint32(&o.PSC.Reg) & 0xffff
}

// TIM.ARR: auto-reload register
func (o *TIM_Type) SetARR(value uint32) {
	volatile.StoreUint32(&o.ARR.Reg, volatile.LoadUint32(&o.ARR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetARR() uint32 {
	return volatile.LoadUint32(&o.ARR.Reg) & 0xffff
}

// TIM.RCR: repetition counter register
func (o *TIM_Type) SetRCR_REP(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetRCR_REP() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// TIM.CCR1: capture/compare register
func (o *TIM_Type) SetCCR1_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR1_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0xffff
}

// TIM.CCR2: capture/compare register
func (o *TIM_Type) SetCCR2_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR2_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0xffff
}

// TIM.CCR3: capture/compare register
func (o *TIM_Type) SetCCR3_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR3_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR3.Reg) & 0xffff
}

// TIM.CCR4: capture/compare register
func (o *TIM_Type) SetCCR4_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR4_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR4.Reg) & 0xffff
}

// TIM.BDTR: break and dead-time register
func (o *TIM_Type) SetBDTR_DTG(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xff)|value)
}
func (o *TIM_Type) GetBDTR_DTG() uint32 {
	return volatile.LoadUint32(&o.BDTR.Reg) & 0xff
}
func (o *TIM_Type) SetBDTR_LOCK(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetBDTR_LOCK() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetBDTR_OSSI(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetBDTR_OSSI() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetBDTR_OSSR(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetBDTR_OSSR() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetBDTR_BKE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetBDTR_BKE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetBDTR_BKP(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetBDTR_BKP() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetBDTR_AOE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetBDTR_AOE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetBDTR_MOE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetBDTR_MOE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetBDTR_BKF(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetBDTR_BKF() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetBDTR_BK2F(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xf00000)|value<<20)
}
func (o *TIM_Type) GetBDTR_BK2F() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0xf00000) >> 20
}
func (o *TIM_Type) SetBDTR_BK2E(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetBDTR_BK2E() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetBDTR_BK2P(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetBDTR_BK2P() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetBDTR_BKDSRM(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x4000000)|value<<26)
}
func (o *TIM_Type) GetBDTR_BKDSRM() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x4000000) >> 26
}
func (o *TIM_Type) SetBDTR_BK2DSRM(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x8000000)|value<<27)
}
func (o *TIM_Type) GetBDTR_BK2DSRM() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x8000000) >> 27
}
func (o *TIM_Type) SetBDTR_BKBID(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x10000000)|value<<28)
}
func (o *TIM_Type) GetBDTR_BKBID() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x10000000) >> 28
}
func (o *TIM_Type) SetBDTR_BK2BID(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x20000000)|value<<29)
}
func (o *TIM_Type) GetBDTR_BK2BID() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x20000000) >> 29
}

// TIM.DCR: DMA control register
func (o *TIM_Type) SetDCR_DBA(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f)|value)
}
func (o *TIM_Type) GetDCR_DBA() uint32 {
	return volatile.LoadUint32(&o.DCR.Reg) & 0x1f
}
func (o *TIM_Type) SetDCR_DBL(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f00)|value<<8)
}
func (o *TIM_Type) GetDCR_DBL() uint32 {
	return (volatile.LoadUint32(&o.DCR.Reg) & 0x1f00) >> 8
}

// TIM.DMAR: DMA address for full transfer
func (o *TIM_Type) SetDMAR(value uint32) {
	volatile.StoreUint32(&o.DMAR.Reg, value)
}
func (o *TIM_Type) GetDMAR() uint32 {
	return volatile.LoadUint32(&o.DMAR.Reg)
}

// TIM.CCMR3_Output: capture/compare mode register 2 (output mode)
func (o *TIM_Type) SetCCMR3_Output_OC5M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR3_Output_OC5M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR3_Output_OC6M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR3_Output_OC6M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x0) >> 32
}
func (o *TIM_Type) SetCCMR3_Output_OC5CE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR3_Output_OC5CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR3_Output_OC6CE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR3_Output_OC6CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR3_Output_OC5M(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR3_Output_OC5M() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR3_Output_OC6M(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR3_Output_OC6M() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR3_Output_OC5PE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR3_Output_OC5PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR3_Output_OC6PE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR3_Output_OC6PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR3_Output_OC5FE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR3_Output_OC5FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR3_Output_OC6FE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR3_Output_OC6FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x40000) >> 18
}

// TIM.CCR5: capture/compare register
func (o *TIM_Type) SetCCR5_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR5_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR5.Reg) & 0xffff
}
func (o *TIM_Type) SetCCR5_GC5C1(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x20000000)|value<<29)
}
func (o *TIM_Type) GetCCR5_GC5C1() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x20000000) >> 29
}
func (o *TIM_Type) SetCCR5_GC5C2(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x40000000)|value<<30)
}
func (o *TIM_Type) GetCCR5_GC5C2() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x40000000) >> 30
}
func (o *TIM_Type) SetCCR5_GC5C3(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCCR5_GC5C3() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x80000000) >> 31
}

// TIM.CCR6: capture/compare register
func (o *TIM_Type) SetCCR6_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR6_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR6.Reg) & 0xffff
}

// TIM.AF1: TIM1 alternate function option register 1
func (o *TIM_Type) SetAF1_BKINE(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetAF1_BKINE() uint32 {
	return volatile.LoadUint32(&o.AF1.Reg) & 0x1
}
func (o *TIM_Type) SetAF1_BKINP(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetAF1_BKINP() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetAF1_ETRSEL(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x3c000)|value<<14)
}
func (o *TIM_Type) GetAF1_ETRSEL() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x3c000) >> 14
}

// TIM.AF2: TIM1 alternate function option register 2
func (o *TIM_Type) SetAF2_BK2INE(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetAF2_BK2INE() uint32 {
	return volatile.LoadUint32(&o.AF2.Reg) & 0x1
}
func (o *TIM_Type) SetAF2_BK2INP(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetAF2_BK2INP() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x200) >> 9
}

// TIM.TISEL: TIM1 timer input selection register
func (o *TIM_Type) SetTISEL_TI1SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf)|value)
}
func (o *TIM_Type) GetTISEL_TI1SEL() uint32 {
	return volatile.LoadUint32(&o.TISEL.Reg) & 0xf
}
func (o *TIM_Type) SetTISEL_TI2SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetTISEL_TI2SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetTISEL_TI3SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetTISEL_TI3SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetTISEL_TI4SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf000000)|value<<24)
}
func (o *TIM_Type) GetTISEL_TI4SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf000000) >> 24
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// USART.CR1: Control register 1
func (o *USART_Type) SetCR1_UE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR1_UE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *USART_Type) SetCR1_UESM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR1_UESM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR1_RE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR1_RE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR1_TE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR1_TE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR1_IDLEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR1_IDLEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR1_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR1_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR1_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR1_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR1_PEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR1_PEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR1_PS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR1_PS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR1_PCE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR1_PCE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR1_WAKE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR1_WAKE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR1_M0(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR1_M0() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR1_MME(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR1_MME() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR1_CMIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR1_CMIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR1_OVER8(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR1_OVER8() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR1_DEDT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *USART_Type) GetCR1_DEDT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f0000) >> 16
}
func (o *USART_Type) SetCR1_DEAT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3e00000)|value<<21)
}
func (o *USART_Type) GetCR1_DEAT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x3e00000) >> 21
}
func (o *USART_Type) SetCR1_RTOIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetCR1_RTOIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetCR1_EOBIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetCR1_EOBIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000000) >> 27
}
func (o *USART_Type) SetCR1_M1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR1_M1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR1_FIFOEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *USART_Type) GetCR1_FIFOEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *USART_Type) SetCR1_TXFEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *USART_Type) GetCR1_TXFEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *USART_Type) SetCR1_RXFFIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *USART_Type) GetCR1_RXFFIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}

// USART.CR2: Control register 2
func (o *USART_Type) SetCR2_SLVEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR2_SLVEN() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *USART_Type) SetCR2_DIS_NSS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR2_DIS_NSS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR2_ADDM7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR2_ADDM7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR2_LBDL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR2_LBDL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR2_LBDIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR2_LBDIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR2_LBCL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR2_LBCL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR2_CPHA(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR2_CPHA() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR2_CPOL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR2_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR2_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR2_CLKEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3000)|value<<12)
}
func (o *USART_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x3000) >> 12
}
func (o *USART_Type) SetCR2_LINEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR2_LINEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR2_SWAP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR2_SWAP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR2_RXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetCR2_RXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetCR2_TXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetCR2_TXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetCR2_DATAINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetCR2_DATAINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetCR2_MSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetCR2_MSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetCR2_ABREN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetCR2_ABREN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetCR2_ABRMOD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x600000)|value<<21)
}
func (o *USART_Type) GetCR2_ABRMOD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x600000) >> 21
}
func (o *USART_Type) SetCR2_RTOEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR2_RTOEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR2_ADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetCR2_ADD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff000000) >> 24
}

// USART.CR3: Control register 3
func (o *USART_Type) SetCR3_EIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR3_EIE() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *USART_Type) SetCR3_IREN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR3_IREN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR3_IRLP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR3_IRLP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR3_HDSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR3_HDSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR3_NACK(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR3_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR3_SCEN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR3_SCEN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR3_DMAR(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR3_DMAR() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR3_DMAT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR3_DMAT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR3_RTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR3_RTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR3_CTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR3_CTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR3_CTSIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR3_CTSIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR3_ONEBIT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR3_ONEBIT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR3_OVRDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR3_OVRDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR3_DDRE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR3_DDRE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR3_DEM(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR3_DEM() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR3_DEP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR3_DEP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR3_SCARCNT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000)|value<<17)
}
func (o *USART_Type) GetCR3_SCARCNT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000) >> 17
}
func (o *USART_Type) SetCR3_WUS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x300000)|value<<20)
}
func (o *USART_Type) GetCR3_WUS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x300000) >> 20
}
func (o *USART_Type) SetCR3_WUFIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetCR3_WUFIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetCR3_TXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR3_TXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR3_TCBGTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetCR3_TCBGTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetCR3_RXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe000000)|value<<25)
}
func (o *USART_Type) GetCR3_RXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe000000) >> 25
}
func (o *USART_Type) SetCR3_RXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR3_RXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR3_TXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000000)|value<<29)
}
func (o *USART_Type) GetCR3_TXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000000) >> 29
}

// USART.BRR: Baud rate register
func (o *USART_Type) SetBRR(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetBRR() uint32 {
	return volatile.LoadUint32(&o.BRR.Reg) & 0xffff
}

// USART.GTPR: Guard time and prescaler register
func (o *USART_Type) SetGTPR_PSC(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetGTPR_PSC() uint32 {
	return volatile.LoadUint32(&o.GTPR.Reg) & 0xff
}
func (o *USART_Type) SetGTPR_GT(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff00)|value<<8)
}
func (o *USART_Type) GetGTPR_GT() uint32 {
	return (volatile.LoadUint32(&o.GTPR.Reg) & 0xff00) >> 8
}

// USART.RTOR: Receiver timeout register
func (o *USART_Type) SetRTOR_RTO(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xffffff)|value)
}
func (o *USART_Type) GetRTOR_RTO() uint32 {
	return volatile.LoadUint32(&o.RTOR.Reg) & 0xffffff
}
func (o *USART_Type) SetRTOR_BLEN(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetRTOR_BLEN() uint32 {
	return (volatile.LoadUint32(&o.RTOR.Reg) & 0xff000000) >> 24
}

// USART.RQR: Request register
func (o *USART_Type) SetRQR_ABRRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetRQR_ABRRQ() uint32 {
	return volatile.LoadUint32(&o.RQR.Reg) & 0x1
}
func (o *USART_Type) SetRQR_SBKRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetRQR_SBKRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetRQR_MMRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetRQR_MMRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetRQR_RXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetRQR_RXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetRQR_TXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetRQR_TXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x10) >> 4
}

// USART.ISR: Interrupt & status register
func (o *USART_Type) SetISR_PE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetISR_PE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *USART_Type) SetISR_FE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetISR_FE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetISR_NE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetISR_NE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetISR_ORE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetISR_ORE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetISR_IDLE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetISR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetISR_RXFNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetISR_RXFNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetISR_TXFNF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetISR_TXFNF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetISR_LBDF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetISR_LBDF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetISR_CTSIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetISR_CTSIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetISR_CTS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetISR_CTS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetISR_RTOF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetISR_RTOF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetISR_EOBF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetISR_EOBF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetISR_UDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetISR_UDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetISR_ABRE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetISR_ABRE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetISR_ABRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetISR_ABRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetISR_CMF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetISR_CMF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetISR_SBKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetISR_SBKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetISR_RWU(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetISR_RWU() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetISR_WUF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetISR_WUF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetISR_TEACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *USART_Type) GetISR_TEACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *USART_Type) SetISR_REACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetISR_REACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetISR_TXFE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetISR_TXFE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetISR_RXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetISR_RXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetISR_TCBGT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *USART_Type) GetISR_TCBGT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *USART_Type) SetISR_RXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetISR_RXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetISR_TXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetISR_TXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}

// USART.ICR: Interrupt flag clear register
func (o *USART_Type) SetICR_PECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetICR_PECF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *USART_Type) SetICR_FECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetICR_FECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetICR_NECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetICR_NECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetICR_ORECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetICR_ORECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetICR_IDLECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetICR_IDLECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetICR_TXFECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetICR_TXFECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetICR_TCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetICR_TCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetICR_TCBGTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetICR_TCBGTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetICR_LBDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetICR_LBDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetICR_CTSCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetICR_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetICR_RTOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetICR_RTOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetICR_EOBCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetICR_EOBCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetICR_UDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetICR_UDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetICR_CMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetICR_CMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetICR_WUCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetICR_WUCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100000) >> 20
}

// USART.RDR: Receive data register
func (o *USART_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0x1ff
}

// USART.TDR: Transmit data register
func (o *USART_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0x1ff
}

// USART.PRESC: Prescaler register
func (o *USART_Type) SetPRESC_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.PRESC.Reg, volatile.LoadUint32(&o.PRESC.Reg)&^(0xf)|value)
}
func (o *USART_Type) GetPRESC_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.PRESC.Reg) & 0xf
}

// System window watchdog
type WWDG_Type struct {
	CR  volatile.Register32 // 0x0
	CFR volatile.Register32 // 0x4
	SR  volatile.Register32 // 0x8
}

// WWDG.CR: Control register
func (o *WWDG_Type) SetCR_T(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7f)|value)
}
func (o *WWDG_Type) GetCR_T() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7f
}
func (o *WWDG_Type) SetCR_WDGA(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *WWDG_Type) GetCR_WDGA() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}

// WWDG.CFR: Configuration register
func (o *WWDG_Type) SetCFR_W(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x7f)|value)
}
func (o *WWDG_Type) GetCFR_W() uint32 {
	return volatile.LoadUint32(&o.CFR.Reg) & 0x7f
}
func (o *WWDG_Type) SetCFR_EWI(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x200)|value<<9)
}
func (o *WWDG_Type) GetCFR_EWI() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x200) >> 9
}
func (o *WWDG_Type) SetCFR_WDGTB(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x3800)|value<<11)
}
func (o *WWDG_Type) GetCFR_WDGTB() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x3800) >> 11
}

// WWDG.SR: Status register
func (o *WWDG_Type) SetSR_EWIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *WWDG_Type) GetSR_EWIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// Constants for ADC: Analog to Digital ConverteR
const (
	// ISR: ADC interrupt and status register
	// Position of ADRDY field.
	ADC_ISR_ADRDY_Pos = 0x0
	// Bit mask of ADRDY field.
	ADC_ISR_ADRDY_Msk = 0x1
	// Bit ADRDY.
	ADC_ISR_ADRDY = 0x1
	// ADC not yet ready to start conversion
	ADC_ISR_ADRDY_NotReady = 0x0
	// ADC ready to start conversion
	ADC_ISR_ADRDY_Ready = 0x1
	// Clear the ADC ready flag
	ADC_ISR_ADRDY_Clear = 0x1
	// Position of EOSMP field.
	ADC_ISR_EOSMP_Pos = 0x1
	// Bit mask of EOSMP field.
	ADC_ISR_EOSMP_Msk = 0x2
	// Bit EOSMP.
	ADC_ISR_EOSMP = 0x2
	// Not at the end of the samplings phase
	ADC_ISR_EOSMP_NotAtEnd = 0x0
	// End of sampling phase reached
	ADC_ISR_EOSMP_AtEnd = 0x1
	// Clear the sampling phase flag
	ADC_ISR_EOSMP_Clear = 0x1
	// Position of EOC field.
	ADC_ISR_EOC_Pos = 0x2
	// Bit mask of EOC field.
	ADC_ISR_EOC_Msk = 0x4
	// Bit EOC.
	ADC_ISR_EOC = 0x4
	// Channel conversion is not complete
	ADC_ISR_EOC_NotComplete = 0x0
	// Channel conversion complete
	ADC_ISR_EOC_Complete = 0x1
	// Clear the channel conversion flag
	ADC_ISR_EOC_Clear = 0x1
	// Position of EOS field.
	ADC_ISR_EOS_Pos = 0x3
	// Bit mask of EOS field.
	ADC_ISR_EOS_Msk = 0x8
	// Bit EOS.
	ADC_ISR_EOS = 0x8
	// Conversion sequence is not complete
	ADC_ISR_EOS_NotComplete = 0x0
	// Conversion sequence complete
	ADC_ISR_EOS_Complete = 0x1
	// Clear the conversion sequence flag
	ADC_ISR_EOS_Clear = 0x1
	// Position of OVR field.
	ADC_ISR_OVR_Pos = 0x4
	// Bit mask of OVR field.
	ADC_ISR_OVR_Msk = 0x10
	// Bit OVR.
	ADC_ISR_OVR = 0x10
	// No overrun occurred
	ADC_ISR_OVR_NoOverrun = 0x0
	// Overrun occurred
	ADC_ISR_OVR_Overrun = 0x1
	// Clear the overrun flag
	ADC_ISR_OVR_Clear = 0x1
	// Position of AWD1 field.
	ADC_ISR_AWD1_Pos = 0x8
	// Bit mask of AWD1 field.
	ADC_ISR_AWD1_Msk = 0x100
	// Bit AWD1.
	ADC_ISR_AWD1 = 0x100
	// No analog watchdog event occurred
	ADC_ISR_AWD1_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD1_Event = 0x1
	// Clear the analog watchdog event flag
	ADC_ISR_AWD1_Clear = 0x1
	// Position of AWD2 field.
	ADC_ISR_AWD2_Pos = 0x9
	// Bit mask of AWD2 field.
	ADC_ISR_AWD2_Msk = 0x200
	// Bit AWD2.
	ADC_ISR_AWD2 = 0x200
	// No analog watchdog event occurred
	ADC_ISR_AWD2_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD2_Event = 0x1
	// Clear the analog watchdog event flag
	ADC_ISR_AWD2_Clear = 0x1
	// Position of AWD3 field.
	ADC_ISR_AWD3_Pos = 0xa
	// Bit mask of AWD3 field.
	ADC_ISR_AWD3_Msk = 0x400
	// Bit AWD3.
	ADC_ISR_AWD3 = 0x400
	// No analog watchdog event occurred
	ADC_ISR_AWD3_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD3_Event = 0x1
	// Clear the analog watchdog event flag
	ADC_ISR_AWD3_Clear = 0x1
	// Position of EOCAL field.
	ADC_ISR_EOCAL_Pos = 0xb
	// Bit mask of EOCAL field.
	ADC_ISR_EOCAL_Msk = 0x800
	// Bit EOCAL.
	ADC_ISR_EOCAL = 0x800
	// Calibration is not complete
	ADC_ISR_EOCAL_NotComplete = 0x0
	// Calibration complete
	ADC_ISR_EOCAL_Complete = 0x1
	// Clear the calibration flag
	ADC_ISR_EOCAL_Clear = 0x1
	// Position of CCRDY field.
	ADC_ISR_CCRDY_Pos = 0xd
	// Bit mask of CCRDY field.
	ADC_ISR_CCRDY_Msk = 0x2000
	// Bit CCRDY.
	ADC_ISR_CCRDY = 0x2000
	// Channel configuration update not applied
	ADC_ISR_CCRDY_NotComplete = 0x0
	// Channel configuration update is applied
	ADC_ISR_CCRDY_Complete = 0x1
	// Clear the channel configuration flag
	ADC_ISR_CCRDY_Clear = 0x1

	// IER: ADC interrupt enable register
	// Position of ADRDYIE field.
	ADC_IER_ADRDYIE_Pos = 0x0
	// Bit mask of ADRDYIE field.
	ADC_IER_ADRDYIE_Msk = 0x1
	// Bit ADRDYIE.
	ADC_IER_ADRDYIE = 0x1
	// ADRDY interrupt disabled
	ADC_IER_ADRDYIE_Disabled = 0x0
	// ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
	ADC_IER_ADRDYIE_Enabled = 0x1
	// Position of EOSMPIE field.
	ADC_IER_EOSMPIE_Pos = 0x1
	// Bit mask of EOSMPIE field.
	ADC_IER_EOSMPIE_Msk = 0x2
	// Bit EOSMPIE.
	ADC_IER_EOSMPIE = 0x2
	// EOSMP interrupt disabled
	ADC_IER_EOSMPIE_Disabled = 0x0
	// EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
	ADC_IER_EOSMPIE_Enabled = 0x1
	// Position of EOCIE field.
	ADC_IER_EOCIE_Pos = 0x2
	// Bit mask of EOCIE field.
	ADC_IER_EOCIE_Msk = 0x4
	// Bit EOCIE.
	ADC_IER_EOCIE = 0x4
	// EOC interrupt disabled
	ADC_IER_EOCIE_Disabled = 0x0
	// EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
	ADC_IER_EOCIE_Enabled = 0x1
	// Position of EOSIE field.
	ADC_IER_EOSIE_Pos = 0x3
	// Bit mask of EOSIE field.
	ADC_IER_EOSIE_Msk = 0x8
	// Bit EOSIE.
	ADC_IER_EOSIE = 0x8
	// EOS interrupt disabled
	ADC_IER_EOSIE_Disabled = 0x0
	// EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
	ADC_IER_EOSIE_Enabled = 0x1
	// Position of OVRIE field.
	ADC_IER_OVRIE_Pos = 0x4
	// Bit mask of OVRIE field.
	ADC_IER_OVRIE_Msk = 0x10
	// Bit OVRIE.
	ADC_IER_OVRIE = 0x10
	// Overrun interrupt disabled
	ADC_IER_OVRIE_Disabled = 0x0
	// Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
	ADC_IER_OVRIE_Enabled = 0x1
	// Position of AWD1IE field.
	ADC_IER_AWD1IE_Pos = 0x8
	// Bit mask of AWD1IE field.
	ADC_IER_AWD1IE_Msk = 0x100
	// Bit AWD1IE.
	ADC_IER_AWD1IE = 0x100
	// Analog watchdog interrupt disabled
	ADC_IER_AWD1IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD1IE_Enabled = 0x1
	// Position of AWD2IE field.
	ADC_IER_AWD2IE_Pos = 0x9
	// Bit mask of AWD2IE field.
	ADC_IER_AWD2IE_Msk = 0x200
	// Bit AWD2IE.
	ADC_IER_AWD2IE = 0x200
	// Analog watchdog interrupt disabled
	ADC_IER_AWD2IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD2IE_Enabled = 0x1
	// Position of AWD3IE field.
	ADC_IER_AWD3IE_Pos = 0xa
	// Bit mask of AWD3IE field.
	ADC_IER_AWD3IE_Msk = 0x400
	// Bit AWD3IE.
	ADC_IER_AWD3IE = 0x400
	// Analog watchdog interrupt disabled
	ADC_IER_AWD3IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD3IE_Enabled = 0x1
	// Position of EOCALIE field.
	ADC_IER_EOCALIE_Pos = 0xb
	// Bit mask of EOCALIE field.
	ADC_IER_EOCALIE_Msk = 0x800
	// Bit EOCALIE.
	ADC_IER_EOCALIE = 0x800
	// End of calibration interrupt disabled
	ADC_IER_EOCALIE_Disabled = 0x0
	// End of calibration interrupt enabled
	ADC_IER_EOCALIE_Enabled = 0x1
	// Position of CCRDYIE field.
	ADC_IER_CCRDYIE_Pos = 0xd
	// Bit mask of CCRDYIE field.
	ADC_IER_CCRDYIE_Msk = 0x2000
	// Bit CCRDYIE.
	ADC_IER_CCRDYIE = 0x2000
	// Channel configuration ready interrupt disabled
	ADC_IER_CCRDYIE_Disabled = 0x0
	// Channel configuration ready interrupt enabled
	ADC_IER_CCRDYIE_Enabled = 0x1

	// CR: ADC control register
	// Position of ADEN field.
	ADC_CR_ADEN_Pos = 0x0
	// Bit mask of ADEN field.
	ADC_CR_ADEN_Msk = 0x1
	// Bit ADEN.
	ADC_CR_ADEN = 0x1
	// ADC disabled
	ADC_CR_ADEN_Disabled = 0x0
	// ADC enabled
	ADC_CR_ADEN_Enabled = 0x1
	// Position of ADDIS field.
	ADC_CR_ADDIS_Pos = 0x1
	// Bit mask of ADDIS field.
	ADC_CR_ADDIS_Msk = 0x2
	// Bit ADDIS.
	ADC_CR_ADDIS = 0x2
	// No disable command active
	ADC_CR_ADDIS_NotDisabling = 0x0
	// ADC disabling
	ADC_CR_ADDIS_Disabling = 0x1
	// Disable the ADC
	ADC_CR_ADDIS_Disable = 0x1
	// Position of ADSTART field.
	ADC_CR_ADSTART_Pos = 0x2
	// Bit mask of ADSTART field.
	ADC_CR_ADSTART_Msk = 0x4
	// Bit ADSTART.
	ADC_CR_ADSTART = 0x4
	// No conversion ongoing
	ADC_CR_ADSTART_NotActive = 0x0
	// ADC operating and may be converting
	ADC_CR_ADSTART_Active = 0x1
	// Start the ADC conversion (may be delayed for hardware triggers)
	ADC_CR_ADSTART_StartConversion = 0x1
	// Position of ADSTP field.
	ADC_CR_ADSTP_Pos = 0x4
	// Bit mask of ADSTP field.
	ADC_CR_ADSTP_Msk = 0x10
	// Bit ADSTP.
	ADC_CR_ADSTP = 0x10
	// No stop command active
	ADC_CR_ADSTP_NotStopping = 0x0
	// ADC stopping conversion
	ADC_CR_ADSTP_Stopping = 0x1
	// Stop the active conversion
	ADC_CR_ADSTP_StopConversion = 0x1
	// Position of ADVREGEN field.
	ADC_CR_ADVREGEN_Pos = 0x1c
	// Bit mask of ADVREGEN field.
	ADC_CR_ADVREGEN_Msk = 0x10000000
	// Bit ADVREGEN.
	ADC_CR_ADVREGEN = 0x10000000
	// ADC voltage regulator disabled
	ADC_CR_ADVREGEN_Disabled = 0x0
	// ADC voltage regulator enabled
	ADC_CR_ADVREGEN_Enabled = 0x1
	// Position of ADCAL field.
	ADC_CR_ADCAL_Pos = 0x1f
	// Bit mask of ADCAL field.
	ADC_CR_ADCAL_Msk = 0x80000000
	// Bit ADCAL.
	ADC_CR_ADCAL = 0x80000000
	// ADC calibration either not yet performed or completed
	ADC_CR_ADCAL_NotCalibrating = 0x0
	// ADC calibration in progress
	ADC_CR_ADCAL_Calibrating = 0x1
	// Start the ADC calibration sequence
	ADC_CR_ADCAL_StartCalibration = 0x1

	// CFGR1: ADC configuration register 1
	// Position of DMAEN field.
	ADC_CFGR1_DMAEN_Pos = 0x0
	// Bit mask of DMAEN field.
	ADC_CFGR1_DMAEN_Msk = 0x1
	// Bit DMAEN.
	ADC_CFGR1_DMAEN = 0x1
	// DMA disabled
	ADC_CFGR1_DMAEN_Disabled = 0x0
	// DMA enabled
	ADC_CFGR1_DMAEN_Enabled = 0x1
	// Position of DMACFG field.
	ADC_CFGR1_DMACFG_Pos = 0x1
	// Bit mask of DMACFG field.
	ADC_CFGR1_DMACFG_Msk = 0x2
	// Bit DMACFG.
	ADC_CFGR1_DMACFG = 0x2
	// DMA one shot mode selected
	ADC_CFGR1_DMACFG_OneShot = 0x0
	// DMA circular mode selected
	ADC_CFGR1_DMACFG_Circular = 0x1
	// Position of SCANDIR field.
	ADC_CFGR1_SCANDIR_Pos = 0x2
	// Bit mask of SCANDIR field.
	ADC_CFGR1_SCANDIR_Msk = 0x4
	// Bit SCANDIR.
	ADC_CFGR1_SCANDIR = 0x4
	// Upward scan (from CHSEL0 to CHSEL17)
	ADC_CFGR1_SCANDIR_Upward = 0x0
	// Backward scan (from CHSEL17 to CHSEL0)
	ADC_CFGR1_SCANDIR_Backward = 0x1
	// Position of RES field.
	ADC_CFGR1_RES_Pos = 0x3
	// Bit mask of RES field.
	ADC_CFGR1_RES_Msk = 0x18
	// 12 bits
	ADC_CFGR1_RES_Bits12 = 0x0
	// 10 bits
	ADC_CFGR1_RES_Bits10 = 0x1
	// 8 bits
	ADC_CFGR1_RES_Bits8 = 0x2
	// 6 bits
	ADC_CFGR1_RES_Bits6 = 0x3
	// Position of ALIGN field.
	ADC_CFGR1_ALIGN_Pos = 0x5
	// Bit mask of ALIGN field.
	ADC_CFGR1_ALIGN_Msk = 0x20
	// Bit ALIGN.
	ADC_CFGR1_ALIGN = 0x20
	// Right alignment
	ADC_CFGR1_ALIGN_Right = 0x0
	// Left alignment
	ADC_CFGR1_ALIGN_Left = 0x1
	// Position of EXTSEL field.
	ADC_CFGR1_EXTSEL_Pos = 0x6
	// Bit mask of EXTSEL field.
	ADC_CFGR1_EXTSEL_Msk = 0x1c0
	// Timer 1 TRGO 2 event
	ADC_CFGR1_EXTSEL_TIM1_TRGO2 = 0x0
	// Timer 1 CC4 event
	ADC_CFGR1_EXTSEL_TIM1_CC4 = 0x1
	// Timer 2 TRGO event
	ADC_CFGR1_EXTSEL_TIM2_TRGO = 0x2
	// Timer 3 TRGO event
	ADC_CFGR1_EXTSEL_TIM3_TRGO = 0x3
	// Timer 15 TRGO event
	ADC_CFGR1_EXTSEL_TIM15_TRGO = 0x4
	// Timer 6 TRGO event
	ADC_CFGR1_EXTSEL_TIM6_TRGO = 0x5
	// Timer 4 TRGO event
	ADC_CFGR1_EXTSEL_TIM4_TRGO = 0x6
	// EXTI line 11 event
	ADC_CFGR1_EXTSEL_EXTI11 = 0x7
	// Position of EXTEN field.
	ADC_CFGR1_EXTEN_Pos = 0xa
	// Bit mask of EXTEN field.
	ADC_CFGR1_EXTEN_Msk = 0xc00
	// Hardware trigger detection disabled
	ADC_CFGR1_EXTEN_Disabled = 0x0
	// Hardware trigger detection on the rising edge
	ADC_CFGR1_EXTEN_RisingEdge = 0x1
	// Hardware trigger detection on the falling edge
	ADC_CFGR1_EXTEN_FallingEdge = 0x2
	// Hardware trigger detection on both the rising and falling edges
	ADC_CFGR1_EXTEN_BothEdges = 0x3
	// Position of OVRMOD field.
	ADC_CFGR1_OVRMOD_Pos = 0xc
	// Bit mask of OVRMOD field.
	ADC_CFGR1_OVRMOD_Msk = 0x1000
	// Bit OVRMOD.
	ADC_CFGR1_OVRMOD = 0x1000
	// ADC_DR register is preserved with the old data when an overrun is detected
	ADC_CFGR1_OVRMOD_Preserve = 0x0
	// ADC_DR register is overwritten with the last conversion result when an overrun is detected
	ADC_CFGR1_OVRMOD_Overwrite = 0x1
	// Position of CONT field.
	ADC_CFGR1_CONT_Pos = 0xd
	// Bit mask of CONT field.
	ADC_CFGR1_CONT_Msk = 0x2000
	// Bit CONT.
	ADC_CFGR1_CONT = 0x2000
	// Single conversion mode
	ADC_CFGR1_CONT_Single = 0x0
	// Continuous conversion mode
	ADC_CFGR1_CONT_Continuous = 0x1
	// Position of WAIT field.
	ADC_CFGR1_WAIT_Pos = 0xe
	// Bit mask of WAIT field.
	ADC_CFGR1_WAIT_Msk = 0x4000
	// Bit WAIT.
	ADC_CFGR1_WAIT = 0x4000
	// Wait conversion mode off
	ADC_CFGR1_WAIT_Disabled = 0x0
	// Wait conversion mode on
	ADC_CFGR1_WAIT_Enabled = 0x1
	// Position of AUTOFF field.
	ADC_CFGR1_AUTOFF_Pos = 0xf
	// Bit mask of AUTOFF field.
	ADC_CFGR1_AUTOFF_Msk = 0x8000
	// Bit AUTOFF.
	ADC_CFGR1_AUTOFF = 0x8000
	// Auto-off mode disabled
	ADC_CFGR1_AUTOFF_Disabled = 0x0
	// Auto-off mode enabled
	ADC_CFGR1_AUTOFF_Enabled = 0x1
	// Position of DISCEN field.
	ADC_CFGR1_DISCEN_Pos = 0x10
	// Bit mask of DISCEN field.
	ADC_CFGR1_DISCEN_Msk = 0x10000
	// Bit DISCEN.
	ADC_CFGR1_DISCEN = 0x10000
	// Discontinuous mode disabled
	ADC_CFGR1_DISCEN_Disabled = 0x0
	// Discontinuous mode enabled
	ADC_CFGR1_DISCEN_Enabled = 0x1
	// Position of CHSELRMOD field.
	ADC_CFGR1_CHSELRMOD_Pos = 0x15
	// Bit mask of CHSELRMOD field.
	ADC_CFGR1_CHSELRMOD_Msk = 0x200000
	// Bit CHSELRMOD.
	ADC_CFGR1_CHSELRMOD = 0x200000
	// Each bit of the ADC_CHSELR register enables an input
	ADC_CFGR1_CHSELRMOD_BitPerInput = 0x0
	// ADC_CHSELR register is able to sequence up to 8 channels
	ADC_CFGR1_CHSELRMOD_Sequence = 0x1
	// Position of AWD1SGL field.
	ADC_CFGR1_AWD1SGL_Pos = 0x16
	// Bit mask of AWD1SGL field.
	ADC_CFGR1_AWD1SGL_Msk = 0x400000
	// Bit AWD1SGL.
	ADC_CFGR1_AWD1SGL = 0x400000
	// Analog watchdog 1 enabled on all channels
	ADC_CFGR1_AWD1SGL_AllChannels = 0x0
	// Analog watchdog 1 enabled on a single channel
	ADC_CFGR1_AWD1SGL_SingleChannel = 0x1
	// Position of AWD1EN field.
	ADC_CFGR1_AWD1EN_Pos = 0x17
	// Bit mask of AWD1EN field.
	ADC_CFGR1_AWD1EN_Msk = 0x800000
	// Bit AWD1EN.
	ADC_CFGR1_AWD1EN = 0x800000
	// Analog watchdog 1 disabled
	ADC_CFGR1_AWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled
	ADC_CFGR1_AWD1EN_Enabled = 0x1
	// Position of AWD1CH field.
	ADC_CFGR1_AWD1CH_Pos = 0x1a
	// Bit mask of AWD1CH field.
	ADC_CFGR1_AWD1CH_Msk = 0x7c000000

	// CFGR2: ADC configuration register 2
	// Position of OVSE field.
	ADC_CFGR2_OVSE_Pos = 0x0
	// Bit mask of OVSE field.
	ADC_CFGR2_OVSE_Msk = 0x1
	// Bit OVSE.
	ADC_CFGR2_OVSE = 0x1
	// Oversampler disabled
	ADC_CFGR2_OVSE_Disabled = 0x0
	// Oversampler enabled
	ADC_CFGR2_OVSE_Enabled = 0x1
	// Position of OVSR field.
	ADC_CFGR2_OVSR_Pos = 0x2
	// Bit mask of OVSR field.
	ADC_CFGR2_OVSR_Msk = 0x1c
	// 2x
	ADC_CFGR2_OVSR_Mul2 = 0x0
	// 4x
	ADC_CFGR2_OVSR_Mul4 = 0x1
	// 8x
	ADC_CFGR2_OVSR_Mul8 = 0x2
	// 16x
	ADC_CFGR2_OVSR_Mul16 = 0x3
	// 32x
	ADC_CFGR2_OVSR_Mul32 = 0x4
	// 64x
	ADC_CFGR2_OVSR_Mul64 = 0x5
	// 128x
	ADC_CFGR2_OVSR_Mul128 = 0x6
	// 256x
	ADC_CFGR2_OVSR_Mul256 = 0x7
	// Position of OVSS field.
	ADC_CFGR2_OVSS_Pos = 0x5
	// Bit mask of OVSS field.
	ADC_CFGR2_OVSS_Msk = 0x1e0
	// No shift
	ADC_CFGR2_OVSS_NoShift = 0x0
	// Shift 1-bit
	ADC_CFGR2_OVSS_Shift1 = 0x1
	// Shift 2-bits
	ADC_CFGR2_OVSS_Shift2 = 0x2
	// Shift 3-bits
	ADC_CFGR2_OVSS_Shift3 = 0x3
	// Shift 4-bits
	ADC_CFGR2_OVSS_Shift4 = 0x4
	// Shift 5-bits
	ADC_CFGR2_OVSS_Shift5 = 0x5
	// Shift 6-bits
	ADC_CFGR2_OVSS_Shift6 = 0x6
	// Shift 7-bits
	ADC_CFGR2_OVSS_Shift7 = 0x7
	// Shift 8-bits
	ADC_CFGR2_OVSS_Shift8 = 0x8
	// Position of TOVS field.
	ADC_CFGR2_TOVS_Pos = 0x9
	// Bit mask of TOVS field.
	ADC_CFGR2_TOVS_Msk = 0x200
	// Bit TOVS.
	ADC_CFGR2_TOVS = 0x200
	// All oversampled conversions for a channel are done consecutively after a trigger
	ADC_CFGR2_TOVS_TriggerAll = 0x0
	// Each oversampled conversion for a channel needs a trigger
	ADC_CFGR2_TOVS_TriggerEach = 0x1
	// Position of LFTRIG field.
	ADC_CFGR2_LFTRIG_Pos = 0x1d
	// Bit mask of LFTRIG field.
	ADC_CFGR2_LFTRIG_Msk = 0x20000000
	// Bit LFTRIG.
	ADC_CFGR2_LFTRIG = 0x20000000
	// Low Frequency Trigger Mode disabled
	ADC_CFGR2_LFTRIG_Disabled = 0x0
	// Low Frequency Trigger Mode enabled
	ADC_CFGR2_LFTRIG_Enabled = 0x1
	// Position of CKMODE field.
	ADC_CFGR2_CKMODE_Pos = 0x1e
	// Bit mask of CKMODE field.
	ADC_CFGR2_CKMODE_Msk = 0xc0000000
	// ADCCLK (Asynchronous clock mode)
	ADC_CFGR2_CKMODE_ADCLK = 0x0
	// PCLK/2 (Synchronous clock mode)
	ADC_CFGR2_CKMODE_PCLK_Div2 = 0x1
	// PCLK/4 (Synchronous clock mode)
	ADC_CFGR2_CKMODE_PCLK_Div4 = 0x2
	// PCLK (Synchronous clock mode)
	ADC_CFGR2_CKMODE_PCLK = 0x3

	// SMPR: ADC sampling time register
	// Position of SMP1 field.
	ADC_SMPR_SMP1_Pos = 0x4
	// Bit mask of SMP1 field.
	ADC_SMPR_SMP1_Msk = 0x70
	// 1.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles1_5 = 0x0
	// 3.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles3_5 = 0x1
	// 7.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles7_5 = 0x2
	// 12.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles12_5 = 0x3
	// 19.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles19_5 = 0x4
	// 39.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles39_5 = 0x5
	// 79.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles79_5 = 0x6
	// 160.5 ADC clock cycles
	ADC_SMPR_SMP1_Cycles160_5 = 0x7
	// Position of SMP2 field.
	ADC_SMPR_SMP2_Pos = 0x8
	// Bit mask of SMP2 field.
	ADC_SMPR_SMP2_Msk = 0x700
	// 1.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles1_5 = 0x0
	// 3.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles3_5 = 0x1
	// 7.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles7_5 = 0x2
	// 12.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles12_5 = 0x3
	// 19.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles19_5 = 0x4
	// 39.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles39_5 = 0x5
	// 79.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles79_5 = 0x6
	// 160.5 ADC clock cycles
	ADC_SMPR_SMP2_Cycles160_5 = 0x7
	// Position of SMPSEL0 field.
	ADC_SMPR_SMPSEL0_Pos = 0x9
	// Bit mask of SMPSEL0 field.
	ADC_SMPR_SMPSEL0_Msk = 0x200
	// Bit SMPSEL0.
	ADC_SMPR_SMPSEL0 = 0x200
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL0_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL0_Smp2 = 0x1
	// Position of SMPSEL1 field.
	ADC_SMPR_SMPSEL1_Pos = 0xa
	// Bit mask of SMPSEL1 field.
	ADC_SMPR_SMPSEL1_Msk = 0x400
	// Bit SMPSEL1.
	ADC_SMPR_SMPSEL1 = 0x400
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL1_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL1_Smp2 = 0x1
	// Position of SMPSEL2 field.
	ADC_SMPR_SMPSEL2_Pos = 0xb
	// Bit mask of SMPSEL2 field.
	ADC_SMPR_SMPSEL2_Msk = 0x800
	// Bit SMPSEL2.
	ADC_SMPR_SMPSEL2 = 0x800
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL2_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL2_Smp2 = 0x1
	// Position of SMPSEL3 field.
	ADC_SMPR_SMPSEL3_Pos = 0xc
	// Bit mask of SMPSEL3 field.
	ADC_SMPR_SMPSEL3_Msk = 0x1000
	// Bit SMPSEL3.
	ADC_SMPR_SMPSEL3 = 0x1000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL3_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL3_Smp2 = 0x1
	// Position of SMPSEL4 field.
	ADC_SMPR_SMPSEL4_Pos = 0xd
	// Bit mask of SMPSEL4 field.
	ADC_SMPR_SMPSEL4_Msk = 0x2000
	// Bit SMPSEL4.
	ADC_SMPR_SMPSEL4 = 0x2000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL4_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL4_Smp2 = 0x1
	// Position of SMPSEL5 field.
	ADC_SMPR_SMPSEL5_Pos = 0xe
	// Bit mask of SMPSEL5 field.
	ADC_SMPR_SMPSEL5_Msk = 0x4000
	// Bit SMPSEL5.
	ADC_SMPR_SMPSEL5 = 0x4000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL5_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL5_Smp2 = 0x1
	// Position of SMPSEL6 field.
	ADC_SMPR_SMPSEL6_Pos = 0xf
	// Bit mask of SMPSEL6 field.
	ADC_SMPR_SMPSEL6_Msk = 0x8000
	// Bit SMPSEL6.
	ADC_SMPR_SMPSEL6 = 0x8000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL6_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL6_Smp2 = 0x1
	// Position of SMPSEL7 field.
	ADC_SMPR_SMPSEL7_Pos = 0x10
	// Bit mask of SMPSEL7 field.
	ADC_SMPR_SMPSEL7_Msk = 0x10000
	// Bit SMPSEL7.
	ADC_SMPR_SMPSEL7 = 0x10000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL7_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL7_Smp2 = 0x1
	// Position of SMPSEL8 field.
	ADC_SMPR_SMPSEL8_Pos = 0x11
	// Bit mask of SMPSEL8 field.
	ADC_SMPR_SMPSEL8_Msk = 0x20000
	// Bit SMPSEL8.
	ADC_SMPR_SMPSEL8 = 0x20000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL8_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL8_Smp2 = 0x1
	// Position of SMPSEL9 field.
	ADC_SMPR_SMPSEL9_Pos = 0x12
	// Bit mask of SMPSEL9 field.
	ADC_SMPR_SMPSEL9_Msk = 0x40000
	// Bit SMPSEL9.
	ADC_SMPR_SMPSEL9 = 0x40000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL9_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL9_Smp2 = 0x1
	// Position of SMPSEL10 field.
	ADC_SMPR_SMPSEL10_Pos = 0x13
	// Bit mask of SMPSEL10 field.
	ADC_SMPR_SMPSEL10_Msk = 0x80000
	// Bit SMPSEL10.
	ADC_SMPR_SMPSEL10 = 0x80000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL10_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL10_Smp2 = 0x1
	// Position of SMPSEL11 field.
	ADC_SMPR_SMPSEL11_Pos = 0x14
	// Bit mask of SMPSEL11 field.
	ADC_SMPR_SMPSEL11_Msk = 0x100000
	// Bit SMPSEL11.
	ADC_SMPR_SMPSEL11 = 0x100000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL11_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL11_Smp2 = 0x1
	// Position of SMPSEL12 field.
	ADC_SMPR_SMPSEL12_Pos = 0x15
	// Bit mask of SMPSEL12 field.
	ADC_SMPR_SMPSEL12_Msk = 0x200000
	// Bit SMPSEL12.
	ADC_SMPR_SMPSEL12 = 0x200000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL12_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL12_Smp2 = 0x1
	// Position of SMPSEL13 field.
	ADC_SMPR_SMPSEL13_Pos = 0x16
	// Bit mask of SMPSEL13 field.
	ADC_SMPR_SMPSEL13_Msk = 0x400000
	// Bit SMPSEL13.
	ADC_SMPR_SMPSEL13 = 0x400000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL13_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL13_Smp2 = 0x1
	// Position of SMPSEL14 field.
	ADC_SMPR_SMPSEL14_Pos = 0x17
	// Bit mask of SMPSEL14 field.
	ADC_SMPR_SMPSEL14_Msk = 0x800000
	// Bit SMPSEL14.
	ADC_SMPR_SMPSEL14 = 0x800000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL14_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL14_Smp2 = 0x1
	// Position of SMPSEL15 field.
	ADC_SMPR_SMPSEL15_Pos = 0x18
	// Bit mask of SMPSEL15 field.
	ADC_SMPR_SMPSEL15_Msk = 0x1000000
	// Bit SMPSEL15.
	ADC_SMPR_SMPSEL15 = 0x1000000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL15_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL15_Smp2 = 0x1
	// Position of SMPSEL16 field.
	ADC_SMPR_SMPSEL16_Pos = 0x19
	// Bit mask of SMPSEL16 field.
	ADC_SMPR_SMPSEL16_Msk = 0x2000000
	// Bit SMPSEL16.
	ADC_SMPR_SMPSEL16 = 0x2000000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL16_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL16_Smp2 = 0x1
	// Position of SMPSEL17 field.
	ADC_SMPR_SMPSEL17_Pos = 0x1a
	// Bit mask of SMPSEL17 field.
	ADC_SMPR_SMPSEL17_Msk = 0x4000000
	// Bit SMPSEL17.
	ADC_SMPR_SMPSEL17 = 0x4000000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL17_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL17_Smp2 = 0x1
	// Position of SMPSEL18 field.
	ADC_SMPR_SMPSEL18_Pos = 0x1b
	// Bit mask of SMPSEL18 field.
	ADC_SMPR_SMPSEL18_Msk = 0x8000000
	// Bit SMPSEL18.
	ADC_SMPR_SMPSEL18 = 0x8000000
	// Sampling time of CHANNELx use the setting of SMP1 register
	ADC_SMPR_SMPSEL18_Smp1 = 0x0
	// Sampling time of CHANNELx use the setting of SMP2 register
	ADC_SMPR_SMPSEL18_Smp2 = 0x1

	// AWD1TR: ADC watchdog threshold register
	// Position of LT1 field.
	ADC_AWD1TR_LT1_Pos = 0x0
	// Bit mask of LT1 field.
	ADC_AWD1TR_LT1_Msk = 0xfff
	// Position of HT1 field.
	ADC_AWD1TR_HT1_Pos = 0x10
	// Bit mask of HT1 field.
	ADC_AWD1TR_HT1_Msk = 0xfff0000

	// AWD2TR: ADC watchdog threshold register
	// Position of LT2 field.
	ADC_AWD2TR_LT2_Pos = 0x0
	// Bit mask of LT2 field.
	ADC_AWD2TR_LT2_Msk = 0xfff
	// Position of HT2 field.
	ADC_AWD2TR_HT2_Pos = 0x10
	// Bit mask of HT2 field.
	ADC_AWD2TR_HT2_Msk = 0xfff0000

	// CHSELR0: ADC channel selection register [alternate]
	// Position of CHSEL0 field.
	ADC_CHSELR0_CHSEL0_Pos = 0x1
	// Bit mask of CHSEL0 field.
	ADC_CHSELR0_CHSEL0_Msk = 0x2
	// Bit CHSEL0.
	ADC_CHSELR0_CHSEL0 = 0x2
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL0_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL0_Selected = 0x1
	// Position of CHSEL1 field.
	ADC_CHSELR0_CHSEL1_Pos = 0x2
	// Bit mask of CHSEL1 field.
	ADC_CHSELR0_CHSEL1_Msk = 0x4
	// Bit CHSEL1.
	ADC_CHSELR0_CHSEL1 = 0x4
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL1_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL1_Selected = 0x1
	// Position of CHSEL2 field.
	ADC_CHSELR0_CHSEL2_Pos = 0x3
	// Bit mask of CHSEL2 field.
	ADC_CHSELR0_CHSEL2_Msk = 0x8
	// Bit CHSEL2.
	ADC_CHSELR0_CHSEL2 = 0x8
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL2_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL2_Selected = 0x1
	// Position of CHSEL3 field.
	ADC_CHSELR0_CHSEL3_Pos = 0x4
	// Bit mask of CHSEL3 field.
	ADC_CHSELR0_CHSEL3_Msk = 0x10
	// Bit CHSEL3.
	ADC_CHSELR0_CHSEL3 = 0x10
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL3_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL3_Selected = 0x1
	// Position of CHSEL4 field.
	ADC_CHSELR0_CHSEL4_Pos = 0x5
	// Bit mask of CHSEL4 field.
	ADC_CHSELR0_CHSEL4_Msk = 0x20
	// Bit CHSEL4.
	ADC_CHSELR0_CHSEL4 = 0x20
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL4_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL4_Selected = 0x1
	// Position of CHSEL5 field.
	ADC_CHSELR0_CHSEL5_Pos = 0x6
	// Bit mask of CHSEL5 field.
	ADC_CHSELR0_CHSEL5_Msk = 0x40
	// Bit CHSEL5.
	ADC_CHSELR0_CHSEL5 = 0x40
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL5_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL5_Selected = 0x1
	// Position of CHSEL6 field.
	ADC_CHSELR0_CHSEL6_Pos = 0x7
	// Bit mask of CHSEL6 field.
	ADC_CHSELR0_CHSEL6_Msk = 0x80
	// Bit CHSEL6.
	ADC_CHSELR0_CHSEL6 = 0x80
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL6_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL6_Selected = 0x1
	// Position of CHSEL7 field.
	ADC_CHSELR0_CHSEL7_Pos = 0x8
	// Bit mask of CHSEL7 field.
	ADC_CHSELR0_CHSEL7_Msk = 0x100
	// Bit CHSEL7.
	ADC_CHSELR0_CHSEL7 = 0x100
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL7_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL7_Selected = 0x1
	// Position of CHSEL8 field.
	ADC_CHSELR0_CHSEL8_Pos = 0x9
	// Bit mask of CHSEL8 field.
	ADC_CHSELR0_CHSEL8_Msk = 0x200
	// Bit CHSEL8.
	ADC_CHSELR0_CHSEL8 = 0x200
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL8_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL8_Selected = 0x1
	// Position of CHSEL9 field.
	ADC_CHSELR0_CHSEL9_Pos = 0xa
	// Bit mask of CHSEL9 field.
	ADC_CHSELR0_CHSEL9_Msk = 0x400
	// Bit CHSEL9.
	ADC_CHSELR0_CHSEL9 = 0x400
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL9_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL9_Selected = 0x1
	// Position of CHSEL10 field.
	ADC_CHSELR0_CHSEL10_Pos = 0xb
	// Bit mask of CHSEL10 field.
	ADC_CHSELR0_CHSEL10_Msk = 0x800
	// Bit CHSEL10.
	ADC_CHSELR0_CHSEL10 = 0x800
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL10_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL10_Selected = 0x1
	// Position of CHSEL11 field.
	ADC_CHSELR0_CHSEL11_Pos = 0xc
	// Bit mask of CHSEL11 field.
	ADC_CHSELR0_CHSEL11_Msk = 0x1000
	// Bit CHSEL11.
	ADC_CHSELR0_CHSEL11 = 0x1000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL11_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL11_Selected = 0x1
	// Position of CHSEL12 field.
	ADC_CHSELR0_CHSEL12_Pos = 0xd
	// Bit mask of CHSEL12 field.
	ADC_CHSELR0_CHSEL12_Msk = 0x2000
	// Bit CHSEL12.
	ADC_CHSELR0_CHSEL12 = 0x2000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL12_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL12_Selected = 0x1
	// Position of CHSEL13 field.
	ADC_CHSELR0_CHSEL13_Pos = 0xe
	// Bit mask of CHSEL13 field.
	ADC_CHSELR0_CHSEL13_Msk = 0x4000
	// Bit CHSEL13.
	ADC_CHSELR0_CHSEL13 = 0x4000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL13_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL13_Selected = 0x1
	// Position of CHSEL14 field.
	ADC_CHSELR0_CHSEL14_Pos = 0xf
	// Bit mask of CHSEL14 field.
	ADC_CHSELR0_CHSEL14_Msk = 0x8000
	// Bit CHSEL14.
	ADC_CHSELR0_CHSEL14 = 0x8000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL14_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL14_Selected = 0x1
	// Position of CHSEL15 field.
	ADC_CHSELR0_CHSEL15_Pos = 0x10
	// Bit mask of CHSEL15 field.
	ADC_CHSELR0_CHSEL15_Msk = 0x10000
	// Bit CHSEL15.
	ADC_CHSELR0_CHSEL15 = 0x10000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL15_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL15_Selected = 0x1
	// Position of CHSEL16 field.
	ADC_CHSELR0_CHSEL16_Pos = 0x11
	// Bit mask of CHSEL16 field.
	ADC_CHSELR0_CHSEL16_Msk = 0x20000
	// Bit CHSEL16.
	ADC_CHSELR0_CHSEL16 = 0x20000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL16_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL16_Selected = 0x1
	// Position of CHSEL17 field.
	ADC_CHSELR0_CHSEL17_Pos = 0x12
	// Bit mask of CHSEL17 field.
	ADC_CHSELR0_CHSEL17_Msk = 0x40000
	// Bit CHSEL17.
	ADC_CHSELR0_CHSEL17 = 0x40000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL17_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL17_Selected = 0x1
	// Position of CHSEL18 field.
	ADC_CHSELR0_CHSEL18_Pos = 0x13
	// Bit mask of CHSEL18 field.
	ADC_CHSELR0_CHSEL18_Msk = 0x80000
	// Bit CHSEL18.
	ADC_CHSELR0_CHSEL18 = 0x80000
	// Input Channel is not selected for conversion
	ADC_CHSELR0_CHSEL18_NotSelected = 0x0
	// Input Channel is selected for conversion
	ADC_CHSELR0_CHSEL18_Selected = 0x1

	// CHSELR1: channel selection register CHSELRMOD = 1 in ADC_CFGR1
	// Position of SQ1 field.
	ADC_CHSELR1_SQ1_Pos = 0x4
	// Bit mask of SQ1 field.
	ADC_CHSELR1_SQ1_Msk = 0xf0
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ1_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ1_EOS = 0xf
	// Position of SQ2 field.
	ADC_CHSELR1_SQ2_Pos = 0x8
	// Bit mask of SQ2 field.
	ADC_CHSELR1_SQ2_Msk = 0xf00
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ2_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ2_EOS = 0xf
	// Position of SQ3 field.
	ADC_CHSELR1_SQ3_Pos = 0xc
	// Bit mask of SQ3 field.
	ADC_CHSELR1_SQ3_Msk = 0xf000
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ3_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ3_EOS = 0xf
	// Position of SQ4 field.
	ADC_CHSELR1_SQ4_Pos = 0x10
	// Bit mask of SQ4 field.
	ADC_CHSELR1_SQ4_Msk = 0xf0000
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ4_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ4_EOS = 0xf
	// Position of SQ5 field.
	ADC_CHSELR1_SQ5_Pos = 0x14
	// Bit mask of SQ5 field.
	ADC_CHSELR1_SQ5_Msk = 0xf00000
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ5_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ5_EOS = 0xf
	// Position of SQ6 field.
	ADC_CHSELR1_SQ6_Pos = 0x18
	// Bit mask of SQ6 field.
	ADC_CHSELR1_SQ6_Msk = 0xf000000
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ6_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ6_EOS = 0xf
	// Position of SQ7 field.
	ADC_CHSELR1_SQ7_Pos = 0x1c
	// Bit mask of SQ7 field.
	ADC_CHSELR1_SQ7_Msk = 0xf0000000
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ7_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ7_EOS = 0xf
	// Position of SQ8 field.
	ADC_CHSELR1_SQ8_Pos = 0x20
	// Bit mask of SQ8 field.
	ADC_CHSELR1_SQ8_Msk = 0xf00000000
	// Channel 0 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch0 = 0x0
	// Channel 1 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch1 = 0x1
	// Channel 2 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch2 = 0x2
	// Channel 3 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch3 = 0x3
	// Channel 4 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch4 = 0x4
	// Channel 5 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch5 = 0x5
	// Channel 6 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch6 = 0x6
	// Channel 7 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch7 = 0x7
	// Channel 8 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch8 = 0x8
	// Channel 9 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch9 = 0x9
	// Channel 10 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch10 = 0xa
	// Channel 11 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch11 = 0xb
	// Channel 12 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch12 = 0xc
	// Channel 13 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch13 = 0xd
	// Channel 14 selected for the Nth conversion
	ADC_CHSELR1_SQ8_Ch14 = 0xe
	// End of sequence
	ADC_CHSELR1_SQ8_EOS = 0xf

	// AWD3TR: ADC watchdog threshold register
	// Position of LT3 field.
	ADC_AWD3TR_LT3_Pos = 0x0
	// Bit mask of LT3 field.
	ADC_AWD3TR_LT3_Msk = 0xfff
	// Position of HT3 field.
	ADC_AWD3TR_HT3_Pos = 0x10
	// Bit mask of HT3 field.
	ADC_AWD3TR_HT3_Msk = 0xfff0000

	// DR: ADC data register
	// Position of DATA field.
	ADC_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	ADC_DR_DATA_Msk = 0xffff

	// AWD2CR: ADC Analog Watchdog 2 Configuration register
	// Position of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Pos = 0x1
	// Bit mask of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Msk = 0x2
	// Bit AWD2CH0.
	ADC_AWD2CR_AWD2CH0 = 0x2
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH0_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH0_Monitored = 0x1
	// Position of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Pos = 0x2
	// Bit mask of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Msk = 0x4
	// Bit AWD2CH1.
	ADC_AWD2CR_AWD2CH1 = 0x4
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH1_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH1_Monitored = 0x1
	// Position of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Pos = 0x3
	// Bit mask of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Msk = 0x8
	// Bit AWD2CH2.
	ADC_AWD2CR_AWD2CH2 = 0x8
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH2_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH2_Monitored = 0x1
	// Position of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Pos = 0x4
	// Bit mask of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Msk = 0x10
	// Bit AWD2CH3.
	ADC_AWD2CR_AWD2CH3 = 0x10
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH3_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH3_Monitored = 0x1
	// Position of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Pos = 0x5
	// Bit mask of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Msk = 0x20
	// Bit AWD2CH4.
	ADC_AWD2CR_AWD2CH4 = 0x20
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH4_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH4_Monitored = 0x1
	// Position of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Pos = 0x6
	// Bit mask of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Msk = 0x40
	// Bit AWD2CH5.
	ADC_AWD2CR_AWD2CH5 = 0x40
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH5_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH5_Monitored = 0x1
	// Position of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Pos = 0x7
	// Bit mask of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Msk = 0x80
	// Bit AWD2CH6.
	ADC_AWD2CR_AWD2CH6 = 0x80
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH6_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH6_Monitored = 0x1
	// Position of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Pos = 0x8
	// Bit mask of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Msk = 0x100
	// Bit AWD2CH7.
	ADC_AWD2CR_AWD2CH7 = 0x100
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH7_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH7_Monitored = 0x1
	// Position of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Pos = 0x9
	// Bit mask of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Msk = 0x200
	// Bit AWD2CH8.
	ADC_AWD2CR_AWD2CH8 = 0x200
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH8_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH8_Monitored = 0x1
	// Position of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Pos = 0xa
	// Bit mask of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Msk = 0x400
	// Bit AWD2CH9.
	ADC_AWD2CR_AWD2CH9 = 0x400
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH9_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH9_Monitored = 0x1
	// Position of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Pos = 0xb
	// Bit mask of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Msk = 0x800
	// Bit AWD2CH10.
	ADC_AWD2CR_AWD2CH10 = 0x800
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH10_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH10_Monitored = 0x1
	// Position of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Pos = 0xc
	// Bit mask of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Msk = 0x1000
	// Bit AWD2CH11.
	ADC_AWD2CR_AWD2CH11 = 0x1000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH11_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH11_Monitored = 0x1
	// Position of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Pos = 0xd
	// Bit mask of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Msk = 0x2000
	// Bit AWD2CH12.
	ADC_AWD2CR_AWD2CH12 = 0x2000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH12_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH12_Monitored = 0x1
	// Position of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Pos = 0xe
	// Bit mask of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Msk = 0x4000
	// Bit AWD2CH13.
	ADC_AWD2CR_AWD2CH13 = 0x4000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH13_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH13_Monitored = 0x1
	// Position of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Pos = 0xf
	// Bit mask of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Msk = 0x8000
	// Bit AWD2CH14.
	ADC_AWD2CR_AWD2CH14 = 0x8000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH14_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH14_Monitored = 0x1
	// Position of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Pos = 0x10
	// Bit mask of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Msk = 0x10000
	// Bit AWD2CH15.
	ADC_AWD2CR_AWD2CH15 = 0x10000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH15_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH15_Monitored = 0x1
	// Position of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Pos = 0x11
	// Bit mask of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Msk = 0x20000
	// Bit AWD2CH16.
	ADC_AWD2CR_AWD2CH16 = 0x20000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH16_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH16_Monitored = 0x1
	// Position of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Pos = 0x12
	// Bit mask of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Msk = 0x40000
	// Bit AWD2CH17.
	ADC_AWD2CR_AWD2CH17 = 0x40000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH17_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH17_Monitored = 0x1
	// Position of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Pos = 0x13
	// Bit mask of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Msk = 0x80000
	// Bit AWD2CH18.
	ADC_AWD2CR_AWD2CH18 = 0x80000
	// ADC analog channel-x is not monitored by AWD2
	ADC_AWD2CR_AWD2CH18_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD2
	ADC_AWD2CR_AWD2CH18_Monitored = 0x1

	// AWD3CR: ADC Analog Watchdog 3 Configuration register
	// Position of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Pos = 0x1
	// Bit mask of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Msk = 0x2
	// Bit AWD3CH0.
	ADC_AWD3CR_AWD3CH0 = 0x2
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH0_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH0_Monitored = 0x1
	// Position of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Pos = 0x2
	// Bit mask of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Msk = 0x4
	// Bit AWD3CH1.
	ADC_AWD3CR_AWD3CH1 = 0x4
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH1_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH1_Monitored = 0x1
	// Position of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Pos = 0x3
	// Bit mask of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Msk = 0x8
	// Bit AWD3CH2.
	ADC_AWD3CR_AWD3CH2 = 0x8
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH2_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH2_Monitored = 0x1
	// Position of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Pos = 0x4
	// Bit mask of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Msk = 0x10
	// Bit AWD3CH3.
	ADC_AWD3CR_AWD3CH3 = 0x10
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH3_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH3_Monitored = 0x1
	// Position of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Pos = 0x5
	// Bit mask of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Msk = 0x20
	// Bit AWD3CH4.
	ADC_AWD3CR_AWD3CH4 = 0x20
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH4_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH4_Monitored = 0x1
	// Position of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Pos = 0x6
	// Bit mask of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Msk = 0x40
	// Bit AWD3CH5.
	ADC_AWD3CR_AWD3CH5 = 0x40
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH5_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH5_Monitored = 0x1
	// Position of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Pos = 0x7
	// Bit mask of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Msk = 0x80
	// Bit AWD3CH6.
	ADC_AWD3CR_AWD3CH6 = 0x80
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH6_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH6_Monitored = 0x1
	// Position of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Pos = 0x8
	// Bit mask of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Msk = 0x100
	// Bit AWD3CH7.
	ADC_AWD3CR_AWD3CH7 = 0x100
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH7_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH7_Monitored = 0x1
	// Position of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Pos = 0x9
	// Bit mask of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Msk = 0x200
	// Bit AWD3CH8.
	ADC_AWD3CR_AWD3CH8 = 0x200
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH8_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH8_Monitored = 0x1
	// Position of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Pos = 0xa
	// Bit mask of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Msk = 0x400
	// Bit AWD3CH9.
	ADC_AWD3CR_AWD3CH9 = 0x400
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH9_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH9_Monitored = 0x1
	// Position of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Pos = 0xb
	// Bit mask of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Msk = 0x800
	// Bit AWD3CH10.
	ADC_AWD3CR_AWD3CH10 = 0x800
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH10_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH10_Monitored = 0x1
	// Position of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Pos = 0xc
	// Bit mask of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Msk = 0x1000
	// Bit AWD3CH11.
	ADC_AWD3CR_AWD3CH11 = 0x1000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH11_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH11_Monitored = 0x1
	// Position of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Pos = 0xd
	// Bit mask of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Msk = 0x2000
	// Bit AWD3CH12.
	ADC_AWD3CR_AWD3CH12 = 0x2000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH12_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH12_Monitored = 0x1
	// Position of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Pos = 0xe
	// Bit mask of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Msk = 0x4000
	// Bit AWD3CH13.
	ADC_AWD3CR_AWD3CH13 = 0x4000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH13_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH13_Monitored = 0x1
	// Position of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Pos = 0xf
	// Bit mask of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Msk = 0x8000
	// Bit AWD3CH14.
	ADC_AWD3CR_AWD3CH14 = 0x8000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH14_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH14_Monitored = 0x1
	// Position of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Pos = 0x10
	// Bit mask of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Msk = 0x10000
	// Bit AWD3CH15.
	ADC_AWD3CR_AWD3CH15 = 0x10000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH15_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH15_Monitored = 0x1
	// Position of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Pos = 0x11
	// Bit mask of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Msk = 0x20000
	// Bit AWD3CH16.
	ADC_AWD3CR_AWD3CH16 = 0x20000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH16_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH16_Monitored = 0x1
	// Position of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Pos = 0x12
	// Bit mask of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Msk = 0x40000
	// Bit AWD3CH17.
	ADC_AWD3CR_AWD3CH17 = 0x40000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH17_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH17_Monitored = 0x1
	// Position of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Pos = 0x13
	// Bit mask of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Msk = 0x80000
	// Bit AWD3CH18.
	ADC_AWD3CR_AWD3CH18 = 0x80000
	// ADC analog channel-x is not monitored by AWD3
	ADC_AWD3CR_AWD3CH18_NotMonitored = 0x0
	// ADC analog channel-x is monitored by AWD3
	ADC_AWD3CR_AWD3CH18_Monitored = 0x1

	// CALFACT: ADC Calibration factor
	// Position of CALFACT field.
	ADC_CALFACT_CALFACT_Pos = 0x0
	// Bit mask of CALFACT field.
	ADC_CALFACT_CALFACT_Msk = 0x7f

	// CCR: ADC common configuration register
	// Position of PRESC field.
	ADC_CCR_PRESC_Pos = 0x12
	// Bit mask of PRESC field.
	ADC_CCR_PRESC_Msk = 0x3c0000
	// Input ADC clock not divided
	ADC_CCR_PRESC_Div1 = 0x0
	// Input ADC clock divided by 2
	ADC_CCR_PRESC_Div2 = 0x1
	// Input ADC clock divided by 4
	ADC_CCR_PRESC_Div4 = 0x2
	// Input ADC clock divided by 6
	ADC_CCR_PRESC_Div6 = 0x3
	// Input ADC clock divided by 8
	ADC_CCR_PRESC_Div8 = 0x4
	// Input ADC clock divided by 10
	ADC_CCR_PRESC_Div10 = 0x5
	// Input ADC clock divided by 12
	ADC_CCR_PRESC_Div12 = 0x6
	// Input ADC clock divided by 16
	ADC_CCR_PRESC_Div16 = 0x7
	// Input ADC clock divided by 32
	ADC_CCR_PRESC_Div32 = 0x8
	// Input ADC clock divided by 64
	ADC_CCR_PRESC_Div64 = 0x9
	// Input ADC clock divided by 128
	ADC_CCR_PRESC_Div128 = 0xa
	// Input ADC clock divided by 256
	ADC_CCR_PRESC_Div256 = 0xb
	// Position of VREFEN field.
	ADC_CCR_VREFEN_Pos = 0x16
	// Bit mask of VREFEN field.
	ADC_CCR_VREFEN_Msk = 0x400000
	// Bit VREFEN.
	ADC_CCR_VREFEN = 0x400000
	// The selected ADC channel disabled
	ADC_CCR_VREFEN_Disabled = 0x0
	// The selected ADC channel enabled
	ADC_CCR_VREFEN_Enabled = 0x1
	// Position of TSEN field.
	ADC_CCR_TSEN_Pos = 0x17
	// Bit mask of TSEN field.
	ADC_CCR_TSEN_Msk = 0x800000
	// Bit TSEN.
	ADC_CCR_TSEN = 0x800000
	// The selected ADC channel disabled
	ADC_CCR_TSEN_Disabled = 0x0
	// The selected ADC channel enabled
	ADC_CCR_TSEN_Enabled = 0x1
	// Position of VBATEN field.
	ADC_CCR_VBATEN_Pos = 0x18
	// Bit mask of VBATEN field.
	ADC_CCR_VBATEN_Msk = 0x1000000
	// Bit VBATEN.
	ADC_CCR_VBATEN = 0x1000000
	// The selected ADC channel disabled
	ADC_CCR_VBATEN_Disabled = 0x0
	// The selected ADC channel enabled
	ADC_CCR_VBATEN_Enabled = 0x1
)

// Constants for CRC: Cyclic redundancy check calculation unit
const (
	// DR: Data register
	// Position of DR field.
	CRC_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	CRC_DR_DR_Msk = 0xffffffff

	// DR8: Data register - byte sized
	// Position of DR8 field.
	CRC_DR8_DR8_Pos = 0x0
	// Bit mask of DR8 field.
	CRC_DR8_DR8_Msk = 0xff

	// DR16: Data register - half-word sized
	// Position of DR16 field.
	CRC_DR16_DR16_Pos = 0x0
	// Bit mask of DR16 field.
	CRC_DR16_DR16_Msk = 0xffff

	// IDR: Independent data register
	// Position of IDR field.
	CRC_IDR_IDR_Pos = 0x0
	// Bit mask of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff

	// CR: Control register
	// Position of REV_OUT field.
	CRC_CR_REV_OUT_Pos = 0x7
	// Bit mask of REV_OUT field.
	CRC_CR_REV_OUT_Msk = 0x80
	// Bit REV_OUT.
	CRC_CR_REV_OUT = 0x80
	// Bit order not affected
	CRC_CR_REV_OUT_Normal = 0x0
	// Bit reversed output
	CRC_CR_REV_OUT_Reversed = 0x1
	// Position of REV_IN field.
	CRC_CR_REV_IN_Pos = 0x5
	// Bit mask of REV_IN field.
	CRC_CR_REV_IN_Msk = 0x60
	// Bit order not affected
	CRC_CR_REV_IN_Normal = 0x0
	// Bit reversal done by byte
	CRC_CR_REV_IN_Byte = 0x1
	// Bit reversal done by half-word
	CRC_CR_REV_IN_HalfWord = 0x2
	// Bit reversal done by word
	CRC_CR_REV_IN_Word = 0x3
	// Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Pos = 0x3
	// Bit mask of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18
	// 32-bit polynomial
	CRC_CR_POLYSIZE_Polysize32 = 0x0
	// 16-bit polynomial
	CRC_CR_POLYSIZE_Polysize16 = 0x1
	// 8-bit polynomial
	CRC_CR_POLYSIZE_Polysize8 = 0x2
	// 7-bit polynomial
	CRC_CR_POLYSIZE_Polysize7 = 0x3
	// Position of RESET field.
	CRC_CR_RESET_Pos = 0x0
	// Bit mask of RESET field.
	CRC_CR_RESET_Msk = 0x1
	// Bit RESET.
	CRC_CR_RESET = 0x1
	// Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
	CRC_CR_RESET_Reset = 0x1

	// INIT: Initial CRC value
	// Position of INIT field.
	CRC_INIT_INIT_Pos = 0x0
	// Bit mask of INIT field.
	CRC_INIT_INIT_Msk = 0xffffffff

	// POL: polynomial
	// Position of POL field.
	CRC_POL_POL_Pos = 0x0
	// Bit mask of POL field.
	CRC_POL_POL_Msk = 0xffffffff
)

// Constants for DBG: Debug support
const (
	// IDCODE: MCU Device ID Code Register
	// Position of DEV_ID field.
	DBG_IDCODE_DEV_ID_Pos = 0x0
	// Bit mask of DEV_ID field.
	DBG_IDCODE_DEV_ID_Msk = 0xfff
	// Position of REV_ID field.
	DBG_IDCODE_REV_ID_Pos = 0x10
	// Bit mask of REV_ID field.
	DBG_IDCODE_REV_ID_Msk = 0xffff0000

	// CR: DBG configuration register
	// Position of DBG_STOP field.
	DBG_CR_DBG_STOP_Pos = 0x1
	// Bit mask of DBG_STOP field.
	DBG_CR_DBG_STOP_Msk = 0x2
	// Bit DBG_STOP.
	DBG_CR_DBG_STOP = 0x2
	// Position of DBG_STANDBY field.
	DBG_CR_DBG_STANDBY_Pos = 0x2
	// Bit mask of DBG_STANDBY field.
	DBG_CR_DBG_STANDBY_Msk = 0x4
	// Bit DBG_STANDBY.
	DBG_CR_DBG_STANDBY = 0x4

	// APB_FZ1: DBG APB freeze register 1
	// Position of DBG_TIM3_STOP field.
	DBG_APB_FZ1_DBG_TIM3_STOP_Pos = 0x1
	// Bit mask of DBG_TIM3_STOP field.
	DBG_APB_FZ1_DBG_TIM3_STOP_Msk = 0x2
	// Bit DBG_TIM3_STOP.
	DBG_APB_FZ1_DBG_TIM3_STOP = 0x2
	// Position of DBG_TIM6_STOP field.
	DBG_APB_FZ1_DBG_TIM6_STOP_Pos = 0x4
	// Bit mask of DBG_TIM6_STOP field.
	DBG_APB_FZ1_DBG_TIM6_STOP_Msk = 0x10
	// Bit DBG_TIM6_STOP.
	DBG_APB_FZ1_DBG_TIM6_STOP = 0x10
	// Position of DBG_TIM7_STOP field.
	DBG_APB_FZ1_DBG_TIM7_STOP_Pos = 0x5
	// Bit mask of DBG_TIM7_STOP field.
	DBG_APB_FZ1_DBG_TIM7_STOP_Msk = 0x20
	// Bit DBG_TIM7_STOP.
	DBG_APB_FZ1_DBG_TIM7_STOP = 0x20
	// Position of DBG_RTC_STOP field.
	DBG_APB_FZ1_DBG_RTC_STOP_Pos = 0xa
	// Bit mask of DBG_RTC_STOP field.
	DBG_APB_FZ1_DBG_RTC_STOP_Msk = 0x400
	// Bit DBG_RTC_STOP.
	DBG_APB_FZ1_DBG_RTC_STOP = 0x400
	// Position of DBG_WWDG_STOP field.
	DBG_APB_FZ1_DBG_WWDG_STOP_Pos = 0xb
	// Bit mask of DBG_WWDG_STOP field.
	DBG_APB_FZ1_DBG_WWDG_STOP_Msk = 0x800
	// Bit DBG_WWDG_STOP.
	DBG_APB_FZ1_DBG_WWDG_STOP = 0x800
	// Position of DBG_IWDG_STOP field.
	DBG_APB_FZ1_DBG_IWDG_STOP_Pos = 0xc
	// Bit mask of DBG_IWDG_STOP field.
	DBG_APB_FZ1_DBG_IWDG_STOP_Msk = 0x1000
	// Bit DBG_IWDG_STOP.
	DBG_APB_FZ1_DBG_IWDG_STOP = 0x1000
	// Position of DBG_I2C1_SMBUS_TIMEOUT field.
	DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Pos = 0x15
	// Bit mask of DBG_I2C1_SMBUS_TIMEOUT field.
	DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Msk = 0x200000
	// Bit DBG_I2C1_SMBUS_TIMEOUT.
	DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT = 0x200000
	// Position of DBG_I2C2_SMBUS_TIMEOUT field.
	DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Pos = 0x16
	// Bit mask of DBG_I2C2_SMBUS_TIMEOUT field.
	DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Msk = 0x400000
	// Bit DBG_I2C2_SMBUS_TIMEOUT.
	DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT = 0x400000

	// APB_FZ2: DBG APB freeze register 2
	// Position of DBG_TIM1_STOP field.
	DBG_APB_FZ2_DBG_TIM1_STOP_Pos = 0xb
	// Bit mask of DBG_TIM1_STOP field.
	DBG_APB_FZ2_DBG_TIM1_STOP_Msk = 0x800
	// Bit DBG_TIM1_STOP.
	DBG_APB_FZ2_DBG_TIM1_STOP = 0x800
	// Position of DBG_TIM14_STOP field.
	DBG_APB_FZ2_DBG_TIM14_STOP_Pos = 0xf
	// Bit mask of DBG_TIM14_STOP field.
	DBG_APB_FZ2_DBG_TIM14_STOP_Msk = 0x8000
	// Bit DBG_TIM14_STOP.
	DBG_APB_FZ2_DBG_TIM14_STOP = 0x8000
	// Position of DBG_TIM15_STOP field.
	DBG_APB_FZ2_DBG_TIM15_STOP_Pos = 0x10
	// Bit mask of DBG_TIM15_STOP field.
	DBG_APB_FZ2_DBG_TIM15_STOP_Msk = 0x10000
	// Bit DBG_TIM15_STOP.
	DBG_APB_FZ2_DBG_TIM15_STOP = 0x10000
	// Position of DBG_TIM16_STOP field.
	DBG_APB_FZ2_DBG_TIM16_STOP_Pos = 0x11
	// Bit mask of DBG_TIM16_STOP field.
	DBG_APB_FZ2_DBG_TIM16_STOP_Msk = 0x20000
	// Bit DBG_TIM16_STOP.
	DBG_APB_FZ2_DBG_TIM16_STOP = 0x20000
	// Position of DBG_TIM17_STOP field.
	DBG_APB_FZ2_DBG_TIM17_STOP_Pos = 0x12
	// Bit mask of DBG_TIM17_STOP field.
	DBG_APB_FZ2_DBG_TIM17_STOP_Msk = 0x40000
	// Bit DBG_TIM17_STOP.
	DBG_APB_FZ2_DBG_TIM17_STOP = 0x40000
)

// Constants for DMA1: DMA controller
const (
	// ISR: DMA interrupt status register
	// Position of GIF1 field.
	DMA_ISR_GIF1_Pos = 0x4
	// Bit mask of GIF1 field.
	DMA_ISR_GIF1_Msk = 0x10
	// Bit GIF1.
	DMA_ISR_GIF1 = 0x10
	// No transfer error, half event, complete event
	DMA_ISR_GIF1_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF1_Event = 0x1
	// Position of GIF2 field.
	DMA_ISR_GIF2_Pos = 0x8
	// Bit mask of GIF2 field.
	DMA_ISR_GIF2_Msk = 0x100
	// Bit GIF2.
	DMA_ISR_GIF2 = 0x100
	// No transfer error, half event, complete event
	DMA_ISR_GIF2_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF2_Event = 0x1
	// Position of GIF3 field.
	DMA_ISR_GIF3_Pos = 0xc
	// Bit mask of GIF3 field.
	DMA_ISR_GIF3_Msk = 0x1000
	// Bit GIF3.
	DMA_ISR_GIF3 = 0x1000
	// No transfer error, half event, complete event
	DMA_ISR_GIF3_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF3_Event = 0x1
	// Position of GIF4 field.
	DMA_ISR_GIF4_Pos = 0x10
	// Bit mask of GIF4 field.
	DMA_ISR_GIF4_Msk = 0x10000
	// Bit GIF4.
	DMA_ISR_GIF4 = 0x10000
	// No transfer error, half event, complete event
	DMA_ISR_GIF4_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF4_Event = 0x1
	// Position of GIF5 field.
	DMA_ISR_GIF5_Pos = 0x14
	// Bit mask of GIF5 field.
	DMA_ISR_GIF5_Msk = 0x100000
	// Bit GIF5.
	DMA_ISR_GIF5 = 0x100000
	// No transfer error, half event, complete event
	DMA_ISR_GIF5_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF5_Event = 0x1
	// Position of GIF6 field.
	DMA_ISR_GIF6_Pos = 0x18
	// Bit mask of GIF6 field.
	DMA_ISR_GIF6_Msk = 0x1000000
	// Bit GIF6.
	DMA_ISR_GIF6 = 0x1000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF6_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF6_Event = 0x1
	// Position of GIF7 field.
	DMA_ISR_GIF7_Pos = 0x1c
	// Bit mask of GIF7 field.
	DMA_ISR_GIF7_Msk = 0x10000000
	// Bit GIF7.
	DMA_ISR_GIF7 = 0x10000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF7_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF7_Event = 0x1
	// Position of TCIF1 field.
	DMA_ISR_TCIF1_Pos = 0x5
	// Bit mask of TCIF1 field.
	DMA_ISR_TCIF1_Msk = 0x20
	// Bit TCIF1.
	DMA_ISR_TCIF1 = 0x20
	// No transfer complete event
	DMA_ISR_TCIF1_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF1_Complete = 0x1
	// Position of TCIF2 field.
	DMA_ISR_TCIF2_Pos = 0x9
	// Bit mask of TCIF2 field.
	DMA_ISR_TCIF2_Msk = 0x200
	// Bit TCIF2.
	DMA_ISR_TCIF2 = 0x200
	// No transfer complete event
	DMA_ISR_TCIF2_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF2_Complete = 0x1
	// Position of TCIF3 field.
	DMA_ISR_TCIF3_Pos = 0xd
	// Bit mask of TCIF3 field.
	DMA_ISR_TCIF3_Msk = 0x2000
	// Bit TCIF3.
	DMA_ISR_TCIF3 = 0x2000
	// No transfer complete event
	DMA_ISR_TCIF3_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF3_Complete = 0x1
	// Position of TCIF4 field.
	DMA_ISR_TCIF4_Pos = 0x11
	// Bit mask of TCIF4 field.
	DMA_ISR_TCIF4_Msk = 0x20000
	// Bit TCIF4.
	DMA_ISR_TCIF4 = 0x20000
	// No transfer complete event
	DMA_ISR_TCIF4_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF4_Complete = 0x1
	// Position of TCIF5 field.
	DMA_ISR_TCIF5_Pos = 0x15
	// Bit mask of TCIF5 field.
	DMA_ISR_TCIF5_Msk = 0x200000
	// Bit TCIF5.
	DMA_ISR_TCIF5 = 0x200000
	// No transfer complete event
	DMA_ISR_TCIF5_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF5_Complete = 0x1
	// Position of TCIF6 field.
	DMA_ISR_TCIF6_Pos = 0x19
	// Bit mask of TCIF6 field.
	DMA_ISR_TCIF6_Msk = 0x2000000
	// Bit TCIF6.
	DMA_ISR_TCIF6 = 0x2000000
	// No transfer complete event
	DMA_ISR_TCIF6_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF6_Complete = 0x1
	// Position of TCIF7 field.
	DMA_ISR_TCIF7_Pos = 0x1d
	// Bit mask of TCIF7 field.
	DMA_ISR_TCIF7_Msk = 0x20000000
	// Bit TCIF7.
	DMA_ISR_TCIF7 = 0x20000000
	// No transfer complete event
	DMA_ISR_TCIF7_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF7_Complete = 0x1
	// Position of HTIF1 field.
	DMA_ISR_HTIF1_Pos = 0x6
	// Bit mask of HTIF1 field.
	DMA_ISR_HTIF1_Msk = 0x40
	// Bit HTIF1.
	DMA_ISR_HTIF1 = 0x40
	// No half transfer event
	DMA_ISR_HTIF1_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF1_Half = 0x1
	// Position of HTIF2 field.
	DMA_ISR_HTIF2_Pos = 0xa
	// Bit mask of HTIF2 field.
	DMA_ISR_HTIF2_Msk = 0x400
	// Bit HTIF2.
	DMA_ISR_HTIF2 = 0x400
	// No half transfer event
	DMA_ISR_HTIF2_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF2_Half = 0x1
	// Position of HTIF3 field.
	DMA_ISR_HTIF3_Pos = 0xe
	// Bit mask of HTIF3 field.
	DMA_ISR_HTIF3_Msk = 0x4000
	// Bit HTIF3.
	DMA_ISR_HTIF3 = 0x4000
	// No half transfer event
	DMA_ISR_HTIF3_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF3_Half = 0x1
	// Position of HTIF4 field.
	DMA_ISR_HTIF4_Pos = 0x12
	// Bit mask of HTIF4 field.
	DMA_ISR_HTIF4_Msk = 0x40000
	// Bit HTIF4.
	DMA_ISR_HTIF4 = 0x40000
	// No half transfer event
	DMA_ISR_HTIF4_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF4_Half = 0x1
	// Position of HTIF5 field.
	DMA_ISR_HTIF5_Pos = 0x16
	// Bit mask of HTIF5 field.
	DMA_ISR_HTIF5_Msk = 0x400000
	// Bit HTIF5.
	DMA_ISR_HTIF5 = 0x400000
	// No half transfer event
	DMA_ISR_HTIF5_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF5_Half = 0x1
	// Position of HTIF6 field.
	DMA_ISR_HTIF6_Pos = 0x1a
	// Bit mask of HTIF6 field.
	DMA_ISR_HTIF6_Msk = 0x4000000
	// Bit HTIF6.
	DMA_ISR_HTIF6 = 0x4000000
	// No half transfer event
	DMA_ISR_HTIF6_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF6_Half = 0x1
	// Position of HTIF7 field.
	DMA_ISR_HTIF7_Pos = 0x1e
	// Bit mask of HTIF7 field.
	DMA_ISR_HTIF7_Msk = 0x40000000
	// Bit HTIF7.
	DMA_ISR_HTIF7 = 0x40000000
	// No half transfer event
	DMA_ISR_HTIF7_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF7_Half = 0x1
	// Position of TEIF1 field.
	DMA_ISR_TEIF1_Pos = 0x7
	// Bit mask of TEIF1 field.
	DMA_ISR_TEIF1_Msk = 0x80
	// Bit TEIF1.
	DMA_ISR_TEIF1 = 0x80
	// No transfer error
	DMA_ISR_TEIF1_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF1_Error = 0x1
	// Position of TEIF2 field.
	DMA_ISR_TEIF2_Pos = 0xb
	// Bit mask of TEIF2 field.
	DMA_ISR_TEIF2_Msk = 0x800
	// Bit TEIF2.
	DMA_ISR_TEIF2 = 0x800
	// No transfer error
	DMA_ISR_TEIF2_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF2_Error = 0x1
	// Position of TEIF3 field.
	DMA_ISR_TEIF3_Pos = 0xf
	// Bit mask of TEIF3 field.
	DMA_ISR_TEIF3_Msk = 0x8000
	// Bit TEIF3.
	DMA_ISR_TEIF3 = 0x8000
	// No transfer error
	DMA_ISR_TEIF3_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF3_Error = 0x1
	// Position of TEIF4 field.
	DMA_ISR_TEIF4_Pos = 0x13
	// Bit mask of TEIF4 field.
	DMA_ISR_TEIF4_Msk = 0x80000
	// Bit TEIF4.
	DMA_ISR_TEIF4 = 0x80000
	// No transfer error
	DMA_ISR_TEIF4_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF4_Error = 0x1
	// Position of TEIF5 field.
	DMA_ISR_TEIF5_Pos = 0x17
	// Bit mask of TEIF5 field.
	DMA_ISR_TEIF5_Msk = 0x800000
	// Bit TEIF5.
	DMA_ISR_TEIF5 = 0x800000
	// No transfer error
	DMA_ISR_TEIF5_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF5_Error = 0x1
	// Position of TEIF6 field.
	DMA_ISR_TEIF6_Pos = 0x1b
	// Bit mask of TEIF6 field.
	DMA_ISR_TEIF6_Msk = 0x8000000
	// Bit TEIF6.
	DMA_ISR_TEIF6 = 0x8000000
	// No transfer error
	DMA_ISR_TEIF6_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF6_Error = 0x1
	// Position of TEIF7 field.
	DMA_ISR_TEIF7_Pos = 0x1f
	// Bit mask of TEIF7 field.
	DMA_ISR_TEIF7_Msk = 0x80000000
	// Bit TEIF7.
	DMA_ISR_TEIF7 = 0x80000000
	// No transfer error
	DMA_ISR_TEIF7_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF7_Error = 0x1

	// IFCR: DMA interrupt flag clear register
	// Position of CGIF1 field.
	DMA_IFCR_CGIF1_Pos = 0x4
	// Bit mask of CGIF1 field.
	DMA_IFCR_CGIF1_Msk = 0x10
	// Bit CGIF1.
	DMA_IFCR_CGIF1 = 0x10
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF1_Clear = 0x1
	// Position of CGIF2 field.
	DMA_IFCR_CGIF2_Pos = 0x8
	// Bit mask of CGIF2 field.
	DMA_IFCR_CGIF2_Msk = 0x100
	// Bit CGIF2.
	DMA_IFCR_CGIF2 = 0x100
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF2_Clear = 0x1
	// Position of CGIF3 field.
	DMA_IFCR_CGIF3_Pos = 0xc
	// Bit mask of CGIF3 field.
	DMA_IFCR_CGIF3_Msk = 0x1000
	// Bit CGIF3.
	DMA_IFCR_CGIF3 = 0x1000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF3_Clear = 0x1
	// Position of CGIF4 field.
	DMA_IFCR_CGIF4_Pos = 0x10
	// Bit mask of CGIF4 field.
	DMA_IFCR_CGIF4_Msk = 0x10000
	// Bit CGIF4.
	DMA_IFCR_CGIF4 = 0x10000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF4_Clear = 0x1
	// Position of CGIF5 field.
	DMA_IFCR_CGIF5_Pos = 0x14
	// Bit mask of CGIF5 field.
	DMA_IFCR_CGIF5_Msk = 0x100000
	// Bit CGIF5.
	DMA_IFCR_CGIF5 = 0x100000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF5_Clear = 0x1
	// Position of CGIF6 field.
	DMA_IFCR_CGIF6_Pos = 0x18
	// Bit mask of CGIF6 field.
	DMA_IFCR_CGIF6_Msk = 0x1000000
	// Bit CGIF6.
	DMA_IFCR_CGIF6 = 0x1000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF6_Clear = 0x1
	// Position of CGIF7 field.
	DMA_IFCR_CGIF7_Pos = 0x1c
	// Bit mask of CGIF7 field.
	DMA_IFCR_CGIF7_Msk = 0x10000000
	// Bit CGIF7.
	DMA_IFCR_CGIF7 = 0x10000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF7_Clear = 0x1
	// Position of CTCIF1 field.
	DMA_IFCR_CTCIF1_Pos = 0x5
	// Bit mask of CTCIF1 field.
	DMA_IFCR_CTCIF1_Msk = 0x20
	// Bit CTCIF1.
	DMA_IFCR_CTCIF1 = 0x20
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF1_Clear = 0x1
	// Position of CTCIF2 field.
	DMA_IFCR_CTCIF2_Pos = 0x9
	// Bit mask of CTCIF2 field.
	DMA_IFCR_CTCIF2_Msk = 0x200
	// Bit CTCIF2.
	DMA_IFCR_CTCIF2 = 0x200
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF2_Clear = 0x1
	// Position of CTCIF3 field.
	DMA_IFCR_CTCIF3_Pos = 0xd
	// Bit mask of CTCIF3 field.
	DMA_IFCR_CTCIF3_Msk = 0x2000
	// Bit CTCIF3.
	DMA_IFCR_CTCIF3 = 0x2000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF3_Clear = 0x1
	// Position of CTCIF4 field.
	DMA_IFCR_CTCIF4_Pos = 0x11
	// Bit mask of CTCIF4 field.
	DMA_IFCR_CTCIF4_Msk = 0x20000
	// Bit CTCIF4.
	DMA_IFCR_CTCIF4 = 0x20000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF4_Clear = 0x1
	// Position of CTCIF5 field.
	DMA_IFCR_CTCIF5_Pos = 0x15
	// Bit mask of CTCIF5 field.
	DMA_IFCR_CTCIF5_Msk = 0x200000
	// Bit CTCIF5.
	DMA_IFCR_CTCIF5 = 0x200000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF5_Clear = 0x1
	// Position of CTCIF6 field.
	DMA_IFCR_CTCIF6_Pos = 0x19
	// Bit mask of CTCIF6 field.
	DMA_IFCR_CTCIF6_Msk = 0x2000000
	// Bit CTCIF6.
	DMA_IFCR_CTCIF6 = 0x2000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF6_Clear = 0x1
	// Position of CTCIF7 field.
	DMA_IFCR_CTCIF7_Pos = 0x1d
	// Bit mask of CTCIF7 field.
	DMA_IFCR_CTCIF7_Msk = 0x20000000
	// Bit CTCIF7.
	DMA_IFCR_CTCIF7 = 0x20000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF7_Clear = 0x1
	// Position of CHTIF1 field.
	DMA_IFCR_CHTIF1_Pos = 0x6
	// Bit mask of CHTIF1 field.
	DMA_IFCR_CHTIF1_Msk = 0x40
	// Bit CHTIF1.
	DMA_IFCR_CHTIF1 = 0x40
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF1_Clear = 0x1
	// Position of CHTIF2 field.
	DMA_IFCR_CHTIF2_Pos = 0xa
	// Bit mask of CHTIF2 field.
	DMA_IFCR_CHTIF2_Msk = 0x400
	// Bit CHTIF2.
	DMA_IFCR_CHTIF2 = 0x400
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF2_Clear = 0x1
	// Position of CHTIF3 field.
	DMA_IFCR_CHTIF3_Pos = 0xe
	// Bit mask of CHTIF3 field.
	DMA_IFCR_CHTIF3_Msk = 0x4000
	// Bit CHTIF3.
	DMA_IFCR_CHTIF3 = 0x4000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF3_Clear = 0x1
	// Position of CHTIF4 field.
	DMA_IFCR_CHTIF4_Pos = 0x12
	// Bit mask of CHTIF4 field.
	DMA_IFCR_CHTIF4_Msk = 0x40000
	// Bit CHTIF4.
	DMA_IFCR_CHTIF4 = 0x40000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF4_Clear = 0x1
	// Position of CHTIF5 field.
	DMA_IFCR_CHTIF5_Pos = 0x16
	// Bit mask of CHTIF5 field.
	DMA_IFCR_CHTIF5_Msk = 0x400000
	// Bit CHTIF5.
	DMA_IFCR_CHTIF5 = 0x400000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF5_Clear = 0x1
	// Position of CHTIF6 field.
	DMA_IFCR_CHTIF6_Pos = 0x1a
	// Bit mask of CHTIF6 field.
	DMA_IFCR_CHTIF6_Msk = 0x4000000
	// Bit CHTIF6.
	DMA_IFCR_CHTIF6 = 0x4000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF6_Clear = 0x1
	// Position of CHTIF7 field.
	DMA_IFCR_CHTIF7_Pos = 0x1e
	// Bit mask of CHTIF7 field.
	DMA_IFCR_CHTIF7_Msk = 0x40000000
	// Bit CHTIF7.
	DMA_IFCR_CHTIF7 = 0x40000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF7_Clear = 0x1
	// Position of CTEIF1 field.
	DMA_IFCR_CTEIF1_Pos = 0x7
	// Bit mask of CTEIF1 field.
	DMA_IFCR_CTEIF1_Msk = 0x80
	// Bit CTEIF1.
	DMA_IFCR_CTEIF1 = 0x80
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF1_Clear = 0x1
	// Position of CTEIF2 field.
	DMA_IFCR_CTEIF2_Pos = 0xb
	// Bit mask of CTEIF2 field.
	DMA_IFCR_CTEIF2_Msk = 0x800
	// Bit CTEIF2.
	DMA_IFCR_CTEIF2 = 0x800
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF2_Clear = 0x1
	// Position of CTEIF3 field.
	DMA_IFCR_CTEIF3_Pos = 0xf
	// Bit mask of CTEIF3 field.
	DMA_IFCR_CTEIF3_Msk = 0x8000
	// Bit CTEIF3.
	DMA_IFCR_CTEIF3 = 0x8000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF3_Clear = 0x1
	// Position of CTEIF4 field.
	DMA_IFCR_CTEIF4_Pos = 0x13
	// Bit mask of CTEIF4 field.
	DMA_IFCR_CTEIF4_Msk = 0x80000
	// Bit CTEIF4.
	DMA_IFCR_CTEIF4 = 0x80000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF4_Clear = 0x1
	// Position of CTEIF5 field.
	DMA_IFCR_CTEIF5_Pos = 0x17
	// Bit mask of CTEIF5 field.
	DMA_IFCR_CTEIF5_Msk = 0x800000
	// Bit CTEIF5.
	DMA_IFCR_CTEIF5 = 0x800000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF5_Clear = 0x1
	// Position of CTEIF6 field.
	DMA_IFCR_CTEIF6_Pos = 0x1b
	// Bit mask of CTEIF6 field.
	DMA_IFCR_CTEIF6_Msk = 0x8000000
	// Bit CTEIF6.
	DMA_IFCR_CTEIF6 = 0x8000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF6_Clear = 0x1
	// Position of CTEIF7 field.
	DMA_IFCR_CTEIF7_Pos = 0x1f
	// Bit mask of CTEIF7 field.
	DMA_IFCR_CTEIF7_Msk = 0x80000000
	// Bit CTEIF7.
	DMA_IFCR_CTEIF7 = 0x80000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF7_Clear = 0x1

	// CH.CR: DMA channel 1 configuration register
	// Position of EN field.
	DMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	DMA_CH_CR_EN = 0x1
	// Channel disabled
	DMA_CH_CR_EN_Disabled = 0x0
	// Channel enabled
	DMA_CH_CR_EN_Enabled = 0x1
	// Position of TCIE field.
	DMA_CH_CR_TCIE_Pos = 0x1
	// Bit mask of TCIE field.
	DMA_CH_CR_TCIE_Msk = 0x2
	// Bit TCIE.
	DMA_CH_CR_TCIE = 0x2
	// Transfer Complete interrupt disabled
	DMA_CH_CR_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	DMA_CH_CR_TCIE_Enabled = 0x1
	// Position of HTIE field.
	DMA_CH_CR_HTIE_Pos = 0x2
	// Bit mask of HTIE field.
	DMA_CH_CR_HTIE_Msk = 0x4
	// Bit HTIE.
	DMA_CH_CR_HTIE = 0x4
	// Half Transfer interrupt disabled
	DMA_CH_CR_HTIE_Disabled = 0x0
	// Half Transfer interrupt enabled
	DMA_CH_CR_HTIE_Enabled = 0x1
	// Position of TEIE field.
	DMA_CH_CR_TEIE_Pos = 0x3
	// Bit mask of TEIE field.
	DMA_CH_CR_TEIE_Msk = 0x8
	// Bit TEIE.
	DMA_CH_CR_TEIE = 0x8
	// Transfer Error interrupt disabled
	DMA_CH_CR_TEIE_Disabled = 0x0
	// Transfer Error interrupt enabled
	DMA_CH_CR_TEIE_Enabled = 0x1
	// Position of DIR field.
	DMA_CH_CR_DIR_Pos = 0x4
	// Bit mask of DIR field.
	DMA_CH_CR_DIR_Msk = 0x10
	// Bit DIR.
	DMA_CH_CR_DIR = 0x10
	// Read from peripheral
	DMA_CH_CR_DIR_FromPeripheral = 0x0
	// Read from memory
	DMA_CH_CR_DIR_FromMemory = 0x1
	// Position of CIRC field.
	DMA_CH_CR_CIRC_Pos = 0x5
	// Bit mask of CIRC field.
	DMA_CH_CR_CIRC_Msk = 0x20
	// Bit CIRC.
	DMA_CH_CR_CIRC = 0x20
	// Circular buffer disabled
	DMA_CH_CR_CIRC_Disabled = 0x0
	// Circular buffer enabled
	DMA_CH_CR_CIRC_Enabled = 0x1
	// Position of PINC field.
	DMA_CH_CR_PINC_Pos = 0x6
	// Bit mask of PINC field.
	DMA_CH_CR_PINC_Msk = 0x40
	// Bit PINC.
	DMA_CH_CR_PINC = 0x40
	// Increment mode disabled
	DMA_CH_CR_PINC_Disabled = 0x0
	// Increment mode enabled
	DMA_CH_CR_PINC_Enabled = 0x1
	// Position of MINC field.
	DMA_CH_CR_MINC_Pos = 0x7
	// Bit mask of MINC field.
	DMA_CH_CR_MINC_Msk = 0x80
	// Bit MINC.
	DMA_CH_CR_MINC = 0x80
	// Increment mode disabled
	DMA_CH_CR_MINC_Disabled = 0x0
	// Increment mode enabled
	DMA_CH_CR_MINC_Enabled = 0x1
	// Position of PSIZE field.
	DMA_CH_CR_PSIZE_Pos = 0x8
	// Bit mask of PSIZE field.
	DMA_CH_CR_PSIZE_Msk = 0x300
	// 8-bit size
	DMA_CH_CR_PSIZE_Bits8 = 0x0
	// 16-bit size
	DMA_CH_CR_PSIZE_Bits16 = 0x1
	// 32-bit size
	DMA_CH_CR_PSIZE_Bits32 = 0x2
	// Position of MSIZE field.
	DMA_CH_CR_MSIZE_Pos = 0xa
	// Bit mask of MSIZE field.
	DMA_CH_CR_MSIZE_Msk = 0xc00
	// 8-bit size
	DMA_CH_CR_MSIZE_Bits8 = 0x0
	// 16-bit size
	DMA_CH_CR_MSIZE_Bits16 = 0x1
	// 32-bit size
	DMA_CH_CR_MSIZE_Bits32 = 0x2
	// Position of PL field.
	DMA_CH_CR_PL_Pos = 0xc
	// Bit mask of PL field.
	DMA_CH_CR_PL_Msk = 0x3000
	// Low priority
	DMA_CH_CR_PL_Low = 0x0
	// Medium priority
	DMA_CH_CR_PL_Medium = 0x1
	// High priority
	DMA_CH_CR_PL_High = 0x2
	// Very high priority
	DMA_CH_CR_PL_VeryHigh = 0x3
	// Position of MEM2MEM field.
	DMA_CH_CR_MEM2MEM_Pos = 0xe
	// Bit mask of MEM2MEM field.
	DMA_CH_CR_MEM2MEM_Msk = 0x4000
	// Bit MEM2MEM.
	DMA_CH_CR_MEM2MEM = 0x4000
	// Memory to memory mode disabled
	DMA_CH_CR_MEM2MEM_Disabled = 0x0
	// Memory to memory mode enabled
	DMA_CH_CR_MEM2MEM_Enabled = 0x1

	// CH.NDTR: DMA channel x number of data register
	// Position of NDT field.
	DMA_CH_NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA_CH_NDTR_NDT_Msk = 0xffff

	// CH.PAR: DMA channel x peripheral address register
	// Position of PA field.
	DMA_CH_PAR_PA_Pos = 0x0
	// Bit mask of PA field.
	DMA_CH_PAR_PA_Msk = 0xffffffff

	// CH.MAR: DMA channel x memory address register
	// Position of MA field.
	DMA_CH_MAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA_CH_MAR_MA_Msk = 0xffffffff
)

// Constants for DMAMUX: DMAMUX
const (
	// CCR0: DMA Multiplexer Channel %s Control register
	// Position of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Msk = 0x3f
	// Position of SOIE field.
	DMAMUX_CCR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX_CCR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX_CCR_SOIE = 0x100
	// Synchronization overrun interrupt disabled
	DMAMUX_CCR_SOIE_Disabled = 0x0
	// Synchronization overrun interrupt enabled
	DMAMUX_CCR_SOIE_Enabled = 0x1
	// Position of EGE field.
	DMAMUX_CCR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX_CCR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX_CCR_EGE = 0x200
	// Event generation disabled
	DMAMUX_CCR_EGE_Disabled = 0x0
	// Event generation enabled
	DMAMUX_CCR_EGE_Enabled = 0x1
	// Position of SE field.
	DMAMUX_CCR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX_CCR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX_CCR_SE = 0x10000
	// Synchronization disabled
	DMAMUX_CCR_SE_Disabled = 0x0
	// Synchronization enabled
	DMAMUX_CCR_SE_Enabled = 0x1
	// Position of SPOL field.
	DMAMUX_CCR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX_CCR_SPOL_Msk = 0x60000
	// No event, i.e. no synchronization nor detection
	DMAMUX_CCR_SPOL_NoEdge = 0x0
	// Rising edge
	DMAMUX_CCR_SPOL_RisingEdge = 0x1
	// Falling edge
	DMAMUX_CCR_SPOL_FallingEdge = 0x2
	// Rising and falling edges
	DMAMUX_CCR_SPOL_BothEdges = 0x3
	// Position of NBREQ field.
	DMAMUX_CCR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX_CCR_NBREQ_Msk = 0xf80000
	// Position of SYNC_ID field.
	DMAMUX_CCR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX_CCR_SYNC_ID_Msk = 0x1f000000

	// CSR: DMAMUX request line multiplexer interrupt channel status register
	// Position of SOF0 field.
	DMAMUX_CSR_SOF0_Pos = 0x1
	// Bit mask of SOF0 field.
	DMAMUX_CSR_SOF0_Msk = 0x2
	// Bit SOF0.
	DMAMUX_CSR_SOF0 = 0x2
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF0_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF0_SyncEvent = 0x1
	// Position of SOF1 field.
	DMAMUX_CSR_SOF1_Pos = 0x2
	// Bit mask of SOF1 field.
	DMAMUX_CSR_SOF1_Msk = 0x4
	// Bit SOF1.
	DMAMUX_CSR_SOF1 = 0x4
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF1_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF1_SyncEvent = 0x1
	// Position of SOF2 field.
	DMAMUX_CSR_SOF2_Pos = 0x3
	// Bit mask of SOF2 field.
	DMAMUX_CSR_SOF2_Msk = 0x8
	// Bit SOF2.
	DMAMUX_CSR_SOF2 = 0x8
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF2_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF2_SyncEvent = 0x1
	// Position of SOF3 field.
	DMAMUX_CSR_SOF3_Pos = 0x4
	// Bit mask of SOF3 field.
	DMAMUX_CSR_SOF3_Msk = 0x10
	// Bit SOF3.
	DMAMUX_CSR_SOF3 = 0x10
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF3_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF3_SyncEvent = 0x1
	// Position of SOF4 field.
	DMAMUX_CSR_SOF4_Pos = 0x5
	// Bit mask of SOF4 field.
	DMAMUX_CSR_SOF4_Msk = 0x20
	// Bit SOF4.
	DMAMUX_CSR_SOF4 = 0x20
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF4_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF4_SyncEvent = 0x1
	// Position of SOF5 field.
	DMAMUX_CSR_SOF5_Pos = 0x6
	// Bit mask of SOF5 field.
	DMAMUX_CSR_SOF5_Msk = 0x40
	// Bit SOF5.
	DMAMUX_CSR_SOF5 = 0x40
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF5_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF5_SyncEvent = 0x1
	// Position of SOF6 field.
	DMAMUX_CSR_SOF6_Pos = 0x7
	// Bit mask of SOF6 field.
	DMAMUX_CSR_SOF6_Msk = 0x80
	// Bit SOF6.
	DMAMUX_CSR_SOF6 = 0x80
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF6_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF6_SyncEvent = 0x1
	// Position of SOF7 field.
	DMAMUX_CSR_SOF7_Pos = 0x8
	// Bit mask of SOF7 field.
	DMAMUX_CSR_SOF7_Msk = 0x100
	// Bit SOF7.
	DMAMUX_CSR_SOF7 = 0x100
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF7_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF7_SyncEvent = 0x1
	// Position of SOF8 field.
	DMAMUX_CSR_SOF8_Pos = 0x9
	// Bit mask of SOF8 field.
	DMAMUX_CSR_SOF8_Msk = 0x200
	// Bit SOF8.
	DMAMUX_CSR_SOF8 = 0x200
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF8_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF8_SyncEvent = 0x1
	// Position of SOF9 field.
	DMAMUX_CSR_SOF9_Pos = 0xa
	// Bit mask of SOF9 field.
	DMAMUX_CSR_SOF9_Msk = 0x400
	// Bit SOF9.
	DMAMUX_CSR_SOF9 = 0x400
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF9_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF9_SyncEvent = 0x1
	// Position of SOF10 field.
	DMAMUX_CSR_SOF10_Pos = 0xb
	// Bit mask of SOF10 field.
	DMAMUX_CSR_SOF10_Msk = 0x800
	// Bit SOF10.
	DMAMUX_CSR_SOF10 = 0x800
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF10_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF10_SyncEvent = 0x1
	// Position of SOF11 field.
	DMAMUX_CSR_SOF11_Pos = 0xc
	// Bit mask of SOF11 field.
	DMAMUX_CSR_SOF11_Msk = 0x1000
	// Bit SOF11.
	DMAMUX_CSR_SOF11 = 0x1000
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF11_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF11_SyncEvent = 0x1

	// CFR: DMAMUX request line multiplexer interrupt clear flag register
	// Position of CSOF0 field.
	DMAMUX_CFR_CSOF0_Pos = 0x1
	// Bit mask of CSOF0 field.
	DMAMUX_CFR_CSOF0_Msk = 0x2
	// Bit CSOF0.
	DMAMUX_CFR_CSOF0 = 0x2
	// Clear synchronization flag
	DMAMUX_CFR_CSOF0_Clear = 0x1
	// Position of CSOF1 field.
	DMAMUX_CFR_CSOF1_Pos = 0x2
	// Bit mask of CSOF1 field.
	DMAMUX_CFR_CSOF1_Msk = 0x4
	// Bit CSOF1.
	DMAMUX_CFR_CSOF1 = 0x4
	// Clear synchronization flag
	DMAMUX_CFR_CSOF1_Clear = 0x1
	// Position of CSOF2 field.
	DMAMUX_CFR_CSOF2_Pos = 0x3
	// Bit mask of CSOF2 field.
	DMAMUX_CFR_CSOF2_Msk = 0x8
	// Bit CSOF2.
	DMAMUX_CFR_CSOF2 = 0x8
	// Clear synchronization flag
	DMAMUX_CFR_CSOF2_Clear = 0x1
	// Position of CSOF3 field.
	DMAMUX_CFR_CSOF3_Pos = 0x4
	// Bit mask of CSOF3 field.
	DMAMUX_CFR_CSOF3_Msk = 0x10
	// Bit CSOF3.
	DMAMUX_CFR_CSOF3 = 0x10
	// Clear synchronization flag
	DMAMUX_CFR_CSOF3_Clear = 0x1
	// Position of CSOF4 field.
	DMAMUX_CFR_CSOF4_Pos = 0x5
	// Bit mask of CSOF4 field.
	DMAMUX_CFR_CSOF4_Msk = 0x20
	// Bit CSOF4.
	DMAMUX_CFR_CSOF4 = 0x20
	// Clear synchronization flag
	DMAMUX_CFR_CSOF4_Clear = 0x1
	// Position of CSOF5 field.
	DMAMUX_CFR_CSOF5_Pos = 0x6
	// Bit mask of CSOF5 field.
	DMAMUX_CFR_CSOF5_Msk = 0x40
	// Bit CSOF5.
	DMAMUX_CFR_CSOF5 = 0x40
	// Clear synchronization flag
	DMAMUX_CFR_CSOF5_Clear = 0x1
	// Position of CSOF6 field.
	DMAMUX_CFR_CSOF6_Pos = 0x7
	// Bit mask of CSOF6 field.
	DMAMUX_CFR_CSOF6_Msk = 0x80
	// Bit CSOF6.
	DMAMUX_CFR_CSOF6 = 0x80
	// Clear synchronization flag
	DMAMUX_CFR_CSOF6_Clear = 0x1
	// Position of CSOF7 field.
	DMAMUX_CFR_CSOF7_Pos = 0x8
	// Bit mask of CSOF7 field.
	DMAMUX_CFR_CSOF7_Msk = 0x100
	// Bit CSOF7.
	DMAMUX_CFR_CSOF7 = 0x100
	// Clear synchronization flag
	DMAMUX_CFR_CSOF7_Clear = 0x1
	// Position of CSOF8 field.
	DMAMUX_CFR_CSOF8_Pos = 0x9
	// Bit mask of CSOF8 field.
	DMAMUX_CFR_CSOF8_Msk = 0x200
	// Bit CSOF8.
	DMAMUX_CFR_CSOF8 = 0x200
	// Clear synchronization flag
	DMAMUX_CFR_CSOF8_Clear = 0x1
	// Position of CSOF9 field.
	DMAMUX_CFR_CSOF9_Pos = 0xa
	// Bit mask of CSOF9 field.
	DMAMUX_CFR_CSOF9_Msk = 0x400
	// Bit CSOF9.
	DMAMUX_CFR_CSOF9 = 0x400
	// Clear synchronization flag
	DMAMUX_CFR_CSOF9_Clear = 0x1
	// Position of CSOF10 field.
	DMAMUX_CFR_CSOF10_Pos = 0xb
	// Bit mask of CSOF10 field.
	DMAMUX_CFR_CSOF10_Msk = 0x800
	// Bit CSOF10.
	DMAMUX_CFR_CSOF10 = 0x800
	// Clear synchronization flag
	DMAMUX_CFR_CSOF10_Clear = 0x1
	// Position of CSOF11 field.
	DMAMUX_CFR_CSOF11_Pos = 0xc
	// Bit mask of CSOF11 field.
	DMAMUX_CFR_CSOF11_Msk = 0x1000
	// Bit CSOF11.
	DMAMUX_CFR_CSOF11 = 0x1000
	// Clear synchronization flag
	DMAMUX_CFR_CSOF11_Clear = 0x1

	// RGCR0: DMAMUX request generator channel x configuration register
	// Position of SIG_ID field.
	DMAMUX_RGCR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX_RGCR_SIG_ID_Msk = 0x1f
	// Position of OIE field.
	DMAMUX_RGCR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX_RGCR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX_RGCR_OIE = 0x100
	// Trigger overrun interrupt disabled
	DMAMUX_RGCR_OIE_Disabled = 0x0
	// Trigger overrun interrupt enabled
	DMAMUX_RGCR_OIE_Enabled = 0x1
	// Position of GE field.
	DMAMUX_RGCR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX_RGCR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX_RGCR_GE = 0x10000
	// DMA request generation disabled
	DMAMUX_RGCR_GE_Disabled = 0x0
	// DMA request enabled
	DMAMUX_RGCR_GE_Enabled = 0x1
	// Position of GPOL field.
	DMAMUX_RGCR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX_RGCR_GPOL_Msk = 0x60000
	// No event, i.e. no detection nor generation
	DMAMUX_RGCR_GPOL_NoEdge = 0x0
	// Rising edge
	DMAMUX_RGCR_GPOL_RisingEdge = 0x1
	// Falling edge
	DMAMUX_RGCR_GPOL_FallingEdge = 0x2
	// Rising and falling edges
	DMAMUX_RGCR_GPOL_BothEdges = 0x3
	// Position of GNBREQ field.
	DMAMUX_RGCR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX_RGCR_GNBREQ_Msk = 0xf80000

	// RGSR: DMAMUX request generator interrupt status register
	// Position of OF0 field.
	DMAMUX_RGSR_OF0_Pos = 0x1
	// Bit mask of OF0 field.
	DMAMUX_RGSR_OF0_Msk = 0x2
	// Bit OF0.
	DMAMUX_RGSR_OF0 = 0x2
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF0_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF0_Trigger = 0x1
	// Position of OF1 field.
	DMAMUX_RGSR_OF1_Pos = 0x2
	// Bit mask of OF1 field.
	DMAMUX_RGSR_OF1_Msk = 0x4
	// Bit OF1.
	DMAMUX_RGSR_OF1 = 0x4
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF1_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF1_Trigger = 0x1
	// Position of OF2 field.
	DMAMUX_RGSR_OF2_Pos = 0x3
	// Bit mask of OF2 field.
	DMAMUX_RGSR_OF2_Msk = 0x8
	// Bit OF2.
	DMAMUX_RGSR_OF2 = 0x8
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF2_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF2_Trigger = 0x1
	// Position of OF3 field.
	DMAMUX_RGSR_OF3_Pos = 0x4
	// Bit mask of OF3 field.
	DMAMUX_RGSR_OF3_Msk = 0x10
	// Bit OF3.
	DMAMUX_RGSR_OF3 = 0x10
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF3_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF3_Trigger = 0x1

	// RGCFR: DMAMUX request generator interrupt clear flag register
	// Position of COF0 field.
	DMAMUX_RGCFR_COF0_Pos = 0x1
	// Bit mask of COF0 field.
	DMAMUX_RGCFR_COF0_Msk = 0x2
	// Bit COF0.
	DMAMUX_RGCFR_COF0 = 0x2
	// Clear overrun flag
	DMAMUX_RGCFR_COF0_Clear = 0x1
	// Position of COF1 field.
	DMAMUX_RGCFR_COF1_Pos = 0x2
	// Bit mask of COF1 field.
	DMAMUX_RGCFR_COF1_Msk = 0x4
	// Bit COF1.
	DMAMUX_RGCFR_COF1 = 0x4
	// Clear overrun flag
	DMAMUX_RGCFR_COF1_Clear = 0x1
	// Position of COF2 field.
	DMAMUX_RGCFR_COF2_Pos = 0x3
	// Bit mask of COF2 field.
	DMAMUX_RGCFR_COF2_Msk = 0x8
	// Bit COF2.
	DMAMUX_RGCFR_COF2 = 0x8
	// Clear overrun flag
	DMAMUX_RGCFR_COF2_Clear = 0x1
	// Position of COF3 field.
	DMAMUX_RGCFR_COF3_Pos = 0x4
	// Bit mask of COF3 field.
	DMAMUX_RGCFR_COF3_Msk = 0x10
	// Bit COF3.
	DMAMUX_RGCFR_COF3 = 0x10
	// Clear overrun flag
	DMAMUX_RGCFR_COF3_Clear = 0x1
)

// Constants for EXTI: External interrupt/event controller
const (
	// RTSR1: EXTI rising trigger selection register
	// Position of RT0 field.
	EXTI_RTSR1_RT0_Pos = 0x0
	// Bit mask of RT0 field.
	EXTI_RTSR1_RT0_Msk = 0x1
	// Bit RT0.
	EXTI_RTSR1_RT0 = 0x1
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT0_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT0_Enabled = 0x1
	// Position of RT1 field.
	EXTI_RTSR1_RT1_Pos = 0x1
	// Bit mask of RT1 field.
	EXTI_RTSR1_RT1_Msk = 0x2
	// Bit RT1.
	EXTI_RTSR1_RT1 = 0x2
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT1_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT1_Enabled = 0x1
	// Position of RT2 field.
	EXTI_RTSR1_RT2_Pos = 0x2
	// Bit mask of RT2 field.
	EXTI_RTSR1_RT2_Msk = 0x4
	// Bit RT2.
	EXTI_RTSR1_RT2 = 0x4
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT2_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT2_Enabled = 0x1
	// Position of RT3 field.
	EXTI_RTSR1_RT3_Pos = 0x3
	// Bit mask of RT3 field.
	EXTI_RTSR1_RT3_Msk = 0x8
	// Bit RT3.
	EXTI_RTSR1_RT3 = 0x8
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT3_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT3_Enabled = 0x1
	// Position of RT4 field.
	EXTI_RTSR1_RT4_Pos = 0x4
	// Bit mask of RT4 field.
	EXTI_RTSR1_RT4_Msk = 0x10
	// Bit RT4.
	EXTI_RTSR1_RT4 = 0x10
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT4_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT4_Enabled = 0x1
	// Position of RT5 field.
	EXTI_RTSR1_RT5_Pos = 0x5
	// Bit mask of RT5 field.
	EXTI_RTSR1_RT5_Msk = 0x20
	// Bit RT5.
	EXTI_RTSR1_RT5 = 0x20
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT5_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT5_Enabled = 0x1
	// Position of RT6 field.
	EXTI_RTSR1_RT6_Pos = 0x6
	// Bit mask of RT6 field.
	EXTI_RTSR1_RT6_Msk = 0x40
	// Bit RT6.
	EXTI_RTSR1_RT6 = 0x40
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT6_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT6_Enabled = 0x1
	// Position of RT7 field.
	EXTI_RTSR1_RT7_Pos = 0x7
	// Bit mask of RT7 field.
	EXTI_RTSR1_RT7_Msk = 0x80
	// Bit RT7.
	EXTI_RTSR1_RT7 = 0x80
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT7_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT7_Enabled = 0x1
	// Position of RT8 field.
	EXTI_RTSR1_RT8_Pos = 0x8
	// Bit mask of RT8 field.
	EXTI_RTSR1_RT8_Msk = 0x100
	// Bit RT8.
	EXTI_RTSR1_RT8 = 0x100
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT8_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT8_Enabled = 0x1
	// Position of RT9 field.
	EXTI_RTSR1_RT9_Pos = 0x9
	// Bit mask of RT9 field.
	EXTI_RTSR1_RT9_Msk = 0x200
	// Bit RT9.
	EXTI_RTSR1_RT9 = 0x200
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT9_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT9_Enabled = 0x1
	// Position of RT10 field.
	EXTI_RTSR1_RT10_Pos = 0xa
	// Bit mask of RT10 field.
	EXTI_RTSR1_RT10_Msk = 0x400
	// Bit RT10.
	EXTI_RTSR1_RT10 = 0x400
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT10_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT10_Enabled = 0x1
	// Position of RT11 field.
	EXTI_RTSR1_RT11_Pos = 0xb
	// Bit mask of RT11 field.
	EXTI_RTSR1_RT11_Msk = 0x800
	// Bit RT11.
	EXTI_RTSR1_RT11 = 0x800
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT11_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT11_Enabled = 0x1
	// Position of RT12 field.
	EXTI_RTSR1_RT12_Pos = 0xc
	// Bit mask of RT12 field.
	EXTI_RTSR1_RT12_Msk = 0x1000
	// Bit RT12.
	EXTI_RTSR1_RT12 = 0x1000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT12_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT12_Enabled = 0x1
	// Position of RT13 field.
	EXTI_RTSR1_RT13_Pos = 0xd
	// Bit mask of RT13 field.
	EXTI_RTSR1_RT13_Msk = 0x2000
	// Bit RT13.
	EXTI_RTSR1_RT13 = 0x2000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT13_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT13_Enabled = 0x1
	// Position of RT14 field.
	EXTI_RTSR1_RT14_Pos = 0xe
	// Bit mask of RT14 field.
	EXTI_RTSR1_RT14_Msk = 0x4000
	// Bit RT14.
	EXTI_RTSR1_RT14 = 0x4000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT14_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT14_Enabled = 0x1
	// Position of RT15 field.
	EXTI_RTSR1_RT15_Pos = 0xf
	// Bit mask of RT15 field.
	EXTI_RTSR1_RT15_Msk = 0x8000
	// Bit RT15.
	EXTI_RTSR1_RT15 = 0x8000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT15_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT15_Enabled = 0x1

	// FTSR1: EXTI falling trigger selection register
	// Position of FT0 field.
	EXTI_FTSR1_FT0_Pos = 0x0
	// Bit mask of FT0 field.
	EXTI_FTSR1_FT0_Msk = 0x1
	// Bit FT0.
	EXTI_FTSR1_FT0 = 0x1
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT0_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT0_Enabled = 0x1
	// Position of FT1 field.
	EXTI_FTSR1_FT1_Pos = 0x1
	// Bit mask of FT1 field.
	EXTI_FTSR1_FT1_Msk = 0x2
	// Bit FT1.
	EXTI_FTSR1_FT1 = 0x2
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT1_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT1_Enabled = 0x1
	// Position of FT2 field.
	EXTI_FTSR1_FT2_Pos = 0x2
	// Bit mask of FT2 field.
	EXTI_FTSR1_FT2_Msk = 0x4
	// Bit FT2.
	EXTI_FTSR1_FT2 = 0x4
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT2_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT2_Enabled = 0x1
	// Position of FT3 field.
	EXTI_FTSR1_FT3_Pos = 0x3
	// Bit mask of FT3 field.
	EXTI_FTSR1_FT3_Msk = 0x8
	// Bit FT3.
	EXTI_FTSR1_FT3 = 0x8
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT3_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT3_Enabled = 0x1
	// Position of FT4 field.
	EXTI_FTSR1_FT4_Pos = 0x4
	// Bit mask of FT4 field.
	EXTI_FTSR1_FT4_Msk = 0x10
	// Bit FT4.
	EXTI_FTSR1_FT4 = 0x10
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT4_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT4_Enabled = 0x1
	// Position of FT5 field.
	EXTI_FTSR1_FT5_Pos = 0x5
	// Bit mask of FT5 field.
	EXTI_FTSR1_FT5_Msk = 0x20
	// Bit FT5.
	EXTI_FTSR1_FT5 = 0x20
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT5_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT5_Enabled = 0x1
	// Position of FT6 field.
	EXTI_FTSR1_FT6_Pos = 0x6
	// Bit mask of FT6 field.
	EXTI_FTSR1_FT6_Msk = 0x40
	// Bit FT6.
	EXTI_FTSR1_FT6 = 0x40
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT6_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT6_Enabled = 0x1
	// Position of FT7 field.
	EXTI_FTSR1_FT7_Pos = 0x7
	// Bit mask of FT7 field.
	EXTI_FTSR1_FT7_Msk = 0x80
	// Bit FT7.
	EXTI_FTSR1_FT7 = 0x80
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT7_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT7_Enabled = 0x1
	// Position of FT8 field.
	EXTI_FTSR1_FT8_Pos = 0x8
	// Bit mask of FT8 field.
	EXTI_FTSR1_FT8_Msk = 0x100
	// Bit FT8.
	EXTI_FTSR1_FT8 = 0x100
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT8_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT8_Enabled = 0x1
	// Position of FT9 field.
	EXTI_FTSR1_FT9_Pos = 0x9
	// Bit mask of FT9 field.
	EXTI_FTSR1_FT9_Msk = 0x200
	// Bit FT9.
	EXTI_FTSR1_FT9 = 0x200
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT9_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT9_Enabled = 0x1
	// Position of FT10 field.
	EXTI_FTSR1_FT10_Pos = 0xa
	// Bit mask of FT10 field.
	EXTI_FTSR1_FT10_Msk = 0x400
	// Bit FT10.
	EXTI_FTSR1_FT10 = 0x400
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT10_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT10_Enabled = 0x1
	// Position of FT11 field.
	EXTI_FTSR1_FT11_Pos = 0xb
	// Bit mask of FT11 field.
	EXTI_FTSR1_FT11_Msk = 0x800
	// Bit FT11.
	EXTI_FTSR1_FT11 = 0x800
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT11_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT11_Enabled = 0x1
	// Position of FT12 field.
	EXTI_FTSR1_FT12_Pos = 0xc
	// Bit mask of FT12 field.
	EXTI_FTSR1_FT12_Msk = 0x1000
	// Bit FT12.
	EXTI_FTSR1_FT12 = 0x1000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT12_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT12_Enabled = 0x1
	// Position of FT13 field.
	EXTI_FTSR1_FT13_Pos = 0xd
	// Bit mask of FT13 field.
	EXTI_FTSR1_FT13_Msk = 0x2000
	// Bit FT13.
	EXTI_FTSR1_FT13 = 0x2000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT13_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT13_Enabled = 0x1
	// Position of FT14 field.
	EXTI_FTSR1_FT14_Pos = 0xe
	// Bit mask of FT14 field.
	EXTI_FTSR1_FT14_Msk = 0x4000
	// Bit FT14.
	EXTI_FTSR1_FT14 = 0x4000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT14_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT14_Enabled = 0x1
	// Position of FT15 field.
	EXTI_FTSR1_FT15_Pos = 0xf
	// Bit mask of FT15 field.
	EXTI_FTSR1_FT15_Msk = 0x8000
	// Bit FT15.
	EXTI_FTSR1_FT15 = 0x8000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT15_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT15_Enabled = 0x1

	// SWIER1: EXTI software interrupt event register
	// Position of SWI0 field.
	EXTI_SWIER1_SWI0_Pos = 0x0
	// Bit mask of SWI0 field.
	EXTI_SWIER1_SWI0_Msk = 0x1
	// Bit SWI0.
	EXTI_SWIER1_SWI0 = 0x1
	// Generates an interrupt request
	EXTI_SWIER1_SWI0_Pend = 0x1
	// Position of SWI1 field.
	EXTI_SWIER1_SWI1_Pos = 0x1
	// Bit mask of SWI1 field.
	EXTI_SWIER1_SWI1_Msk = 0x2
	// Bit SWI1.
	EXTI_SWIER1_SWI1 = 0x2
	// Generates an interrupt request
	EXTI_SWIER1_SWI1_Pend = 0x1
	// Position of SWI2 field.
	EXTI_SWIER1_SWI2_Pos = 0x2
	// Bit mask of SWI2 field.
	EXTI_SWIER1_SWI2_Msk = 0x4
	// Bit SWI2.
	EXTI_SWIER1_SWI2 = 0x4
	// Generates an interrupt request
	EXTI_SWIER1_SWI2_Pend = 0x1
	// Position of SWI3 field.
	EXTI_SWIER1_SWI3_Pos = 0x3
	// Bit mask of SWI3 field.
	EXTI_SWIER1_SWI3_Msk = 0x8
	// Bit SWI3.
	EXTI_SWIER1_SWI3 = 0x8
	// Generates an interrupt request
	EXTI_SWIER1_SWI3_Pend = 0x1
	// Position of SWI4 field.
	EXTI_SWIER1_SWI4_Pos = 0x4
	// Bit mask of SWI4 field.
	EXTI_SWIER1_SWI4_Msk = 0x10
	// Bit SWI4.
	EXTI_SWIER1_SWI4 = 0x10
	// Generates an interrupt request
	EXTI_SWIER1_SWI4_Pend = 0x1
	// Position of SWI5 field.
	EXTI_SWIER1_SWI5_Pos = 0x5
	// Bit mask of SWI5 field.
	EXTI_SWIER1_SWI5_Msk = 0x20
	// Bit SWI5.
	EXTI_SWIER1_SWI5 = 0x20
	// Generates an interrupt request
	EXTI_SWIER1_SWI5_Pend = 0x1
	// Position of SWI6 field.
	EXTI_SWIER1_SWI6_Pos = 0x6
	// Bit mask of SWI6 field.
	EXTI_SWIER1_SWI6_Msk = 0x40
	// Bit SWI6.
	EXTI_SWIER1_SWI6 = 0x40
	// Generates an interrupt request
	EXTI_SWIER1_SWI6_Pend = 0x1
	// Position of SWI7 field.
	EXTI_SWIER1_SWI7_Pos = 0x7
	// Bit mask of SWI7 field.
	EXTI_SWIER1_SWI7_Msk = 0x80
	// Bit SWI7.
	EXTI_SWIER1_SWI7 = 0x80
	// Generates an interrupt request
	EXTI_SWIER1_SWI7_Pend = 0x1
	// Position of SWI8 field.
	EXTI_SWIER1_SWI8_Pos = 0x8
	// Bit mask of SWI8 field.
	EXTI_SWIER1_SWI8_Msk = 0x100
	// Bit SWI8.
	EXTI_SWIER1_SWI8 = 0x100
	// Generates an interrupt request
	EXTI_SWIER1_SWI8_Pend = 0x1
	// Position of SWI9 field.
	EXTI_SWIER1_SWI9_Pos = 0x9
	// Bit mask of SWI9 field.
	EXTI_SWIER1_SWI9_Msk = 0x200
	// Bit SWI9.
	EXTI_SWIER1_SWI9 = 0x200
	// Generates an interrupt request
	EXTI_SWIER1_SWI9_Pend = 0x1
	// Position of SWI10 field.
	EXTI_SWIER1_SWI10_Pos = 0xa
	// Bit mask of SWI10 field.
	EXTI_SWIER1_SWI10_Msk = 0x400
	// Bit SWI10.
	EXTI_SWIER1_SWI10 = 0x400
	// Generates an interrupt request
	EXTI_SWIER1_SWI10_Pend = 0x1
	// Position of SWI11 field.
	EXTI_SWIER1_SWI11_Pos = 0xb
	// Bit mask of SWI11 field.
	EXTI_SWIER1_SWI11_Msk = 0x800
	// Bit SWI11.
	EXTI_SWIER1_SWI11 = 0x800
	// Generates an interrupt request
	EXTI_SWIER1_SWI11_Pend = 0x1
	// Position of SWI12 field.
	EXTI_SWIER1_SWI12_Pos = 0xc
	// Bit mask of SWI12 field.
	EXTI_SWIER1_SWI12_Msk = 0x1000
	// Bit SWI12.
	EXTI_SWIER1_SWI12 = 0x1000
	// Generates an interrupt request
	EXTI_SWIER1_SWI12_Pend = 0x1
	// Position of SWI13 field.
	EXTI_SWIER1_SWI13_Pos = 0xd
	// Bit mask of SWI13 field.
	EXTI_SWIER1_SWI13_Msk = 0x2000
	// Bit SWI13.
	EXTI_SWIER1_SWI13 = 0x2000
	// Generates an interrupt request
	EXTI_SWIER1_SWI13_Pend = 0x1
	// Position of SWI14 field.
	EXTI_SWIER1_SWI14_Pos = 0xe
	// Bit mask of SWI14 field.
	EXTI_SWIER1_SWI14_Msk = 0x4000
	// Bit SWI14.
	EXTI_SWIER1_SWI14 = 0x4000
	// Generates an interrupt request
	EXTI_SWIER1_SWI14_Pend = 0x1
	// Position of SWI15 field.
	EXTI_SWIER1_SWI15_Pos = 0xf
	// Bit mask of SWI15 field.
	EXTI_SWIER1_SWI15_Msk = 0x8000
	// Bit SWI15.
	EXTI_SWIER1_SWI15 = 0x8000
	// Generates an interrupt request
	EXTI_SWIER1_SWI15_Pend = 0x1

	// RPR1: EXTI rising edge pending register
	// Position of RPIF0 field.
	EXTI_RPR1_RPIF0_Pos = 0x0
	// Bit mask of RPIF0 field.
	EXTI_RPR1_RPIF0_Msk = 0x1
	// Bit RPIF0.
	EXTI_RPR1_RPIF0 = 0x1
	// No trigger request occurred
	EXTI_RPR1_RPIF0_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF0_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF0_Clear = 0x1
	// Position of RPIF1 field.
	EXTI_RPR1_RPIF1_Pos = 0x1
	// Bit mask of RPIF1 field.
	EXTI_RPR1_RPIF1_Msk = 0x2
	// Bit RPIF1.
	EXTI_RPR1_RPIF1 = 0x2
	// No trigger request occurred
	EXTI_RPR1_RPIF1_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF1_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF1_Clear = 0x1
	// Position of RPIF2 field.
	EXTI_RPR1_RPIF2_Pos = 0x2
	// Bit mask of RPIF2 field.
	EXTI_RPR1_RPIF2_Msk = 0x4
	// Bit RPIF2.
	EXTI_RPR1_RPIF2 = 0x4
	// No trigger request occurred
	EXTI_RPR1_RPIF2_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF2_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF2_Clear = 0x1
	// Position of RPIF3 field.
	EXTI_RPR1_RPIF3_Pos = 0x3
	// Bit mask of RPIF3 field.
	EXTI_RPR1_RPIF3_Msk = 0x8
	// Bit RPIF3.
	EXTI_RPR1_RPIF3 = 0x8
	// No trigger request occurred
	EXTI_RPR1_RPIF3_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF3_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF3_Clear = 0x1
	// Position of RPIF4 field.
	EXTI_RPR1_RPIF4_Pos = 0x4
	// Bit mask of RPIF4 field.
	EXTI_RPR1_RPIF4_Msk = 0x10
	// Bit RPIF4.
	EXTI_RPR1_RPIF4 = 0x10
	// No trigger request occurred
	EXTI_RPR1_RPIF4_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF4_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF4_Clear = 0x1
	// Position of RPIF5 field.
	EXTI_RPR1_RPIF5_Pos = 0x5
	// Bit mask of RPIF5 field.
	EXTI_RPR1_RPIF5_Msk = 0x20
	// Bit RPIF5.
	EXTI_RPR1_RPIF5 = 0x20
	// No trigger request occurred
	EXTI_RPR1_RPIF5_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF5_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF5_Clear = 0x1
	// Position of RPIF6 field.
	EXTI_RPR1_RPIF6_Pos = 0x6
	// Bit mask of RPIF6 field.
	EXTI_RPR1_RPIF6_Msk = 0x40
	// Bit RPIF6.
	EXTI_RPR1_RPIF6 = 0x40
	// No trigger request occurred
	EXTI_RPR1_RPIF6_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF6_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF6_Clear = 0x1
	// Position of RPIF7 field.
	EXTI_RPR1_RPIF7_Pos = 0x7
	// Bit mask of RPIF7 field.
	EXTI_RPR1_RPIF7_Msk = 0x80
	// Bit RPIF7.
	EXTI_RPR1_RPIF7 = 0x80
	// No trigger request occurred
	EXTI_RPR1_RPIF7_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF7_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF7_Clear = 0x1
	// Position of RPIF8 field.
	EXTI_RPR1_RPIF8_Pos = 0x8
	// Bit mask of RPIF8 field.
	EXTI_RPR1_RPIF8_Msk = 0x100
	// Bit RPIF8.
	EXTI_RPR1_RPIF8 = 0x100
	// No trigger request occurred
	EXTI_RPR1_RPIF8_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF8_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF8_Clear = 0x1
	// Position of RPIF9 field.
	EXTI_RPR1_RPIF9_Pos = 0x9
	// Bit mask of RPIF9 field.
	EXTI_RPR1_RPIF9_Msk = 0x200
	// Bit RPIF9.
	EXTI_RPR1_RPIF9 = 0x200
	// No trigger request occurred
	EXTI_RPR1_RPIF9_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF9_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF9_Clear = 0x1
	// Position of RPIF10 field.
	EXTI_RPR1_RPIF10_Pos = 0xa
	// Bit mask of RPIF10 field.
	EXTI_RPR1_RPIF10_Msk = 0x400
	// Bit RPIF10.
	EXTI_RPR1_RPIF10 = 0x400
	// No trigger request occurred
	EXTI_RPR1_RPIF10_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF10_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF10_Clear = 0x1
	// Position of RPIF11 field.
	EXTI_RPR1_RPIF11_Pos = 0xb
	// Bit mask of RPIF11 field.
	EXTI_RPR1_RPIF11_Msk = 0x800
	// Bit RPIF11.
	EXTI_RPR1_RPIF11 = 0x800
	// No trigger request occurred
	EXTI_RPR1_RPIF11_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF11_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF11_Clear = 0x1
	// Position of RPIF12 field.
	EXTI_RPR1_RPIF12_Pos = 0xc
	// Bit mask of RPIF12 field.
	EXTI_RPR1_RPIF12_Msk = 0x1000
	// Bit RPIF12.
	EXTI_RPR1_RPIF12 = 0x1000
	// No trigger request occurred
	EXTI_RPR1_RPIF12_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF12_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF12_Clear = 0x1
	// Position of RPIF13 field.
	EXTI_RPR1_RPIF13_Pos = 0xd
	// Bit mask of RPIF13 field.
	EXTI_RPR1_RPIF13_Msk = 0x2000
	// Bit RPIF13.
	EXTI_RPR1_RPIF13 = 0x2000
	// No trigger request occurred
	EXTI_RPR1_RPIF13_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF13_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF13_Clear = 0x1
	// Position of RPIF14 field.
	EXTI_RPR1_RPIF14_Pos = 0xe
	// Bit mask of RPIF14 field.
	EXTI_RPR1_RPIF14_Msk = 0x4000
	// Bit RPIF14.
	EXTI_RPR1_RPIF14 = 0x4000
	// No trigger request occurred
	EXTI_RPR1_RPIF14_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF14_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF14_Clear = 0x1
	// Position of RPIF15 field.
	EXTI_RPR1_RPIF15_Pos = 0xf
	// Bit mask of RPIF15 field.
	EXTI_RPR1_RPIF15_Msk = 0x8000
	// Bit RPIF15.
	EXTI_RPR1_RPIF15 = 0x8000
	// No trigger request occurred
	EXTI_RPR1_RPIF15_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF15_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF15_Clear = 0x1

	// FPR1: EXTI falling edge pending register
	// Position of FPIF0 field.
	EXTI_FPR1_FPIF0_Pos = 0x0
	// Bit mask of FPIF0 field.
	EXTI_FPR1_FPIF0_Msk = 0x1
	// Bit FPIF0.
	EXTI_FPR1_FPIF0 = 0x1
	// No trigger request occurred
	EXTI_FPR1_FPIF0_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF0_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF0_Clear = 0x1
	// Position of FPIF1 field.
	EXTI_FPR1_FPIF1_Pos = 0x1
	// Bit mask of FPIF1 field.
	EXTI_FPR1_FPIF1_Msk = 0x2
	// Bit FPIF1.
	EXTI_FPR1_FPIF1 = 0x2
	// No trigger request occurred
	EXTI_FPR1_FPIF1_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF1_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF1_Clear = 0x1
	// Position of FPIF2 field.
	EXTI_FPR1_FPIF2_Pos = 0x2
	// Bit mask of FPIF2 field.
	EXTI_FPR1_FPIF2_Msk = 0x4
	// Bit FPIF2.
	EXTI_FPR1_FPIF2 = 0x4
	// No trigger request occurred
	EXTI_FPR1_FPIF2_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF2_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF2_Clear = 0x1
	// Position of FPIF3 field.
	EXTI_FPR1_FPIF3_Pos = 0x3
	// Bit mask of FPIF3 field.
	EXTI_FPR1_FPIF3_Msk = 0x8
	// Bit FPIF3.
	EXTI_FPR1_FPIF3 = 0x8
	// No trigger request occurred
	EXTI_FPR1_FPIF3_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF3_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF3_Clear = 0x1
	// Position of FPIF4 field.
	EXTI_FPR1_FPIF4_Pos = 0x4
	// Bit mask of FPIF4 field.
	EXTI_FPR1_FPIF4_Msk = 0x10
	// Bit FPIF4.
	EXTI_FPR1_FPIF4 = 0x10
	// No trigger request occurred
	EXTI_FPR1_FPIF4_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF4_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF4_Clear = 0x1
	// Position of FPIF5 field.
	EXTI_FPR1_FPIF5_Pos = 0x5
	// Bit mask of FPIF5 field.
	EXTI_FPR1_FPIF5_Msk = 0x20
	// Bit FPIF5.
	EXTI_FPR1_FPIF5 = 0x20
	// No trigger request occurred
	EXTI_FPR1_FPIF5_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF5_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF5_Clear = 0x1
	// Position of FPIF6 field.
	EXTI_FPR1_FPIF6_Pos = 0x6
	// Bit mask of FPIF6 field.
	EXTI_FPR1_FPIF6_Msk = 0x40
	// Bit FPIF6.
	EXTI_FPR1_FPIF6 = 0x40
	// No trigger request occurred
	EXTI_FPR1_FPIF6_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF6_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF6_Clear = 0x1
	// Position of FPIF7 field.
	EXTI_FPR1_FPIF7_Pos = 0x7
	// Bit mask of FPIF7 field.
	EXTI_FPR1_FPIF7_Msk = 0x80
	// Bit FPIF7.
	EXTI_FPR1_FPIF7 = 0x80
	// No trigger request occurred
	EXTI_FPR1_FPIF7_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF7_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF7_Clear = 0x1
	// Position of FPIF8 field.
	EXTI_FPR1_FPIF8_Pos = 0x8
	// Bit mask of FPIF8 field.
	EXTI_FPR1_FPIF8_Msk = 0x100
	// Bit FPIF8.
	EXTI_FPR1_FPIF8 = 0x100
	// No trigger request occurred
	EXTI_FPR1_FPIF8_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF8_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF8_Clear = 0x1
	// Position of FPIF9 field.
	EXTI_FPR1_FPIF9_Pos = 0x9
	// Bit mask of FPIF9 field.
	EXTI_FPR1_FPIF9_Msk = 0x200
	// Bit FPIF9.
	EXTI_FPR1_FPIF9 = 0x200
	// No trigger request occurred
	EXTI_FPR1_FPIF9_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF9_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF9_Clear = 0x1
	// Position of FPIF10 field.
	EXTI_FPR1_FPIF10_Pos = 0xa
	// Bit mask of FPIF10 field.
	EXTI_FPR1_FPIF10_Msk = 0x400
	// Bit FPIF10.
	EXTI_FPR1_FPIF10 = 0x400
	// No trigger request occurred
	EXTI_FPR1_FPIF10_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF10_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF10_Clear = 0x1
	// Position of FPIF11 field.
	EXTI_FPR1_FPIF11_Pos = 0xb
	// Bit mask of FPIF11 field.
	EXTI_FPR1_FPIF11_Msk = 0x800
	// Bit FPIF11.
	EXTI_FPR1_FPIF11 = 0x800
	// No trigger request occurred
	EXTI_FPR1_FPIF11_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF11_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF11_Clear = 0x1
	// Position of FPIF12 field.
	EXTI_FPR1_FPIF12_Pos = 0xc
	// Bit mask of FPIF12 field.
	EXTI_FPR1_FPIF12_Msk = 0x1000
	// Bit FPIF12.
	EXTI_FPR1_FPIF12 = 0x1000
	// No trigger request occurred
	EXTI_FPR1_FPIF12_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF12_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF12_Clear = 0x1
	// Position of FPIF13 field.
	EXTI_FPR1_FPIF13_Pos = 0xd
	// Bit mask of FPIF13 field.
	EXTI_FPR1_FPIF13_Msk = 0x2000
	// Bit FPIF13.
	EXTI_FPR1_FPIF13 = 0x2000
	// No trigger request occurred
	EXTI_FPR1_FPIF13_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF13_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF13_Clear = 0x1
	// Position of FPIF14 field.
	EXTI_FPR1_FPIF14_Pos = 0xe
	// Bit mask of FPIF14 field.
	EXTI_FPR1_FPIF14_Msk = 0x4000
	// Bit FPIF14.
	EXTI_FPR1_FPIF14 = 0x4000
	// No trigger request occurred
	EXTI_FPR1_FPIF14_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF14_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF14_Clear = 0x1
	// Position of FPIF15 field.
	EXTI_FPR1_FPIF15_Pos = 0xf
	// Bit mask of FPIF15 field.
	EXTI_FPR1_FPIF15_Msk = 0x8000
	// Bit FPIF15.
	EXTI_FPR1_FPIF15 = 0x8000
	// No trigger request occurred
	EXTI_FPR1_FPIF15_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF15_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF15_Clear = 0x1

	// EXTICR1: EXTI external interrupt selection register
	// Position of EXTI0 field.
	EXTI_EXTICR1_EXTI0_Pos = 0x0
	// Bit mask of EXTI0 field.
	EXTI_EXTICR1_EXTI0_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PF = 0x5
	// Position of EXTI1 field.
	EXTI_EXTICR1_EXTI1_Pos = 0x8
	// Bit mask of EXTI1 field.
	EXTI_EXTICR1_EXTI1_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PF = 0x5
	// Position of EXTI2 field.
	EXTI_EXTICR1_EXTI2_Pos = 0x10
	// Bit mask of EXTI2 field.
	EXTI_EXTICR1_EXTI2_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PF = 0x5
	// Position of EXTI3 field.
	EXTI_EXTICR1_EXTI3_Pos = 0x18
	// Bit mask of EXTI3 field.
	EXTI_EXTICR1_EXTI3_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PF = 0x5

	// EXTICR2: EXTI external interrupt selection register
	// Position of EXTI4 field.
	EXTI_EXTICR2_EXTI4_Pos = 0x0
	// Bit mask of EXTI4 field.
	EXTI_EXTICR2_EXTI4_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PF = 0x5
	// Position of EXTI5 field.
	EXTI_EXTICR2_EXTI5_Pos = 0x8
	// Bit mask of EXTI5 field.
	EXTI_EXTICR2_EXTI5_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PF = 0x5
	// Position of EXTI6 field.
	EXTI_EXTICR2_EXTI6_Pos = 0x10
	// Bit mask of EXTI6 field.
	EXTI_EXTICR2_EXTI6_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PF = 0x5
	// Position of EXTI7 field.
	EXTI_EXTICR2_EXTI7_Pos = 0x18
	// Bit mask of EXTI7 field.
	EXTI_EXTICR2_EXTI7_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PF = 0x5

	// EXTICR3: EXTI external interrupt selection register
	// Position of EXTI8 field.
	EXTI_EXTICR3_EXTI8_Pos = 0x0
	// Bit mask of EXTI8 field.
	EXTI_EXTICR3_EXTI8_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PF = 0x5
	// Position of EXTI9 field.
	EXTI_EXTICR3_EXTI9_Pos = 0x8
	// Bit mask of EXTI9 field.
	EXTI_EXTICR3_EXTI9_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PF = 0x5
	// Position of EXTI10 field.
	EXTI_EXTICR3_EXTI10_Pos = 0x10
	// Bit mask of EXTI10 field.
	EXTI_EXTICR3_EXTI10_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PF = 0x5
	// Position of EXTI11 field.
	EXTI_EXTICR3_EXTI11_Pos = 0x18
	// Bit mask of EXTI11 field.
	EXTI_EXTICR3_EXTI11_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PF = 0x5

	// EXTICR4: EXTI external interrupt selection register
	// Position of EXTI12 field.
	EXTI_EXTICR4_EXTI12_Pos = 0x0
	// Bit mask of EXTI12 field.
	EXTI_EXTICR4_EXTI12_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PF = 0x5
	// Position of EXTI13 field.
	EXTI_EXTICR4_EXTI13_Pos = 0x8
	// Bit mask of EXTI13 field.
	EXTI_EXTICR4_EXTI13_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PF = 0x5
	// Position of EXTI14 field.
	EXTI_EXTICR4_EXTI14_Pos = 0x10
	// Bit mask of EXTI14 field.
	EXTI_EXTICR4_EXTI14_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PF = 0x5
	// Position of EXTI15 field.
	EXTI_EXTICR4_EXTI15_Pos = 0x18
	// Bit mask of EXTI15 field.
	EXTI_EXTICR4_EXTI15_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PD = 0x3
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PF = 0x5

	// IMR1: EXTI CPU wakeup with interrupt mask register
	// Position of IM0 field.
	EXTI_IMR1_IM0_Pos = 0x0
	// Bit mask of IM0 field.
	EXTI_IMR1_IM0_Msk = 0x1
	// Bit IM0.
	EXTI_IMR1_IM0 = 0x1
	// Interrupt request line is masked
	EXTI_IMR1_IM0_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM0_Unmasked = 0x1
	// Position of IM1 field.
	EXTI_IMR1_IM1_Pos = 0x1
	// Bit mask of IM1 field.
	EXTI_IMR1_IM1_Msk = 0x2
	// Bit IM1.
	EXTI_IMR1_IM1 = 0x2
	// Interrupt request line is masked
	EXTI_IMR1_IM1_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM1_Unmasked = 0x1
	// Position of IM2 field.
	EXTI_IMR1_IM2_Pos = 0x2
	// Bit mask of IM2 field.
	EXTI_IMR1_IM2_Msk = 0x4
	// Bit IM2.
	EXTI_IMR1_IM2 = 0x4
	// Interrupt request line is masked
	EXTI_IMR1_IM2_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM2_Unmasked = 0x1
	// Position of IM3 field.
	EXTI_IMR1_IM3_Pos = 0x3
	// Bit mask of IM3 field.
	EXTI_IMR1_IM3_Msk = 0x8
	// Bit IM3.
	EXTI_IMR1_IM3 = 0x8
	// Interrupt request line is masked
	EXTI_IMR1_IM3_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM3_Unmasked = 0x1
	// Position of IM4 field.
	EXTI_IMR1_IM4_Pos = 0x4
	// Bit mask of IM4 field.
	EXTI_IMR1_IM4_Msk = 0x10
	// Bit IM4.
	EXTI_IMR1_IM4 = 0x10
	// Interrupt request line is masked
	EXTI_IMR1_IM4_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM4_Unmasked = 0x1
	// Position of IM5 field.
	EXTI_IMR1_IM5_Pos = 0x5
	// Bit mask of IM5 field.
	EXTI_IMR1_IM5_Msk = 0x20
	// Bit IM5.
	EXTI_IMR1_IM5 = 0x20
	// Interrupt request line is masked
	EXTI_IMR1_IM5_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM5_Unmasked = 0x1
	// Position of IM6 field.
	EXTI_IMR1_IM6_Pos = 0x6
	// Bit mask of IM6 field.
	EXTI_IMR1_IM6_Msk = 0x40
	// Bit IM6.
	EXTI_IMR1_IM6 = 0x40
	// Interrupt request line is masked
	EXTI_IMR1_IM6_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM6_Unmasked = 0x1
	// Position of IM7 field.
	EXTI_IMR1_IM7_Pos = 0x7
	// Bit mask of IM7 field.
	EXTI_IMR1_IM7_Msk = 0x80
	// Bit IM7.
	EXTI_IMR1_IM7 = 0x80
	// Interrupt request line is masked
	EXTI_IMR1_IM7_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM7_Unmasked = 0x1
	// Position of IM8 field.
	EXTI_IMR1_IM8_Pos = 0x8
	// Bit mask of IM8 field.
	EXTI_IMR1_IM8_Msk = 0x100
	// Bit IM8.
	EXTI_IMR1_IM8 = 0x100
	// Interrupt request line is masked
	EXTI_IMR1_IM8_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM8_Unmasked = 0x1
	// Position of IM9 field.
	EXTI_IMR1_IM9_Pos = 0x9
	// Bit mask of IM9 field.
	EXTI_IMR1_IM9_Msk = 0x200
	// Bit IM9.
	EXTI_IMR1_IM9 = 0x200
	// Interrupt request line is masked
	EXTI_IMR1_IM9_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM9_Unmasked = 0x1
	// Position of IM10 field.
	EXTI_IMR1_IM10_Pos = 0xa
	// Bit mask of IM10 field.
	EXTI_IMR1_IM10_Msk = 0x400
	// Bit IM10.
	EXTI_IMR1_IM10 = 0x400
	// Interrupt request line is masked
	EXTI_IMR1_IM10_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM10_Unmasked = 0x1
	// Position of IM11 field.
	EXTI_IMR1_IM11_Pos = 0xb
	// Bit mask of IM11 field.
	EXTI_IMR1_IM11_Msk = 0x800
	// Bit IM11.
	EXTI_IMR1_IM11 = 0x800
	// Interrupt request line is masked
	EXTI_IMR1_IM11_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM11_Unmasked = 0x1
	// Position of IM12 field.
	EXTI_IMR1_IM12_Pos = 0xc
	// Bit mask of IM12 field.
	EXTI_IMR1_IM12_Msk = 0x1000
	// Bit IM12.
	EXTI_IMR1_IM12 = 0x1000
	// Interrupt request line is masked
	EXTI_IMR1_IM12_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM12_Unmasked = 0x1
	// Position of IM13 field.
	EXTI_IMR1_IM13_Pos = 0xd
	// Bit mask of IM13 field.
	EXTI_IMR1_IM13_Msk = 0x2000
	// Bit IM13.
	EXTI_IMR1_IM13 = 0x2000
	// Interrupt request line is masked
	EXTI_IMR1_IM13_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM13_Unmasked = 0x1
	// Position of IM14 field.
	EXTI_IMR1_IM14_Pos = 0xe
	// Bit mask of IM14 field.
	EXTI_IMR1_IM14_Msk = 0x4000
	// Bit IM14.
	EXTI_IMR1_IM14 = 0x4000
	// Interrupt request line is masked
	EXTI_IMR1_IM14_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM14_Unmasked = 0x1
	// Position of IM15 field.
	EXTI_IMR1_IM15_Pos = 0xf
	// Bit mask of IM15 field.
	EXTI_IMR1_IM15_Msk = 0x8000
	// Bit IM15.
	EXTI_IMR1_IM15 = 0x8000
	// Interrupt request line is masked
	EXTI_IMR1_IM15_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM15_Unmasked = 0x1
	// Position of IM19 field.
	EXTI_IMR1_IM19_Pos = 0x13
	// Bit mask of IM19 field.
	EXTI_IMR1_IM19_Msk = 0x80000
	// Bit IM19.
	EXTI_IMR1_IM19 = 0x80000
	// Interrupt request line is masked
	EXTI_IMR1_IM19_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM19_Unmasked = 0x1
	// Position of IM21 field.
	EXTI_IMR1_IM21_Pos = 0x15
	// Bit mask of IM21 field.
	EXTI_IMR1_IM21_Msk = 0x200000
	// Bit IM21.
	EXTI_IMR1_IM21 = 0x200000
	// Interrupt request line is masked
	EXTI_IMR1_IM21_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM21_Unmasked = 0x1
	// Position of IM22 field.
	EXTI_IMR1_IM22_Pos = 0x16
	// Bit mask of IM22 field.
	EXTI_IMR1_IM22_Msk = 0x400000
	// Bit IM22.
	EXTI_IMR1_IM22 = 0x400000
	// Interrupt request line is masked
	EXTI_IMR1_IM22_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM22_Unmasked = 0x1
	// Position of IM23 field.
	EXTI_IMR1_IM23_Pos = 0x17
	// Bit mask of IM23 field.
	EXTI_IMR1_IM23_Msk = 0x800000
	// Bit IM23.
	EXTI_IMR1_IM23 = 0x800000
	// Interrupt request line is masked
	EXTI_IMR1_IM23_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM23_Unmasked = 0x1
	// Position of IM24 field.
	EXTI_IMR1_IM24_Pos = 0x18
	// Bit mask of IM24 field.
	EXTI_IMR1_IM24_Msk = 0x1000000
	// Bit IM24.
	EXTI_IMR1_IM24 = 0x1000000
	// Interrupt request line is masked
	EXTI_IMR1_IM24_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM24_Unmasked = 0x1
	// Position of IM25 field.
	EXTI_IMR1_IM25_Pos = 0x19
	// Bit mask of IM25 field.
	EXTI_IMR1_IM25_Msk = 0x2000000
	// Bit IM25.
	EXTI_IMR1_IM25 = 0x2000000
	// Interrupt request line is masked
	EXTI_IMR1_IM25_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM25_Unmasked = 0x1
	// Position of IM26 field.
	EXTI_IMR1_IM26_Pos = 0x1a
	// Bit mask of IM26 field.
	EXTI_IMR1_IM26_Msk = 0x4000000
	// Bit IM26.
	EXTI_IMR1_IM26 = 0x4000000
	// Interrupt request line is masked
	EXTI_IMR1_IM26_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM26_Unmasked = 0x1
	// Position of IM31 field.
	EXTI_IMR1_IM31_Pos = 0x1f
	// Bit mask of IM31 field.
	EXTI_IMR1_IM31_Msk = 0x80000000
	// Bit IM31.
	EXTI_IMR1_IM31 = 0x80000000
	// Interrupt request line is masked
	EXTI_IMR1_IM31_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM31_Unmasked = 0x1

	// EMR1: EXTI CPU wakeup with event mask register
	// Position of EM0 field.
	EXTI_EMR1_EM0_Pos = 0x0
	// Bit mask of EM0 field.
	EXTI_EMR1_EM0_Msk = 0x1
	// Bit EM0.
	EXTI_EMR1_EM0 = 0x1
	// Event request line is masked
	EXTI_EMR1_EM0_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM0_Unmasked = 0x1
	// Position of EM1 field.
	EXTI_EMR1_EM1_Pos = 0x1
	// Bit mask of EM1 field.
	EXTI_EMR1_EM1_Msk = 0x2
	// Bit EM1.
	EXTI_EMR1_EM1 = 0x2
	// Event request line is masked
	EXTI_EMR1_EM1_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM1_Unmasked = 0x1
	// Position of EM2 field.
	EXTI_EMR1_EM2_Pos = 0x2
	// Bit mask of EM2 field.
	EXTI_EMR1_EM2_Msk = 0x4
	// Bit EM2.
	EXTI_EMR1_EM2 = 0x4
	// Event request line is masked
	EXTI_EMR1_EM2_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM2_Unmasked = 0x1
	// Position of EM3 field.
	EXTI_EMR1_EM3_Pos = 0x3
	// Bit mask of EM3 field.
	EXTI_EMR1_EM3_Msk = 0x8
	// Bit EM3.
	EXTI_EMR1_EM3 = 0x8
	// Event request line is masked
	EXTI_EMR1_EM3_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM3_Unmasked = 0x1
	// Position of EM4 field.
	EXTI_EMR1_EM4_Pos = 0x4
	// Bit mask of EM4 field.
	EXTI_EMR1_EM4_Msk = 0x10
	// Bit EM4.
	EXTI_EMR1_EM4 = 0x10
	// Event request line is masked
	EXTI_EMR1_EM4_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM4_Unmasked = 0x1
	// Position of EM5 field.
	EXTI_EMR1_EM5_Pos = 0x5
	// Bit mask of EM5 field.
	EXTI_EMR1_EM5_Msk = 0x20
	// Bit EM5.
	EXTI_EMR1_EM5 = 0x20
	// Event request line is masked
	EXTI_EMR1_EM5_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM5_Unmasked = 0x1
	// Position of EM6 field.
	EXTI_EMR1_EM6_Pos = 0x6
	// Bit mask of EM6 field.
	EXTI_EMR1_EM6_Msk = 0x40
	// Bit EM6.
	EXTI_EMR1_EM6 = 0x40
	// Event request line is masked
	EXTI_EMR1_EM6_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM6_Unmasked = 0x1
	// Position of EM7 field.
	EXTI_EMR1_EM7_Pos = 0x7
	// Bit mask of EM7 field.
	EXTI_EMR1_EM7_Msk = 0x80
	// Bit EM7.
	EXTI_EMR1_EM7 = 0x80
	// Event request line is masked
	EXTI_EMR1_EM7_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM7_Unmasked = 0x1
	// Position of EM8 field.
	EXTI_EMR1_EM8_Pos = 0x8
	// Bit mask of EM8 field.
	EXTI_EMR1_EM8_Msk = 0x100
	// Bit EM8.
	EXTI_EMR1_EM8 = 0x100
	// Event request line is masked
	EXTI_EMR1_EM8_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM8_Unmasked = 0x1
	// Position of EM9 field.
	EXTI_EMR1_EM9_Pos = 0x9
	// Bit mask of EM9 field.
	EXTI_EMR1_EM9_Msk = 0x200
	// Bit EM9.
	EXTI_EMR1_EM9 = 0x200
	// Event request line is masked
	EXTI_EMR1_EM9_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM9_Unmasked = 0x1
	// Position of EM10 field.
	EXTI_EMR1_EM10_Pos = 0xa
	// Bit mask of EM10 field.
	EXTI_EMR1_EM10_Msk = 0x400
	// Bit EM10.
	EXTI_EMR1_EM10 = 0x400
	// Event request line is masked
	EXTI_EMR1_EM10_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM10_Unmasked = 0x1
	// Position of EM11 field.
	EXTI_EMR1_EM11_Pos = 0xb
	// Bit mask of EM11 field.
	EXTI_EMR1_EM11_Msk = 0x800
	// Bit EM11.
	EXTI_EMR1_EM11 = 0x800
	// Event request line is masked
	EXTI_EMR1_EM11_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM11_Unmasked = 0x1
	// Position of EM12 field.
	EXTI_EMR1_EM12_Pos = 0xc
	// Bit mask of EM12 field.
	EXTI_EMR1_EM12_Msk = 0x1000
	// Bit EM12.
	EXTI_EMR1_EM12 = 0x1000
	// Event request line is masked
	EXTI_EMR1_EM12_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM12_Unmasked = 0x1
	// Position of EM13 field.
	EXTI_EMR1_EM13_Pos = 0xd
	// Bit mask of EM13 field.
	EXTI_EMR1_EM13_Msk = 0x2000
	// Bit EM13.
	EXTI_EMR1_EM13 = 0x2000
	// Event request line is masked
	EXTI_EMR1_EM13_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM13_Unmasked = 0x1
	// Position of EM14 field.
	EXTI_EMR1_EM14_Pos = 0xe
	// Bit mask of EM14 field.
	EXTI_EMR1_EM14_Msk = 0x4000
	// Bit EM14.
	EXTI_EMR1_EM14 = 0x4000
	// Event request line is masked
	EXTI_EMR1_EM14_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM14_Unmasked = 0x1
	// Position of EM15 field.
	EXTI_EMR1_EM15_Pos = 0xf
	// Bit mask of EM15 field.
	EXTI_EMR1_EM15_Msk = 0x8000
	// Bit EM15.
	EXTI_EMR1_EM15 = 0x8000
	// Event request line is masked
	EXTI_EMR1_EM15_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM15_Unmasked = 0x1
	// Position of EM19 field.
	EXTI_EMR1_EM19_Pos = 0x13
	// Bit mask of EM19 field.
	EXTI_EMR1_EM19_Msk = 0x80000
	// Bit EM19.
	EXTI_EMR1_EM19 = 0x80000
	// Event request line is masked
	EXTI_EMR1_EM19_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM19_Unmasked = 0x1
	// Position of EM21 field.
	EXTI_EMR1_EM21_Pos = 0x15
	// Bit mask of EM21 field.
	EXTI_EMR1_EM21_Msk = 0x200000
	// Bit EM21.
	EXTI_EMR1_EM21 = 0x200000
	// Event request line is masked
	EXTI_EMR1_EM21_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM21_Unmasked = 0x1
	// Position of EM23 field.
	EXTI_EMR1_EM23_Pos = 0x17
	// Bit mask of EM23 field.
	EXTI_EMR1_EM23_Msk = 0x800000
	// Bit EM23.
	EXTI_EMR1_EM23 = 0x800000
	// Event request line is masked
	EXTI_EMR1_EM23_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM23_Unmasked = 0x1
	// Position of EM25 field.
	EXTI_EMR1_EM25_Pos = 0x19
	// Bit mask of EM25 field.
	EXTI_EMR1_EM25_Msk = 0x2000000
	// Bit EM25.
	EXTI_EMR1_EM25 = 0x2000000
	// Event request line is masked
	EXTI_EMR1_EM25_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM25_Unmasked = 0x1
	// Position of EM26 field.
	EXTI_EMR1_EM26_Pos = 0x1a
	// Bit mask of EM26 field.
	EXTI_EMR1_EM26_Msk = 0x4000000
	// Bit EM26.
	EXTI_EMR1_EM26 = 0x4000000
	// Event request line is masked
	EXTI_EMR1_EM26_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM26_Unmasked = 0x1
	// Position of EM31 field.
	EXTI_EMR1_EM31_Pos = 0x1f
	// Bit mask of EM31 field.
	EXTI_EMR1_EM31_Msk = 0x80000000
	// Bit EM31.
	EXTI_EMR1_EM31 = 0x80000000
	// Event request line is masked
	EXTI_EMR1_EM31_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM31_Unmasked = 0x1
)

// Constants for FLASH: Flash
const (
	// ACR: Access control register
	// Position of LATENCY field.
	Flash_ACR_LATENCY_Pos = 0x0
	// Bit mask of LATENCY field.
	Flash_ACR_LATENCY_Msk = 0x7
	// Position of PRFTEN field.
	Flash_ACR_PRFTEN_Pos = 0x8
	// Bit mask of PRFTEN field.
	Flash_ACR_PRFTEN_Msk = 0x100
	// Bit PRFTEN.
	Flash_ACR_PRFTEN = 0x100
	// Position of ICEN field.
	Flash_ACR_ICEN_Pos = 0x9
	// Bit mask of ICEN field.
	Flash_ACR_ICEN_Msk = 0x200
	// Bit ICEN.
	Flash_ACR_ICEN = 0x200
	// Position of ICRST field.
	Flash_ACR_ICRST_Pos = 0xb
	// Bit mask of ICRST field.
	Flash_ACR_ICRST_Msk = 0x800
	// Bit ICRST.
	Flash_ACR_ICRST = 0x800
	// Position of EMPTY field.
	Flash_ACR_EMPTY_Pos = 0x10
	// Bit mask of EMPTY field.
	Flash_ACR_EMPTY_Msk = 0x10000
	// Bit EMPTY.
	Flash_ACR_EMPTY = 0x10000

	// KEYR: Flash key register
	// Position of KEY field.
	Flash_KEYR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	Flash_KEYR_KEY_Msk = 0xffffffff

	// OPTKEYR: Option byte key register
	// Position of OPTKEY field.
	Flash_OPTKEYR_OPTKEY_Pos = 0x0
	// Bit mask of OPTKEY field.
	Flash_OPTKEYR_OPTKEY_Msk = 0xffffffff

	// SR: Status register
	// Position of EOP field.
	Flash_SR_EOP_Pos = 0x0
	// Bit mask of EOP field.
	Flash_SR_EOP_Msk = 0x1
	// Bit EOP.
	Flash_SR_EOP = 0x1
	// Position of OPERR field.
	Flash_SR_OPERR_Pos = 0x1
	// Bit mask of OPERR field.
	Flash_SR_OPERR_Msk = 0x2
	// Bit OPERR.
	Flash_SR_OPERR = 0x2
	// Position of PROGERR field.
	Flash_SR_PROGERR_Pos = 0x3
	// Bit mask of PROGERR field.
	Flash_SR_PROGERR_Msk = 0x8
	// Bit PROGERR.
	Flash_SR_PROGERR = 0x8
	// Position of WRPERR field.
	Flash_SR_WRPERR_Pos = 0x4
	// Bit mask of WRPERR field.
	Flash_SR_WRPERR_Msk = 0x10
	// Bit WRPERR.
	Flash_SR_WRPERR = 0x10
	// Position of PGAERR field.
	Flash_SR_PGAERR_Pos = 0x5
	// Bit mask of PGAERR field.
	Flash_SR_PGAERR_Msk = 0x20
	// Bit PGAERR.
	Flash_SR_PGAERR = 0x20
	// Position of SIZERR field.
	Flash_SR_SIZERR_Pos = 0x6
	// Bit mask of SIZERR field.
	Flash_SR_SIZERR_Msk = 0x40
	// Bit SIZERR.
	Flash_SR_SIZERR = 0x40
	// Position of PGSERR field.
	Flash_SR_PGSERR_Pos = 0x7
	// Bit mask of PGSERR field.
	Flash_SR_PGSERR_Msk = 0x80
	// Bit PGSERR.
	Flash_SR_PGSERR = 0x80
	// Position of MISSERR field.
	Flash_SR_MISSERR_Pos = 0x8
	// Bit mask of MISSERR field.
	Flash_SR_MISSERR_Msk = 0x100
	// Bit MISSERR.
	Flash_SR_MISSERR = 0x100
	// Position of FASTERR field.
	Flash_SR_FASTERR_Pos = 0x9
	// Bit mask of FASTERR field.
	Flash_SR_FASTERR_Msk = 0x200
	// Bit FASTERR.
	Flash_SR_FASTERR = 0x200
	// Position of OPTVERR field.
	Flash_SR_OPTVERR_Pos = 0xf
	// Bit mask of OPTVERR field.
	Flash_SR_OPTVERR_Msk = 0x8000
	// Bit OPTVERR.
	Flash_SR_OPTVERR = 0x8000
	// Position of BSY1 field.
	Flash_SR_BSY1_Pos = 0x10
	// Bit mask of BSY1 field.
	Flash_SR_BSY1_Msk = 0x10000
	// Bit BSY1.
	Flash_SR_BSY1 = 0x10000
	// Position of BSY2 field.
	Flash_SR_BSY2_Pos = 0x11
	// Bit mask of BSY2 field.
	Flash_SR_BSY2_Msk = 0x20000
	// Bit BSY2.
	Flash_SR_BSY2 = 0x20000
	// Position of CFGBSY field.
	Flash_SR_CFGBSY_Pos = 0x12
	// Bit mask of CFGBSY field.
	Flash_SR_CFGBSY_Msk = 0x40000
	// Bit CFGBSY.
	Flash_SR_CFGBSY = 0x40000

	// CR: Flash control register
	// Position of PG field.
	Flash_CR_PG_Pos = 0x0
	// Bit mask of PG field.
	Flash_CR_PG_Msk = 0x1
	// Bit PG.
	Flash_CR_PG = 0x1
	// Position of PER field.
	Flash_CR_PER_Pos = 0x1
	// Bit mask of PER field.
	Flash_CR_PER_Msk = 0x2
	// Bit PER.
	Flash_CR_PER = 0x2
	// Position of MER1 field.
	Flash_CR_MER1_Pos = 0x2
	// Bit mask of MER1 field.
	Flash_CR_MER1_Msk = 0x4
	// Bit MER1.
	Flash_CR_MER1 = 0x4
	// Position of PNB field.
	Flash_CR_PNB_Pos = 0x3
	// Bit mask of PNB field.
	Flash_CR_PNB_Msk = 0x1ff8
	// Position of BKER field.
	Flash_CR_BKER_Pos = 0xd
	// Bit mask of BKER field.
	Flash_CR_BKER_Msk = 0x2000
	// Bit BKER.
	Flash_CR_BKER = 0x2000
	// Position of MER2 field.
	Flash_CR_MER2_Pos = 0xf
	// Bit mask of MER2 field.
	Flash_CR_MER2_Msk = 0x8000
	// Bit MER2.
	Flash_CR_MER2 = 0x8000
	// Position of STRT field.
	Flash_CR_STRT_Pos = 0x10
	// Bit mask of STRT field.
	Flash_CR_STRT_Msk = 0x10000
	// Bit STRT.
	Flash_CR_STRT = 0x10000
	// Position of OPTSTRT field.
	Flash_CR_OPTSTRT_Pos = 0x11
	// Bit mask of OPTSTRT field.
	Flash_CR_OPTSTRT_Msk = 0x20000
	// Bit OPTSTRT.
	Flash_CR_OPTSTRT = 0x20000
	// Position of FSTPG field.
	Flash_CR_FSTPG_Pos = 0x12
	// Bit mask of FSTPG field.
	Flash_CR_FSTPG_Msk = 0x40000
	// Bit FSTPG.
	Flash_CR_FSTPG = 0x40000
	// Position of EOPIE field.
	Flash_CR_EOPIE_Pos = 0x18
	// Bit mask of EOPIE field.
	Flash_CR_EOPIE_Msk = 0x1000000
	// Bit EOPIE.
	Flash_CR_EOPIE = 0x1000000
	// Position of ERRIE field.
	Flash_CR_ERRIE_Pos = 0x19
	// Bit mask of ERRIE field.
	Flash_CR_ERRIE_Msk = 0x2000000
	// Bit ERRIE.
	Flash_CR_ERRIE = 0x2000000
	// Position of OBL_LAUNCH field.
	Flash_CR_OBL_LAUNCH_Pos = 0x1b
	// Bit mask of OBL_LAUNCH field.
	Flash_CR_OBL_LAUNCH_Msk = 0x8000000
	// Bit OBL_LAUNCH.
	Flash_CR_OBL_LAUNCH = 0x8000000
	// Position of OPTLOCK field.
	Flash_CR_OPTLOCK_Pos = 0x1e
	// Bit mask of OPTLOCK field.
	Flash_CR_OPTLOCK_Msk = 0x40000000
	// Bit OPTLOCK.
	Flash_CR_OPTLOCK = 0x40000000
	// Position of LOCK field.
	Flash_CR_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	Flash_CR_LOCK_Msk = 0x80000000
	// Bit LOCK.
	Flash_CR_LOCK = 0x80000000

	// ECCR: Flash ECC register
	// Position of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Pos = 0x0
	// Bit mask of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Msk = 0x3fff
	// Position of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Pos = 0x14
	// Bit mask of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Msk = 0x100000
	// Bit SYSF_ECC.
	Flash_ECCR_SYSF_ECC = 0x100000
	// Position of ECCIE field.
	Flash_ECCR_ECCIE_Pos = 0x18
	// Bit mask of ECCIE field.
	Flash_ECCR_ECCIE_Msk = 0x1000000
	// Bit ECCIE.
	Flash_ECCR_ECCIE = 0x1000000
	// Position of ECCC field.
	Flash_ECCR_ECCC_Pos = 0x1e
	// Bit mask of ECCC field.
	Flash_ECCR_ECCC_Msk = 0x40000000
	// Bit ECCC.
	Flash_ECCR_ECCC = 0x40000000
	// Position of ECCD field.
	Flash_ECCR_ECCD_Pos = 0x1f
	// Bit mask of ECCD field.
	Flash_ECCR_ECCD_Msk = 0x80000000
	// Bit ECCD.
	Flash_ECCR_ECCD = 0x80000000

	// OPTR: Flash option register
	// Position of RDP field.
	Flash_OPTR_RDP_Pos = 0x0
	// Bit mask of RDP field.
	Flash_OPTR_RDP_Msk = 0xff
	// Position of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Pos = 0xd
	// Bit mask of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Msk = 0x2000
	// Bit NRST_STOP.
	Flash_OPTR_NRST_STOP = 0x2000
	// Position of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Pos = 0xe
	// Bit mask of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Msk = 0x4000
	// Bit NRST_STDBY.
	Flash_OPTR_NRST_STDBY = 0x4000
	// Position of IWDG_SW field.
	Flash_OPTR_IWDG_SW_Pos = 0x10
	// Bit mask of IWDG_SW field.
	Flash_OPTR_IWDG_SW_Msk = 0x10000
	// Bit IWDG_SW.
	Flash_OPTR_IWDG_SW = 0x10000
	// Position of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Pos = 0x11
	// Bit mask of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Msk = 0x20000
	// Bit IWDG_STOP.
	Flash_OPTR_IWDG_STOP = 0x20000
	// Position of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Pos = 0x12
	// Bit mask of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Msk = 0x40000
	// Bit IWDG_STDBY.
	Flash_OPTR_IWDG_STDBY = 0x40000
	// Position of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Pos = 0x13
	// Bit mask of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Msk = 0x80000
	// Bit WWDG_SW.
	Flash_OPTR_WWDG_SW = 0x80000
	// Position of NSWAP_BANK field.
	Flash_OPTR_NSWAP_BANK_Pos = 0x14
	// Bit mask of NSWAP_BANK field.
	Flash_OPTR_NSWAP_BANK_Msk = 0x100000
	// Bit NSWAP_BANK.
	Flash_OPTR_NSWAP_BANK = 0x100000
	// Position of DUAL_BANK field.
	Flash_OPTR_DUAL_BANK_Pos = 0x15
	// Bit mask of DUAL_BANK field.
	Flash_OPTR_DUAL_BANK_Msk = 0x200000
	// Bit DUAL_BANK.
	Flash_OPTR_DUAL_BANK = 0x200000
	// Position of RAM_PARITY_CHECK field.
	Flash_OPTR_RAM_PARITY_CHECK_Pos = 0x16
	// Bit mask of RAM_PARITY_CHECK field.
	Flash_OPTR_RAM_PARITY_CHECK_Msk = 0x400000
	// Bit RAM_PARITY_CHECK.
	Flash_OPTR_RAM_PARITY_CHECK = 0x400000
	// Position of NBOOT_SEL field.
	Flash_OPTR_NBOOT_SEL_Pos = 0x18
	// Bit mask of NBOOT_SEL field.
	Flash_OPTR_NBOOT_SEL_Msk = 0x1000000
	// Bit NBOOT_SEL.
	Flash_OPTR_NBOOT_SEL = 0x1000000
	// Position of NBOOT1 field.
	Flash_OPTR_NBOOT1_Pos = 0x19
	// Bit mask of NBOOT1 field.
	Flash_OPTR_NBOOT1_Msk = 0x2000000
	// Bit NBOOT1.
	Flash_OPTR_NBOOT1 = 0x2000000
	// Position of NBOOT0 field.
	Flash_OPTR_NBOOT0_Pos = 0x1a
	// Bit mask of NBOOT0 field.
	Flash_OPTR_NBOOT0_Msk = 0x4000000
	// Bit NBOOT0.
	Flash_OPTR_NBOOT0 = 0x4000000

	// WRP1AR: Flash WRP area A address register
	// Position of WRP1A_STRT field.
	Flash_WRP1AR_WRP1A_STRT_Pos = 0x0
	// Bit mask of WRP1A_STRT field.
	Flash_WRP1AR_WRP1A_STRT_Msk = 0x7f
	// Position of WRP1A_END field.
	Flash_WRP1AR_WRP1A_END_Pos = 0x10
	// Bit mask of WRP1A_END field.
	Flash_WRP1AR_WRP1A_END_Msk = 0x7f0000

	// WRP1BR: Flash WRP area B address register
	// Position of WRP1B_STRT field.
	Flash_WRP1BR_WRP1B_STRT_Pos = 0x0
	// Bit mask of WRP1B_STRT field.
	Flash_WRP1BR_WRP1B_STRT_Msk = 0x7f
	// Position of WRP1B_END field.
	Flash_WRP1BR_WRP1B_END_Pos = 0x10
	// Bit mask of WRP1B_END field.
	Flash_WRP1BR_WRP1B_END_Msk = 0x7f0000

	// WRP2AR: FLASH WRP2 area A address register
	// Position of WRP2A_STRT field.
	Flash_WRP2AR_WRP2A_STRT_Pos = 0x0
	// Bit mask of WRP2A_STRT field.
	Flash_WRP2AR_WRP2A_STRT_Msk = 0x7f
	// Position of WRP2A_END field.
	Flash_WRP2AR_WRP2A_END_Pos = 0x10
	// Bit mask of WRP2A_END field.
	Flash_WRP2AR_WRP2A_END_Msk = 0x7f0000

	// WRP2BR: FLASH WRP2 area B address register
	// Position of WRP2B_STRT field.
	Flash_WRP2BR_WRP2B_STRT_Pos = 0x0
	// Bit mask of WRP2B_STRT field.
	Flash_WRP2BR_WRP2B_STRT_Msk = 0x7f
	// Position of WRP2B_END field.
	Flash_WRP2BR_WRP2B_END_Pos = 0x10
	// Bit mask of WRP2B_END field.
	Flash_WRP2BR_WRP2B_END_Msk = 0x7f0000
)

// Constants for GPIOA: General-purpose I/Os
const (
	// MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIO_MODER_MODER0_Pos = 0x2
	// Bit mask of MODER0 field.
	GPIO_MODER_MODER0_Msk = 0xc
	// Input mode
	GPIO_MODER_MODER0_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER0_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER0_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER0_Analog = 0x3
	// Position of MODER1 field.
	GPIO_MODER_MODER1_Pos = 0x4
	// Bit mask of MODER1 field.
	GPIO_MODER_MODER1_Msk = 0x30
	// Input mode
	GPIO_MODER_MODER1_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER1_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER1_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER1_Analog = 0x3
	// Position of MODER2 field.
	GPIO_MODER_MODER2_Pos = 0x6
	// Bit mask of MODER2 field.
	GPIO_MODER_MODER2_Msk = 0xc0
	// Input mode
	GPIO_MODER_MODER2_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER2_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER2_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER2_Analog = 0x3
	// Position of MODER3 field.
	GPIO_MODER_MODER3_Pos = 0x8
	// Bit mask of MODER3 field.
	GPIO_MODER_MODER3_Msk = 0x300
	// Input mode
	GPIO_MODER_MODER3_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER3_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER3_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER3_Analog = 0x3
	// Position of MODER4 field.
	GPIO_MODER_MODER4_Pos = 0xa
	// Bit mask of MODER4 field.
	GPIO_MODER_MODER4_Msk = 0xc00
	// Input mode
	GPIO_MODER_MODER4_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER4_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER4_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER4_Analog = 0x3
	// Position of MODER5 field.
	GPIO_MODER_MODER5_Pos = 0xc
	// Bit mask of MODER5 field.
	GPIO_MODER_MODER5_Msk = 0x3000
	// Input mode
	GPIO_MODER_MODER5_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER5_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER5_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER5_Analog = 0x3
	// Position of MODER6 field.
	GPIO_MODER_MODER6_Pos = 0xe
	// Bit mask of MODER6 field.
	GPIO_MODER_MODER6_Msk = 0xc000
	// Input mode
	GPIO_MODER_MODER6_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER6_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER6_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER6_Analog = 0x3
	// Position of MODER7 field.
	GPIO_MODER_MODER7_Pos = 0x10
	// Bit mask of MODER7 field.
	GPIO_MODER_MODER7_Msk = 0x30000
	// Input mode
	GPIO_MODER_MODER7_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER7_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER7_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER7_Analog = 0x3
	// Position of MODER8 field.
	GPIO_MODER_MODER8_Pos = 0x12
	// Bit mask of MODER8 field.
	GPIO_MODER_MODER8_Msk = 0xc0000
	// Input mode
	GPIO_MODER_MODER8_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER8_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER8_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER8_Analog = 0x3
	// Position of MODER9 field.
	GPIO_MODER_MODER9_Pos = 0x14
	// Bit mask of MODER9 field.
	GPIO_MODER_MODER9_Msk = 0x300000
	// Input mode
	GPIO_MODER_MODER9_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER9_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER9_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER9_Analog = 0x3
	// Position of MODER10 field.
	GPIO_MODER_MODER10_Pos = 0x16
	// Bit mask of MODER10 field.
	GPIO_MODER_MODER10_Msk = 0xc00000
	// Input mode
	GPIO_MODER_MODER10_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER10_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER10_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER10_Analog = 0x3
	// Position of MODER11 field.
	GPIO_MODER_MODER11_Pos = 0x18
	// Bit mask of MODER11 field.
	GPIO_MODER_MODER11_Msk = 0x3000000
	// Input mode
	GPIO_MODER_MODER11_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER11_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER11_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER11_Analog = 0x3
	// Position of MODER12 field.
	GPIO_MODER_MODER12_Pos = 0x1a
	// Bit mask of MODER12 field.
	GPIO_MODER_MODER12_Msk = 0xc000000
	// Input mode
	GPIO_MODER_MODER12_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER12_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER12_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER12_Analog = 0x3
	// Position of MODER13 field.
	GPIO_MODER_MODER13_Pos = 0x1c
	// Bit mask of MODER13 field.
	GPIO_MODER_MODER13_Msk = 0x30000000
	// Input mode
	GPIO_MODER_MODER13_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER13_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER13_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER13_Analog = 0x3
	// Position of MODER14 field.
	GPIO_MODER_MODER14_Pos = 0x1e
	// Bit mask of MODER14 field.
	GPIO_MODER_MODER14_Msk = 0xc0000000
	// Input mode
	GPIO_MODER_MODER14_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER14_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER14_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER14_Analog = 0x3
	// Position of MODER15 field.
	GPIO_MODER_MODER15_Pos = 0x20
	// Bit mask of MODER15 field.
	GPIO_MODER_MODER15_Msk = 0x300000000
	// Input mode
	GPIO_MODER_MODER15_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER15_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER15_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER15_Analog = 0x3

	// OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIO_OTYPER_OT0_Pos = 0x1
	// Bit mask of OT0 field.
	GPIO_OTYPER_OT0_Msk = 0x2
	// Bit OT0.
	GPIO_OTYPER_OT0 = 0x2
	// Output push-pull (reset state)
	GPIO_OTYPER_OT0_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT0_OpenDrain = 0x1
	// Position of OT1 field.
	GPIO_OTYPER_OT1_Pos = 0x2
	// Bit mask of OT1 field.
	GPIO_OTYPER_OT1_Msk = 0x4
	// Bit OT1.
	GPIO_OTYPER_OT1 = 0x4
	// Output push-pull (reset state)
	GPIO_OTYPER_OT1_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT1_OpenDrain = 0x1
	// Position of OT2 field.
	GPIO_OTYPER_OT2_Pos = 0x3
	// Bit mask of OT2 field.
	GPIO_OTYPER_OT2_Msk = 0x8
	// Bit OT2.
	GPIO_OTYPER_OT2 = 0x8
	// Output push-pull (reset state)
	GPIO_OTYPER_OT2_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT2_OpenDrain = 0x1
	// Position of OT3 field.
	GPIO_OTYPER_OT3_Pos = 0x4
	// Bit mask of OT3 field.
	GPIO_OTYPER_OT3_Msk = 0x10
	// Bit OT3.
	GPIO_OTYPER_OT3 = 0x10
	// Output push-pull (reset state)
	GPIO_OTYPER_OT3_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT3_OpenDrain = 0x1
	// Position of OT4 field.
	GPIO_OTYPER_OT4_Pos = 0x5
	// Bit mask of OT4 field.
	GPIO_OTYPER_OT4_Msk = 0x20
	// Bit OT4.
	GPIO_OTYPER_OT4 = 0x20
	// Output push-pull (reset state)
	GPIO_OTYPER_OT4_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT4_OpenDrain = 0x1
	// Position of OT5 field.
	GPIO_OTYPER_OT5_Pos = 0x6
	// Bit mask of OT5 field.
	GPIO_OTYPER_OT5_Msk = 0x40
	// Bit OT5.
	GPIO_OTYPER_OT5 = 0x40
	// Output push-pull (reset state)
	GPIO_OTYPER_OT5_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT5_OpenDrain = 0x1
	// Position of OT6 field.
	GPIO_OTYPER_OT6_Pos = 0x7
	// Bit mask of OT6 field.
	GPIO_OTYPER_OT6_Msk = 0x80
	// Bit OT6.
	GPIO_OTYPER_OT6 = 0x80
	// Output push-pull (reset state)
	GPIO_OTYPER_OT6_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT6_OpenDrain = 0x1
	// Position of OT7 field.
	GPIO_OTYPER_OT7_Pos = 0x8
	// Bit mask of OT7 field.
	GPIO_OTYPER_OT7_Msk = 0x100
	// Bit OT7.
	GPIO_OTYPER_OT7 = 0x100
	// Output push-pull (reset state)
	GPIO_OTYPER_OT7_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT7_OpenDrain = 0x1
	// Position of OT8 field.
	GPIO_OTYPER_OT8_Pos = 0x9
	// Bit mask of OT8 field.
	GPIO_OTYPER_OT8_Msk = 0x200
	// Bit OT8.
	GPIO_OTYPER_OT8 = 0x200
	// Output push-pull (reset state)
	GPIO_OTYPER_OT8_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT8_OpenDrain = 0x1
	// Position of OT9 field.
	GPIO_OTYPER_OT9_Pos = 0xa
	// Bit mask of OT9 field.
	GPIO_OTYPER_OT9_Msk = 0x400
	// Bit OT9.
	GPIO_OTYPER_OT9 = 0x400
	// Output push-pull (reset state)
	GPIO_OTYPER_OT9_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT9_OpenDrain = 0x1
	// Position of OT10 field.
	GPIO_OTYPER_OT10_Pos = 0xb
	// Bit mask of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x800
	// Bit OT10.
	GPIO_OTYPER_OT10 = 0x800
	// Output push-pull (reset state)
	GPIO_OTYPER_OT10_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT10_OpenDrain = 0x1
	// Position of OT11 field.
	GPIO_OTYPER_OT11_Pos = 0xc
	// Bit mask of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x1000
	// Bit OT11.
	GPIO_OTYPER_OT11 = 0x1000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT11_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT11_OpenDrain = 0x1
	// Position of OT12 field.
	GPIO_OTYPER_OT12_Pos = 0xd
	// Bit mask of OT12 field.
	GPIO_OTYPER_OT12_Msk = 0x2000
	// Bit OT12.
	GPIO_OTYPER_OT12 = 0x2000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT12_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT12_OpenDrain = 0x1
	// Position of OT13 field.
	GPIO_OTYPER_OT13_Pos = 0xe
	// Bit mask of OT13 field.
	GPIO_OTYPER_OT13_Msk = 0x4000
	// Bit OT13.
	GPIO_OTYPER_OT13 = 0x4000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT13_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT13_OpenDrain = 0x1
	// Position of OT14 field.
	GPIO_OTYPER_OT14_Pos = 0xf
	// Bit mask of OT14 field.
	GPIO_OTYPER_OT14_Msk = 0x8000
	// Bit OT14.
	GPIO_OTYPER_OT14 = 0x8000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT14_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT14_OpenDrain = 0x1
	// Position of OT15 field.
	GPIO_OTYPER_OT15_Pos = 0x10
	// Bit mask of OT15 field.
	GPIO_OTYPER_OT15_Msk = 0x10000
	// Bit OT15.
	GPIO_OTYPER_OT15 = 0x10000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT15_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT15_OpenDrain = 0x1

	// OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Pos = 0x2
	// Bit mask of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Msk = 0xc
	// Low speed
	GPIO_OSPEEDR_OSPEEDR0_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR0_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR0_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR0_VeryHighSpeed = 0x3
	// Position of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Pos = 0x4
	// Bit mask of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Msk = 0x30
	// Low speed
	GPIO_OSPEEDR_OSPEEDR1_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR1_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR1_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR1_VeryHighSpeed = 0x3
	// Position of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Pos = 0x6
	// Bit mask of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Msk = 0xc0
	// Low speed
	GPIO_OSPEEDR_OSPEEDR2_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR2_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR2_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR2_VeryHighSpeed = 0x3
	// Position of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Pos = 0x8
	// Bit mask of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Msk = 0x300
	// Low speed
	GPIO_OSPEEDR_OSPEEDR3_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR3_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR3_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR3_VeryHighSpeed = 0x3
	// Position of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Pos = 0xa
	// Bit mask of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Msk = 0xc00
	// Low speed
	GPIO_OSPEEDR_OSPEEDR4_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR4_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR4_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR4_VeryHighSpeed = 0x3
	// Position of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Pos = 0xc
	// Bit mask of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Msk = 0x3000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR5_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR5_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR5_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR5_VeryHighSpeed = 0x3
	// Position of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Pos = 0xe
	// Bit mask of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Msk = 0xc000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR6_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR6_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR6_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR6_VeryHighSpeed = 0x3
	// Position of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Pos = 0x10
	// Bit mask of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Msk = 0x30000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR7_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR7_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR7_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR7_VeryHighSpeed = 0x3
	// Position of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Pos = 0x12
	// Bit mask of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Msk = 0xc0000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR8_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR8_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR8_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR8_VeryHighSpeed = 0x3
	// Position of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Pos = 0x14
	// Bit mask of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Msk = 0x300000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR9_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR9_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR9_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR9_VeryHighSpeed = 0x3
	// Position of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Pos = 0x16
	// Bit mask of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Msk = 0xc00000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR10_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR10_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR10_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR10_VeryHighSpeed = 0x3
	// Position of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Pos = 0x18
	// Bit mask of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Msk = 0x3000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR11_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR11_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR11_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR11_VeryHighSpeed = 0x3
	// Position of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Pos = 0x1a
	// Bit mask of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Msk = 0xc000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR12_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR12_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR12_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR12_VeryHighSpeed = 0x3
	// Position of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Pos = 0x1c
	// Bit mask of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Msk = 0x30000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR13_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR13_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR13_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR13_VeryHighSpeed = 0x3
	// Position of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Pos = 0x1e
	// Bit mask of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Msk = 0xc0000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR14_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR14_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR14_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR14_VeryHighSpeed = 0x3
	// Position of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Pos = 0x20
	// Bit mask of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Msk = 0x300000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR15_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR15_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR15_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR15_VeryHighSpeed = 0x3

	// PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Pos = 0x2
	// Bit mask of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Msk = 0xc
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR0_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR0_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR0_PullDown = 0x2
	// Position of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Pos = 0x4
	// Bit mask of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Msk = 0x30
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR1_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR1_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR1_PullDown = 0x2
	// Position of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Pos = 0x6
	// Bit mask of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Msk = 0xc0
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR2_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR2_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR2_PullDown = 0x2
	// Position of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Pos = 0x8
	// Bit mask of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Msk = 0x300
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR3_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR3_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR3_PullDown = 0x2
	// Position of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Pos = 0xa
	// Bit mask of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Msk = 0xc00
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR4_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR4_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR4_PullDown = 0x2
	// Position of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Pos = 0xc
	// Bit mask of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Msk = 0x3000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR5_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR5_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR5_PullDown = 0x2
	// Position of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Pos = 0xe
	// Bit mask of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Msk = 0xc000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR6_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR6_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR6_PullDown = 0x2
	// Position of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Pos = 0x10
	// Bit mask of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Msk = 0x30000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR7_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR7_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR7_PullDown = 0x2
	// Position of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Pos = 0x12
	// Bit mask of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Msk = 0xc0000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR8_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR8_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR8_PullDown = 0x2
	// Position of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Pos = 0x14
	// Bit mask of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Msk = 0x300000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR9_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR9_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR9_PullDown = 0x2
	// Position of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Pos = 0x16
	// Bit mask of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Msk = 0xc00000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR10_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR10_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR10_PullDown = 0x2
	// Position of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Pos = 0x18
	// Bit mask of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Msk = 0x3000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR11_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR11_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR11_PullDown = 0x2
	// Position of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Pos = 0x1a
	// Bit mask of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Msk = 0xc000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR12_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR12_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR12_PullDown = 0x2
	// Position of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Pos = 0x1c
	// Bit mask of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Msk = 0x30000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR13_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR13_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR13_PullDown = 0x2
	// Position of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Pos = 0x1e
	// Bit mask of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Msk = 0xc0000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR14_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR14_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR14_PullDown = 0x2
	// Position of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Pos = 0x20
	// Bit mask of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Msk = 0x300000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR15_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR15_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR15_PullDown = 0x2

	// IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIO_IDR_IDR0_Pos = 0x1
	// Bit mask of IDR0 field.
	GPIO_IDR_IDR0_Msk = 0x2
	// Bit IDR0.
	GPIO_IDR_IDR0 = 0x2
	// Input is logic low
	GPIO_IDR_IDR0_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR0_High = 0x1
	// Position of IDR1 field.
	GPIO_IDR_IDR1_Pos = 0x2
	// Bit mask of IDR1 field.
	GPIO_IDR_IDR1_Msk = 0x4
	// Bit IDR1.
	GPIO_IDR_IDR1 = 0x4
	// Input is logic low
	GPIO_IDR_IDR1_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR1_High = 0x1
	// Position of IDR2 field.
	GPIO_IDR_IDR2_Pos = 0x3
	// Bit mask of IDR2 field.
	GPIO_IDR_IDR2_Msk = 0x8
	// Bit IDR2.
	GPIO_IDR_IDR2 = 0x8
	// Input is logic low
	GPIO_IDR_IDR2_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR2_High = 0x1
	// Position of IDR3 field.
	GPIO_IDR_IDR3_Pos = 0x4
	// Bit mask of IDR3 field.
	GPIO_IDR_IDR3_Msk = 0x10
	// Bit IDR3.
	GPIO_IDR_IDR3 = 0x10
	// Input is logic low
	GPIO_IDR_IDR3_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR3_High = 0x1
	// Position of IDR4 field.
	GPIO_IDR_IDR4_Pos = 0x5
	// Bit mask of IDR4 field.
	GPIO_IDR_IDR4_Msk = 0x20
	// Bit IDR4.
	GPIO_IDR_IDR4 = 0x20
	// Input is logic low
	GPIO_IDR_IDR4_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR4_High = 0x1
	// Position of IDR5 field.
	GPIO_IDR_IDR5_Pos = 0x6
	// Bit mask of IDR5 field.
	GPIO_IDR_IDR5_Msk = 0x40
	// Bit IDR5.
	GPIO_IDR_IDR5 = 0x40
	// Input is logic low
	GPIO_IDR_IDR5_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR5_High = 0x1
	// Position of IDR6 field.
	GPIO_IDR_IDR6_Pos = 0x7
	// Bit mask of IDR6 field.
	GPIO_IDR_IDR6_Msk = 0x80
	// Bit IDR6.
	GPIO_IDR_IDR6 = 0x80
	// Input is logic low
	GPIO_IDR_IDR6_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR6_High = 0x1
	// Position of IDR7 field.
	GPIO_IDR_IDR7_Pos = 0x8
	// Bit mask of IDR7 field.
	GPIO_IDR_IDR7_Msk = 0x100
	// Bit IDR7.
	GPIO_IDR_IDR7 = 0x100
	// Input is logic low
	GPIO_IDR_IDR7_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR7_High = 0x1
	// Position of IDR8 field.
	GPIO_IDR_IDR8_Pos = 0x9
	// Bit mask of IDR8 field.
	GPIO_IDR_IDR8_Msk = 0x200
	// Bit IDR8.
	GPIO_IDR_IDR8 = 0x200
	// Input is logic low
	GPIO_IDR_IDR8_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR8_High = 0x1
	// Position of IDR9 field.
	GPIO_IDR_IDR9_Pos = 0xa
	// Bit mask of IDR9 field.
	GPIO_IDR_IDR9_Msk = 0x400
	// Bit IDR9.
	GPIO_IDR_IDR9 = 0x400
	// Input is logic low
	GPIO_IDR_IDR9_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR9_High = 0x1
	// Position of IDR10 field.
	GPIO_IDR_IDR10_Pos = 0xb
	// Bit mask of IDR10 field.
	GPIO_IDR_IDR10_Msk = 0x800
	// Bit IDR10.
	GPIO_IDR_IDR10 = 0x800
	// Input is logic low
	GPIO_IDR_IDR10_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR10_High = 0x1
	// Position of IDR11 field.
	GPIO_IDR_IDR11_Pos = 0xc
	// Bit mask of IDR11 field.
	GPIO_IDR_IDR11_Msk = 0x1000
	// Bit IDR11.
	GPIO_IDR_IDR11 = 0x1000
	// Input is logic low
	GPIO_IDR_IDR11_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR11_High = 0x1
	// Position of IDR12 field.
	GPIO_IDR_IDR12_Pos = 0xd
	// Bit mask of IDR12 field.
	GPIO_IDR_IDR12_Msk = 0x2000
	// Bit IDR12.
	GPIO_IDR_IDR12 = 0x2000
	// Input is logic low
	GPIO_IDR_IDR12_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR12_High = 0x1
	// Position of IDR13 field.
	GPIO_IDR_IDR13_Pos = 0xe
	// Bit mask of IDR13 field.
	GPIO_IDR_IDR13_Msk = 0x4000
	// Bit IDR13.
	GPIO_IDR_IDR13 = 0x4000
	// Input is logic low
	GPIO_IDR_IDR13_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR13_High = 0x1
	// Position of IDR14 field.
	GPIO_IDR_IDR14_Pos = 0xf
	// Bit mask of IDR14 field.
	GPIO_IDR_IDR14_Msk = 0x8000
	// Bit IDR14.
	GPIO_IDR_IDR14 = 0x8000
	// Input is logic low
	GPIO_IDR_IDR14_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR14_High = 0x1
	// Position of IDR15 field.
	GPIO_IDR_IDR15_Pos = 0x10
	// Bit mask of IDR15 field.
	GPIO_IDR_IDR15_Msk = 0x10000
	// Bit IDR15.
	GPIO_IDR_IDR15 = 0x10000
	// Input is logic low
	GPIO_IDR_IDR15_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR15_High = 0x1

	// ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIO_ODR_ODR0_Pos = 0x1
	// Bit mask of ODR0 field.
	GPIO_ODR_ODR0_Msk = 0x2
	// Bit ODR0.
	GPIO_ODR_ODR0 = 0x2
	// Set output to logic low
	GPIO_ODR_ODR0_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR0_High = 0x1
	// Position of ODR1 field.
	GPIO_ODR_ODR1_Pos = 0x2
	// Bit mask of ODR1 field.
	GPIO_ODR_ODR1_Msk = 0x4
	// Bit ODR1.
	GPIO_ODR_ODR1 = 0x4
	// Set output to logic low
	GPIO_ODR_ODR1_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR1_High = 0x1
	// Position of ODR2 field.
	GPIO_ODR_ODR2_Pos = 0x3
	// Bit mask of ODR2 field.
	GPIO_ODR_ODR2_Msk = 0x8
	// Bit ODR2.
	GPIO_ODR_ODR2 = 0x8
	// Set output to logic low
	GPIO_ODR_ODR2_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR2_High = 0x1
	// Position of ODR3 field.
	GPIO_ODR_ODR3_Pos = 0x4
	// Bit mask of ODR3 field.
	GPIO_ODR_ODR3_Msk = 0x10
	// Bit ODR3.
	GPIO_ODR_ODR3 = 0x10
	// Set output to logic low
	GPIO_ODR_ODR3_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR3_High = 0x1
	// Position of ODR4 field.
	GPIO_ODR_ODR4_Pos = 0x5
	// Bit mask of ODR4 field.
	GPIO_ODR_ODR4_Msk = 0x20
	// Bit ODR4.
	GPIO_ODR_ODR4 = 0x20
	// Set output to logic low
	GPIO_ODR_ODR4_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR4_High = 0x1
	// Position of ODR5 field.
	GPIO_ODR_ODR5_Pos = 0x6
	// Bit mask of ODR5 field.
	GPIO_ODR_ODR5_Msk = 0x40
	// Bit ODR5.
	GPIO_ODR_ODR5 = 0x40
	// Set output to logic low
	GPIO_ODR_ODR5_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR5_High = 0x1
	// Position of ODR6 field.
	GPIO_ODR_ODR6_Pos = 0x7
	// Bit mask of ODR6 field.
	GPIO_ODR_ODR6_Msk = 0x80
	// Bit ODR6.
	GPIO_ODR_ODR6 = 0x80
	// Set output to logic low
	GPIO_ODR_ODR6_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR6_High = 0x1
	// Position of ODR7 field.
	GPIO_ODR_ODR7_Pos = 0x8
	// Bit mask of ODR7 field.
	GPIO_ODR_ODR7_Msk = 0x100
	// Bit ODR7.
	GPIO_ODR_ODR7 = 0x100
	// Set output to logic low
	GPIO_ODR_ODR7_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR7_High = 0x1
	// Position of ODR8 field.
	GPIO_ODR_ODR8_Pos = 0x9
	// Bit mask of ODR8 field.
	GPIO_ODR_ODR8_Msk = 0x200
	// Bit ODR8.
	GPIO_ODR_ODR8 = 0x200
	// Set output to logic low
	GPIO_ODR_ODR8_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR8_High = 0x1
	// Position of ODR9 field.
	GPIO_ODR_ODR9_Pos = 0xa
	// Bit mask of ODR9 field.
	GPIO_ODR_ODR9_Msk = 0x400
	// Bit ODR9.
	GPIO_ODR_ODR9 = 0x400
	// Set output to logic low
	GPIO_ODR_ODR9_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR9_High = 0x1
	// Position of ODR10 field.
	GPIO_ODR_ODR10_Pos = 0xb
	// Bit mask of ODR10 field.
	GPIO_ODR_ODR10_Msk = 0x800
	// Bit ODR10.
	GPIO_ODR_ODR10 = 0x800
	// Set output to logic low
	GPIO_ODR_ODR10_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR10_High = 0x1
	// Position of ODR11 field.
	GPIO_ODR_ODR11_Pos = 0xc
	// Bit mask of ODR11 field.
	GPIO_ODR_ODR11_Msk = 0x1000
	// Bit ODR11.
	GPIO_ODR_ODR11 = 0x1000
	// Set output to logic low
	GPIO_ODR_ODR11_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR11_High = 0x1
	// Position of ODR12 field.
	GPIO_ODR_ODR12_Pos = 0xd
	// Bit mask of ODR12 field.
	GPIO_ODR_ODR12_Msk = 0x2000
	// Bit ODR12.
	GPIO_ODR_ODR12 = 0x2000
	// Set output to logic low
	GPIO_ODR_ODR12_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR12_High = 0x1
	// Position of ODR13 field.
	GPIO_ODR_ODR13_Pos = 0xe
	// Bit mask of ODR13 field.
	GPIO_ODR_ODR13_Msk = 0x4000
	// Bit ODR13.
	GPIO_ODR_ODR13 = 0x4000
	// Set output to logic low
	GPIO_ODR_ODR13_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR13_High = 0x1
	// Position of ODR14 field.
	GPIO_ODR_ODR14_Pos = 0xf
	// Bit mask of ODR14 field.
	GPIO_ODR_ODR14_Msk = 0x8000
	// Bit ODR14.
	GPIO_ODR_ODR14 = 0x8000
	// Set output to logic low
	GPIO_ODR_ODR14_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR14_High = 0x1
	// Position of ODR15 field.
	GPIO_ODR_ODR15_Pos = 0x10
	// Bit mask of ODR15 field.
	GPIO_ODR_ODR15_Msk = 0x10000
	// Bit ODR15.
	GPIO_ODR_ODR15 = 0x10000
	// Set output to logic low
	GPIO_ODR_ODR15_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR15_High = 0x1

	// BSRR: GPIO port bit set/reset register
	// Position of BR0 field.
	GPIO_BSRR_BR0_Pos = 0x11
	// Bit mask of BR0 field.
	GPIO_BSRR_BR0_Msk = 0x20000
	// Bit BR0.
	GPIO_BSRR_BR0 = 0x20000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BSRR_BR1_Pos = 0x12
	// Bit mask of BR1 field.
	GPIO_BSRR_BR1_Msk = 0x40000
	// Bit BR1.
	GPIO_BSRR_BR1 = 0x40000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BSRR_BR2_Pos = 0x13
	// Bit mask of BR2 field.
	GPIO_BSRR_BR2_Msk = 0x80000
	// Bit BR2.
	GPIO_BSRR_BR2 = 0x80000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BSRR_BR3_Pos = 0x14
	// Bit mask of BR3 field.
	GPIO_BSRR_BR3_Msk = 0x100000
	// Bit BR3.
	GPIO_BSRR_BR3 = 0x100000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BSRR_BR4_Pos = 0x15
	// Bit mask of BR4 field.
	GPIO_BSRR_BR4_Msk = 0x200000
	// Bit BR4.
	GPIO_BSRR_BR4 = 0x200000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BSRR_BR5_Pos = 0x16
	// Bit mask of BR5 field.
	GPIO_BSRR_BR5_Msk = 0x400000
	// Bit BR5.
	GPIO_BSRR_BR5 = 0x400000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BSRR_BR6_Pos = 0x17
	// Bit mask of BR6 field.
	GPIO_BSRR_BR6_Msk = 0x800000
	// Bit BR6.
	GPIO_BSRR_BR6 = 0x800000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BSRR_BR7_Pos = 0x18
	// Bit mask of BR7 field.
	GPIO_BSRR_BR7_Msk = 0x1000000
	// Bit BR7.
	GPIO_BSRR_BR7 = 0x1000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BSRR_BR8_Pos = 0x19
	// Bit mask of BR8 field.
	GPIO_BSRR_BR8_Msk = 0x2000000
	// Bit BR8.
	GPIO_BSRR_BR8 = 0x2000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BSRR_BR9_Pos = 0x1a
	// Bit mask of BR9 field.
	GPIO_BSRR_BR9_Msk = 0x4000000
	// Bit BR9.
	GPIO_BSRR_BR9 = 0x4000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BSRR_BR10_Pos = 0x1b
	// Bit mask of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x8000000
	// Bit BR10.
	GPIO_BSRR_BR10 = 0x8000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BSRR_BR11_Pos = 0x1c
	// Bit mask of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x10000000
	// Bit BR11.
	GPIO_BSRR_BR11 = 0x10000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BSRR_BR12_Pos = 0x1d
	// Bit mask of BR12 field.
	GPIO_BSRR_BR12_Msk = 0x20000000
	// Bit BR12.
	GPIO_BSRR_BR12 = 0x20000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BSRR_BR13_Pos = 0x1e
	// Bit mask of BR13 field.
	GPIO_BSRR_BR13_Msk = 0x40000000
	// Bit BR13.
	GPIO_BSRR_BR13 = 0x40000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BSRR_BR14_Pos = 0x1f
	// Bit mask of BR14 field.
	GPIO_BSRR_BR14_Msk = 0x80000000
	// Bit BR14.
	GPIO_BSRR_BR14 = 0x80000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BSRR_BR15_Pos = 0x20
	// Bit mask of BR15 field.
	GPIO_BSRR_BR15_Msk = 0x100000000
	// Bit BR15.
	GPIO_BSRR_BR15 = 0x100000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR15_Reset = 0x1
	// Position of BS0 field.
	GPIO_BSRR_BS0_Pos = 0x1
	// Bit mask of BS0 field.
	GPIO_BSRR_BS0_Msk = 0x2
	// Bit BS0.
	GPIO_BSRR_BS0 = 0x2
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS0_Set = 0x1
	// Position of BS1 field.
	GPIO_BSRR_BS1_Pos = 0x2
	// Bit mask of BS1 field.
	GPIO_BSRR_BS1_Msk = 0x4
	// Bit BS1.
	GPIO_BSRR_BS1 = 0x4
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS1_Set = 0x1
	// Position of BS2 field.
	GPIO_BSRR_BS2_Pos = 0x3
	// Bit mask of BS2 field.
	GPIO_BSRR_BS2_Msk = 0x8
	// Bit BS2.
	GPIO_BSRR_BS2 = 0x8
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS2_Set = 0x1
	// Position of BS3 field.
	GPIO_BSRR_BS3_Pos = 0x4
	// Bit mask of BS3 field.
	GPIO_BSRR_BS3_Msk = 0x10
	// Bit BS3.
	GPIO_BSRR_BS3 = 0x10
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS3_Set = 0x1
	// Position of BS4 field.
	GPIO_BSRR_BS4_Pos = 0x5
	// Bit mask of BS4 field.
	GPIO_BSRR_BS4_Msk = 0x20
	// Bit BS4.
	GPIO_BSRR_BS4 = 0x20
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS4_Set = 0x1
	// Position of BS5 field.
	GPIO_BSRR_BS5_Pos = 0x6
	// Bit mask of BS5 field.
	GPIO_BSRR_BS5_Msk = 0x40
	// Bit BS5.
	GPIO_BSRR_BS5 = 0x40
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS5_Set = 0x1
	// Position of BS6 field.
	GPIO_BSRR_BS6_Pos = 0x7
	// Bit mask of BS6 field.
	GPIO_BSRR_BS6_Msk = 0x80
	// Bit BS6.
	GPIO_BSRR_BS6 = 0x80
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS6_Set = 0x1
	// Position of BS7 field.
	GPIO_BSRR_BS7_Pos = 0x8
	// Bit mask of BS7 field.
	GPIO_BSRR_BS7_Msk = 0x100
	// Bit BS7.
	GPIO_BSRR_BS7 = 0x100
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS7_Set = 0x1
	// Position of BS8 field.
	GPIO_BSRR_BS8_Pos = 0x9
	// Bit mask of BS8 field.
	GPIO_BSRR_BS8_Msk = 0x200
	// Bit BS8.
	GPIO_BSRR_BS8 = 0x200
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS8_Set = 0x1
	// Position of BS9 field.
	GPIO_BSRR_BS9_Pos = 0xa
	// Bit mask of BS9 field.
	GPIO_BSRR_BS9_Msk = 0x400
	// Bit BS9.
	GPIO_BSRR_BS9 = 0x400
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS9_Set = 0x1
	// Position of BS10 field.
	GPIO_BSRR_BS10_Pos = 0xb
	// Bit mask of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x800
	// Bit BS10.
	GPIO_BSRR_BS10 = 0x800
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS10_Set = 0x1
	// Position of BS11 field.
	GPIO_BSRR_BS11_Pos = 0xc
	// Bit mask of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x1000
	// Bit BS11.
	GPIO_BSRR_BS11 = 0x1000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS11_Set = 0x1
	// Position of BS12 field.
	GPIO_BSRR_BS12_Pos = 0xd
	// Bit mask of BS12 field.
	GPIO_BSRR_BS12_Msk = 0x2000
	// Bit BS12.
	GPIO_BSRR_BS12 = 0x2000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS12_Set = 0x1
	// Position of BS13 field.
	GPIO_BSRR_BS13_Pos = 0xe
	// Bit mask of BS13 field.
	GPIO_BSRR_BS13_Msk = 0x4000
	// Bit BS13.
	GPIO_BSRR_BS13 = 0x4000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS13_Set = 0x1
	// Position of BS14 field.
	GPIO_BSRR_BS14_Pos = 0xf
	// Bit mask of BS14 field.
	GPIO_BSRR_BS14_Msk = 0x8000
	// Bit BS14.
	GPIO_BSRR_BS14 = 0x8000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS14_Set = 0x1
	// Position of BS15 field.
	GPIO_BSRR_BS15_Pos = 0x10
	// Bit mask of BS15 field.
	GPIO_BSRR_BS15_Msk = 0x10000
	// Bit BS15.
	GPIO_BSRR_BS15 = 0x10000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS15_Set = 0x1

	// LCKR: GPIO port configuration lock register
	// Position of LCKK field.
	GPIO_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIO_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIO_LCKR_LCKK = 0x10000
	// Port configuration lock key not active
	GPIO_LCKR_LCKK_NotActive = 0x0
	// Port configuration lock key active
	GPIO_LCKR_LCKK_Active = 0x1
	// Position of LCK0 field.
	GPIO_LCKR_LCK0_Pos = 0x1
	// Bit mask of LCK0 field.
	GPIO_LCKR_LCK0_Msk = 0x2
	// Bit LCK0.
	GPIO_LCKR_LCK0 = 0x2
	// Port configuration not locked
	GPIO_LCKR_LCK0_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK0_Locked = 0x1
	// Position of LCK1 field.
	GPIO_LCKR_LCK1_Pos = 0x2
	// Bit mask of LCK1 field.
	GPIO_LCKR_LCK1_Msk = 0x4
	// Bit LCK1.
	GPIO_LCKR_LCK1 = 0x4
	// Port configuration not locked
	GPIO_LCKR_LCK1_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK1_Locked = 0x1
	// Position of LCK2 field.
	GPIO_LCKR_LCK2_Pos = 0x3
	// Bit mask of LCK2 field.
	GPIO_LCKR_LCK2_Msk = 0x8
	// Bit LCK2.
	GPIO_LCKR_LCK2 = 0x8
	// Port configuration not locked
	GPIO_LCKR_LCK2_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK2_Locked = 0x1
	// Position of LCK3 field.
	GPIO_LCKR_LCK3_Pos = 0x4
	// Bit mask of LCK3 field.
	GPIO_LCKR_LCK3_Msk = 0x10
	// Bit LCK3.
	GPIO_LCKR_LCK3 = 0x10
	// Port configuration not locked
	GPIO_LCKR_LCK3_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK3_Locked = 0x1
	// Position of LCK4 field.
	GPIO_LCKR_LCK4_Pos = 0x5
	// Bit mask of LCK4 field.
	GPIO_LCKR_LCK4_Msk = 0x20
	// Bit LCK4.
	GPIO_LCKR_LCK4 = 0x20
	// Port configuration not locked
	GPIO_LCKR_LCK4_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK4_Locked = 0x1
	// Position of LCK5 field.
	GPIO_LCKR_LCK5_Pos = 0x6
	// Bit mask of LCK5 field.
	GPIO_LCKR_LCK5_Msk = 0x40
	// Bit LCK5.
	GPIO_LCKR_LCK5 = 0x40
	// Port configuration not locked
	GPIO_LCKR_LCK5_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK5_Locked = 0x1
	// Position of LCK6 field.
	GPIO_LCKR_LCK6_Pos = 0x7
	// Bit mask of LCK6 field.
	GPIO_LCKR_LCK6_Msk = 0x80
	// Bit LCK6.
	GPIO_LCKR_LCK6 = 0x80
	// Port configuration not locked
	GPIO_LCKR_LCK6_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK6_Locked = 0x1
	// Position of LCK7 field.
	GPIO_LCKR_LCK7_Pos = 0x8
	// Bit mask of LCK7 field.
	GPIO_LCKR_LCK7_Msk = 0x100
	// Bit LCK7.
	GPIO_LCKR_LCK7 = 0x100
	// Port configuration not locked
	GPIO_LCKR_LCK7_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK7_Locked = 0x1
	// Position of LCK8 field.
	GPIO_LCKR_LCK8_Pos = 0x9
	// Bit mask of LCK8 field.
	GPIO_LCKR_LCK8_Msk = 0x200
	// Bit LCK8.
	GPIO_LCKR_LCK8 = 0x200
	// Port configuration not locked
	GPIO_LCKR_LCK8_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK8_Locked = 0x1
	// Position of LCK9 field.
	GPIO_LCKR_LCK9_Pos = 0xa
	// Bit mask of LCK9 field.
	GPIO_LCKR_LCK9_Msk = 0x400
	// Bit LCK9.
	GPIO_LCKR_LCK9 = 0x400
	// Port configuration not locked
	GPIO_LCKR_LCK9_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK9_Locked = 0x1
	// Position of LCK10 field.
	GPIO_LCKR_LCK10_Pos = 0xb
	// Bit mask of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x800
	// Bit LCK10.
	GPIO_LCKR_LCK10 = 0x800
	// Port configuration not locked
	GPIO_LCKR_LCK10_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK10_Locked = 0x1
	// Position of LCK11 field.
	GPIO_LCKR_LCK11_Pos = 0xc
	// Bit mask of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x1000
	// Bit LCK11.
	GPIO_LCKR_LCK11 = 0x1000
	// Port configuration not locked
	GPIO_LCKR_LCK11_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK11_Locked = 0x1
	// Position of LCK12 field.
	GPIO_LCKR_LCK12_Pos = 0xd
	// Bit mask of LCK12 field.
	GPIO_LCKR_LCK12_Msk = 0x2000
	// Bit LCK12.
	GPIO_LCKR_LCK12 = 0x2000
	// Port configuration not locked
	GPIO_LCKR_LCK12_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK12_Locked = 0x1
	// Position of LCK13 field.
	GPIO_LCKR_LCK13_Pos = 0xe
	// Bit mask of LCK13 field.
	GPIO_LCKR_LCK13_Msk = 0x4000
	// Bit LCK13.
	GPIO_LCKR_LCK13 = 0x4000
	// Port configuration not locked
	GPIO_LCKR_LCK13_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK13_Locked = 0x1
	// Position of LCK14 field.
	GPIO_LCKR_LCK14_Pos = 0xf
	// Bit mask of LCK14 field.
	GPIO_LCKR_LCK14_Msk = 0x8000
	// Bit LCK14.
	GPIO_LCKR_LCK14 = 0x8000
	// Port configuration not locked
	GPIO_LCKR_LCK14_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK14_Locked = 0x1
	// Position of LCK15 field.
	GPIO_LCKR_LCK15_Pos = 0x10
	// Bit mask of LCK15 field.
	GPIO_LCKR_LCK15_Msk = 0x10000
	// Bit LCK15.
	GPIO_LCKR_LCK15 = 0x10000
	// Port configuration not locked
	GPIO_LCKR_LCK15_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK15_Locked = 0x1

	// AFRL: GPIO alternate function low register
	// Position of AFREL0 field.
	GPIO_AFRL_AFREL0_Pos = 0x4
	// Bit mask of AFREL0 field.
	GPIO_AFRL_AFREL0_Msk = 0xf0
	// AF0
	GPIO_AFRL_AFREL0_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL0_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL0_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL0_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL0_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL0_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL0_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL0_AF7 = 0x7
	// Position of AFREL1 field.
	GPIO_AFRL_AFREL1_Pos = 0x8
	// Bit mask of AFREL1 field.
	GPIO_AFRL_AFREL1_Msk = 0xf00
	// AF0
	GPIO_AFRL_AFREL1_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL1_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL1_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL1_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL1_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL1_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL1_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL1_AF7 = 0x7
	// Position of AFREL2 field.
	GPIO_AFRL_AFREL2_Pos = 0xc
	// Bit mask of AFREL2 field.
	GPIO_AFRL_AFREL2_Msk = 0xf000
	// AF0
	GPIO_AFRL_AFREL2_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL2_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL2_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL2_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL2_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL2_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL2_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL2_AF7 = 0x7
	// Position of AFREL3 field.
	GPIO_AFRL_AFREL3_Pos = 0x10
	// Bit mask of AFREL3 field.
	GPIO_AFRL_AFREL3_Msk = 0xf0000
	// AF0
	GPIO_AFRL_AFREL3_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL3_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL3_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL3_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL3_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL3_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL3_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL3_AF7 = 0x7
	// Position of AFREL4 field.
	GPIO_AFRL_AFREL4_Pos = 0x14
	// Bit mask of AFREL4 field.
	GPIO_AFRL_AFREL4_Msk = 0xf00000
	// AF0
	GPIO_AFRL_AFREL4_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL4_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL4_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL4_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL4_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL4_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL4_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL4_AF7 = 0x7
	// Position of AFREL5 field.
	GPIO_AFRL_AFREL5_Pos = 0x18
	// Bit mask of AFREL5 field.
	GPIO_AFRL_AFREL5_Msk = 0xf000000
	// AF0
	GPIO_AFRL_AFREL5_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL5_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL5_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL5_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL5_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL5_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL5_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL5_AF7 = 0x7
	// Position of AFREL6 field.
	GPIO_AFRL_AFREL6_Pos = 0x1c
	// Bit mask of AFREL6 field.
	GPIO_AFRL_AFREL6_Msk = 0xf0000000
	// AF0
	GPIO_AFRL_AFREL6_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL6_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL6_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL6_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL6_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL6_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL6_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL6_AF7 = 0x7
	// Position of AFREL7 field.
	GPIO_AFRL_AFREL7_Pos = 0x20
	// Bit mask of AFREL7 field.
	GPIO_AFRL_AFREL7_Msk = 0xf00000000
	// AF0
	GPIO_AFRL_AFREL7_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL7_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL7_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL7_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL7_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL7_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL7_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL7_AF7 = 0x7

	// AFRH: GPIO alternate function high register
	// Position of AFREL8 field.
	GPIO_AFRH_AFREL8_Pos = 0x4
	// Bit mask of AFREL8 field.
	GPIO_AFRH_AFREL8_Msk = 0xf0
	// AF0
	GPIO_AFRH_AFREL8_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL8_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL8_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL8_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL8_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL8_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL8_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL8_AF7 = 0x7
	// Position of AFREL9 field.
	GPIO_AFRH_AFREL9_Pos = 0x8
	// Bit mask of AFREL9 field.
	GPIO_AFRH_AFREL9_Msk = 0xf00
	// AF0
	GPIO_AFRH_AFREL9_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL9_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL9_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL9_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL9_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL9_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL9_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL9_AF7 = 0x7
	// Position of AFREL10 field.
	GPIO_AFRH_AFREL10_Pos = 0xc
	// Bit mask of AFREL10 field.
	GPIO_AFRH_AFREL10_Msk = 0xf000
	// AF0
	GPIO_AFRH_AFREL10_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL10_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL10_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL10_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL10_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL10_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL10_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL10_AF7 = 0x7
	// Position of AFREL11 field.
	GPIO_AFRH_AFREL11_Pos = 0x10
	// Bit mask of AFREL11 field.
	GPIO_AFRH_AFREL11_Msk = 0xf0000
	// AF0
	GPIO_AFRH_AFREL11_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL11_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL11_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL11_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL11_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL11_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL11_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL11_AF7 = 0x7
	// Position of AFREL12 field.
	GPIO_AFRH_AFREL12_Pos = 0x14
	// Bit mask of AFREL12 field.
	GPIO_AFRH_AFREL12_Msk = 0xf00000
	// AF0
	GPIO_AFRH_AFREL12_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL12_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL12_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL12_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL12_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL12_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL12_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL12_AF7 = 0x7
	// Position of AFREL13 field.
	GPIO_AFRH_AFREL13_Pos = 0x18
	// Bit mask of AFREL13 field.
	GPIO_AFRH_AFREL13_Msk = 0xf000000
	// AF0
	GPIO_AFRH_AFREL13_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL13_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL13_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL13_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL13_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL13_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL13_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL13_AF7 = 0x7
	// Position of AFREL14 field.
	GPIO_AFRH_AFREL14_Pos = 0x1c
	// Bit mask of AFREL14 field.
	GPIO_AFRH_AFREL14_Msk = 0xf0000000
	// AF0
	GPIO_AFRH_AFREL14_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL14_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL14_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL14_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL14_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL14_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL14_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL14_AF7 = 0x7
	// Position of AFREL15 field.
	GPIO_AFRH_AFREL15_Pos = 0x20
	// Bit mask of AFREL15 field.
	GPIO_AFRH_AFREL15_Msk = 0xf00000000
	// AF0
	GPIO_AFRH_AFREL15_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL15_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL15_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL15_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL15_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL15_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL15_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL15_AF7 = 0x7

	// BRR: port bit reset register
	// Position of BR0 field.
	GPIO_BRR_BR0_Pos = 0x1
	// Bit mask of BR0 field.
	GPIO_BRR_BR0_Msk = 0x2
	// Bit BR0.
	GPIO_BRR_BR0 = 0x2
	// No action on the corresponding ODx bit
	GPIO_BRR_BR0_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BRR_BR1_Pos = 0x2
	// Bit mask of BR1 field.
	GPIO_BRR_BR1_Msk = 0x4
	// Bit BR1.
	GPIO_BRR_BR1 = 0x4
	// No action on the corresponding ODx bit
	GPIO_BRR_BR1_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BRR_BR2_Pos = 0x3
	// Bit mask of BR2 field.
	GPIO_BRR_BR2_Msk = 0x8
	// Bit BR2.
	GPIO_BRR_BR2 = 0x8
	// No action on the corresponding ODx bit
	GPIO_BRR_BR2_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BRR_BR3_Pos = 0x4
	// Bit mask of BR3 field.
	GPIO_BRR_BR3_Msk = 0x10
	// Bit BR3.
	GPIO_BRR_BR3 = 0x10
	// No action on the corresponding ODx bit
	GPIO_BRR_BR3_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BRR_BR4_Pos = 0x5
	// Bit mask of BR4 field.
	GPIO_BRR_BR4_Msk = 0x20
	// Bit BR4.
	GPIO_BRR_BR4 = 0x20
	// No action on the corresponding ODx bit
	GPIO_BRR_BR4_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BRR_BR5_Pos = 0x6
	// Bit mask of BR5 field.
	GPIO_BRR_BR5_Msk = 0x40
	// Bit BR5.
	GPIO_BRR_BR5 = 0x40
	// No action on the corresponding ODx bit
	GPIO_BRR_BR5_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BRR_BR6_Pos = 0x7
	// Bit mask of BR6 field.
	GPIO_BRR_BR6_Msk = 0x80
	// Bit BR6.
	GPIO_BRR_BR6 = 0x80
	// No action on the corresponding ODx bit
	GPIO_BRR_BR6_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BRR_BR7_Pos = 0x8
	// Bit mask of BR7 field.
	GPIO_BRR_BR7_Msk = 0x100
	// Bit BR7.
	GPIO_BRR_BR7 = 0x100
	// No action on the corresponding ODx bit
	GPIO_BRR_BR7_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BRR_BR8_Pos = 0x9
	// Bit mask of BR8 field.
	GPIO_BRR_BR8_Msk = 0x200
	// Bit BR8.
	GPIO_BRR_BR8 = 0x200
	// No action on the corresponding ODx bit
	GPIO_BRR_BR8_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BRR_BR9_Pos = 0xa
	// Bit mask of BR9 field.
	GPIO_BRR_BR9_Msk = 0x400
	// Bit BR9.
	GPIO_BRR_BR9 = 0x400
	// No action on the corresponding ODx bit
	GPIO_BRR_BR9_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BRR_BR10_Pos = 0xb
	// Bit mask of BR10 field.
	GPIO_BRR_BR10_Msk = 0x800
	// Bit BR10.
	GPIO_BRR_BR10 = 0x800
	// No action on the corresponding ODx bit
	GPIO_BRR_BR10_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BRR_BR11_Pos = 0xc
	// Bit mask of BR11 field.
	GPIO_BRR_BR11_Msk = 0x1000
	// Bit BR11.
	GPIO_BRR_BR11 = 0x1000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR11_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BRR_BR12_Pos = 0xd
	// Bit mask of BR12 field.
	GPIO_BRR_BR12_Msk = 0x2000
	// Bit BR12.
	GPIO_BRR_BR12 = 0x2000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR12_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BRR_BR13_Pos = 0xe
	// Bit mask of BR13 field.
	GPIO_BRR_BR13_Msk = 0x4000
	// Bit BR13.
	GPIO_BRR_BR13 = 0x4000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR13_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BRR_BR14_Pos = 0xf
	// Bit mask of BR14 field.
	GPIO_BRR_BR14_Msk = 0x8000
	// Bit BR14.
	GPIO_BRR_BR14 = 0x8000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR14_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BRR_BR15_Pos = 0x10
	// Bit mask of BR15 field.
	GPIO_BRR_BR15_Msk = 0x10000
	// Bit BR15.
	GPIO_BRR_BR15 = 0x10000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR15_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR15_Reset = 0x1
)

// Constants for I2C1: Inter-integrated circuit
const (
	// CR1: Control register 1
	// Position of PE field.
	I2C_CR1_PE_Pos = 0x0
	// Bit mask of PE field.
	I2C_CR1_PE_Msk = 0x1
	// Bit PE.
	I2C_CR1_PE = 0x1
	// Peripheral disabled
	I2C_CR1_PE_Disabled = 0x0
	// Peripheral enabled
	I2C_CR1_PE_Enabled = 0x1
	// Position of TXIE field.
	I2C_CR1_TXIE_Pos = 0x1
	// Bit mask of TXIE field.
	I2C_CR1_TXIE_Msk = 0x2
	// Bit TXIE.
	I2C_CR1_TXIE = 0x2
	// Transmit (TXIS) interrupt disabled
	I2C_CR1_TXIE_Disabled = 0x0
	// Transmit (TXIS) interrupt enabled
	I2C_CR1_TXIE_Enabled = 0x1
	// Position of RXIE field.
	I2C_CR1_RXIE_Pos = 0x2
	// Bit mask of RXIE field.
	I2C_CR1_RXIE_Msk = 0x4
	// Bit RXIE.
	I2C_CR1_RXIE = 0x4
	// Receive (RXNE) interrupt disabled
	I2C_CR1_RXIE_Disabled = 0x0
	// Receive (RXNE) interrupt enabled
	I2C_CR1_RXIE_Enabled = 0x1
	// Position of ADDRIE field.
	I2C_CR1_ADDRIE_Pos = 0x3
	// Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE_Msk = 0x8
	// Bit ADDRIE.
	I2C_CR1_ADDRIE = 0x8
	// Address match (ADDR) interrupts disabled
	I2C_CR1_ADDRIE_Disabled = 0x0
	// Address match (ADDR) interrupts enabled
	I2C_CR1_ADDRIE_Enabled = 0x1
	// Position of NACKIE field.
	I2C_CR1_NACKIE_Pos = 0x4
	// Bit mask of NACKIE field.
	I2C_CR1_NACKIE_Msk = 0x10
	// Bit NACKIE.
	I2C_CR1_NACKIE = 0x10
	// Not acknowledge (NACKF) received interrupts disabled
	I2C_CR1_NACKIE_Disabled = 0x0
	// Not acknowledge (NACKF) received interrupts enabled
	I2C_CR1_NACKIE_Enabled = 0x1
	// Position of STOPIE field.
	I2C_CR1_STOPIE_Pos = 0x5
	// Bit mask of STOPIE field.
	I2C_CR1_STOPIE_Msk = 0x20
	// Bit STOPIE.
	I2C_CR1_STOPIE = 0x20
	// Stop detection (STOPF) interrupt disabled
	I2C_CR1_STOPIE_Disabled = 0x0
	// Stop detection (STOPF) interrupt enabled
	I2C_CR1_STOPIE_Enabled = 0x1
	// Position of TCIE field.
	I2C_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	I2C_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	I2C_CR1_TCIE = 0x40
	// Transfer Complete interrupt disabled
	I2C_CR1_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	I2C_CR1_TCIE_Enabled = 0x1
	// Position of ERRIE field.
	I2C_CR1_ERRIE_Pos = 0x7
	// Bit mask of ERRIE field.
	I2C_CR1_ERRIE_Msk = 0x80
	// Bit ERRIE.
	I2C_CR1_ERRIE = 0x80
	// Error detection interrupts disabled
	I2C_CR1_ERRIE_Disabled = 0x0
	// Error detection interrupts enabled
	I2C_CR1_ERRIE_Enabled = 0x1
	// Position of DNF field.
	I2C_CR1_DNF_Pos = 0x8
	// Bit mask of DNF field.
	I2C_CR1_DNF_Msk = 0xf00
	// Digital filter disabled
	I2C_CR1_DNF_NoFilter = 0x0
	// Digital filter enabled and filtering capability up to 1 tI2CCLK
	I2C_CR1_DNF_Filter1 = 0x1
	// Digital filter enabled and filtering capability up to 2 tI2CCLK
	I2C_CR1_DNF_Filter2 = 0x2
	// Digital filter enabled and filtering capability up to 3 tI2CCLK
	I2C_CR1_DNF_Filter3 = 0x3
	// Digital filter enabled and filtering capability up to 4 tI2CCLK
	I2C_CR1_DNF_Filter4 = 0x4
	// Digital filter enabled and filtering capability up to 5 tI2CCLK
	I2C_CR1_DNF_Filter5 = 0x5
	// Digital filter enabled and filtering capability up to 6 tI2CCLK
	I2C_CR1_DNF_Filter6 = 0x6
	// Digital filter enabled and filtering capability up to 7 tI2CCLK
	I2C_CR1_DNF_Filter7 = 0x7
	// Digital filter enabled and filtering capability up to 8 tI2CCLK
	I2C_CR1_DNF_Filter8 = 0x8
	// Digital filter enabled and filtering capability up to 9 tI2CCLK
	I2C_CR1_DNF_Filter9 = 0x9
	// Digital filter enabled and filtering capability up to 10 tI2CCLK
	I2C_CR1_DNF_Filter10 = 0xa
	// Digital filter enabled and filtering capability up to 11 tI2CCLK
	I2C_CR1_DNF_Filter11 = 0xb
	// Digital filter enabled and filtering capability up to 12 tI2CCLK
	I2C_CR1_DNF_Filter12 = 0xc
	// Digital filter enabled and filtering capability up to 13 tI2CCLK
	I2C_CR1_DNF_Filter13 = 0xd
	// Digital filter enabled and filtering capability up to 14 tI2CCLK
	I2C_CR1_DNF_Filter14 = 0xe
	// Digital filter enabled and filtering capability up to 15 tI2CCLK
	I2C_CR1_DNF_Filter15 = 0xf
	// Position of ANFOFF field.
	I2C_CR1_ANFOFF_Pos = 0xc
	// Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF_Msk = 0x1000
	// Bit ANFOFF.
	I2C_CR1_ANFOFF = 0x1000
	// Analog noise filter enabled
	I2C_CR1_ANFOFF_Enabled = 0x0
	// Analog noise filter disabled
	I2C_CR1_ANFOFF_Disabled = 0x1
	// Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Pos = 0xe
	// Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk = 0x4000
	// Bit TXDMAEN.
	I2C_CR1_TXDMAEN = 0x4000
	// DMA mode disabled for transmission
	I2C_CR1_TXDMAEN_Disabled = 0x0
	// DMA mode enabled for transmission
	I2C_CR1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Pos = 0xf
	// Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk = 0x8000
	// Bit RXDMAEN.
	I2C_CR1_RXDMAEN = 0x8000
	// DMA mode disabled for reception
	I2C_CR1_RXDMAEN_Disabled = 0x0
	// DMA mode enabled for reception
	I2C_CR1_RXDMAEN_Enabled = 0x1
	// Position of SBC field.
	I2C_CR1_SBC_Pos = 0x10
	// Bit mask of SBC field.
	I2C_CR1_SBC_Msk = 0x10000
	// Bit SBC.
	I2C_CR1_SBC = 0x10000
	// Slave byte control disabled
	I2C_CR1_SBC_Disabled = 0x0
	// Slave byte control enabled
	I2C_CR1_SBC_Enabled = 0x1
	// Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Pos = 0x11
	// Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000
	// Bit NOSTRETCH.
	I2C_CR1_NOSTRETCH = 0x20000
	// Clock stretching enabled
	I2C_CR1_NOSTRETCH_Enabled = 0x0
	// Clock stretching disabled
	I2C_CR1_NOSTRETCH_Disabled = 0x1
	// Position of WUPEN field.
	I2C_CR1_WUPEN_Pos = 0x12
	// Bit mask of WUPEN field.
	I2C_CR1_WUPEN_Msk = 0x40000
	// Bit WUPEN.
	I2C_CR1_WUPEN = 0x40000
	// Wakeup from Stop mode disabled
	I2C_CR1_WUPEN_Disabled = 0x0
	// Wakeup from Stop mode enabled
	I2C_CR1_WUPEN_Enabled = 0x1
	// Position of GCEN field.
	I2C_CR1_GCEN_Pos = 0x13
	// Bit mask of GCEN field.
	I2C_CR1_GCEN_Msk = 0x80000
	// Bit GCEN.
	I2C_CR1_GCEN = 0x80000
	// General call disabled. Address 0b00000000 is NACKed
	I2C_CR1_GCEN_Disabled = 0x0
	// General call enabled. Address 0b00000000 is ACKed
	I2C_CR1_GCEN_Enabled = 0x1
	// Position of SMBHEN field.
	I2C_CR1_SMBHEN_Pos = 0x14
	// Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN_Msk = 0x100000
	// Bit SMBHEN.
	I2C_CR1_SMBHEN = 0x100000
	// Host address disabled. Address 0b0001000x is NACKed
	I2C_CR1_SMBHEN_Disabled = 0x0
	// Host address enabled. Address 0b0001000x is ACKed
	I2C_CR1_SMBHEN_Enabled = 0x1
	// Position of SMBDEN field.
	I2C_CR1_SMBDEN_Pos = 0x15
	// Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN_Msk = 0x200000
	// Bit SMBDEN.
	I2C_CR1_SMBDEN = 0x200000
	// Device default address disabled. Address 0b1100001x is NACKed
	I2C_CR1_SMBDEN_Disabled = 0x0
	// Device default address enabled. Address 0b1100001x is ACKed
	I2C_CR1_SMBDEN_Enabled = 0x1
	// Position of ALERTEN field.
	I2C_CR1_ALERTEN_Pos = 0x16
	// Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN_Msk = 0x400000
	// Bit ALERTEN.
	I2C_CR1_ALERTEN = 0x400000
	// In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
	I2C_CR1_ALERTEN_Disabled = 0x0
	// In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
	I2C_CR1_ALERTEN_Enabled = 0x1
	// Position of PECEN field.
	I2C_CR1_PECEN_Pos = 0x17
	// Bit mask of PECEN field.
	I2C_CR1_PECEN_Msk = 0x800000
	// Bit PECEN.
	I2C_CR1_PECEN = 0x800000
	// PEC calculation disabled
	I2C_CR1_PECEN_Disabled = 0x0
	// PEC calculation enabled
	I2C_CR1_PECEN_Enabled = 0x1

	// CR2: Control register 2
	// Position of SADD field.
	I2C_CR2_SADD_Pos = 0x0
	// Bit mask of SADD field.
	I2C_CR2_SADD_Msk = 0x3ff
	// Position of RD_WRN field.
	I2C_CR2_RD_WRN_Pos = 0xa
	// Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN_Msk = 0x400
	// Bit RD_WRN.
	I2C_CR2_RD_WRN = 0x400
	// Master requests a write transfer
	I2C_CR2_RD_WRN_Write = 0x0
	// Master requests a read transfer
	I2C_CR2_RD_WRN_Read = 0x1
	// Position of ADD10 field.
	I2C_CR2_ADD10_Pos = 0xb
	// Bit mask of ADD10 field.
	I2C_CR2_ADD10_Msk = 0x800
	// Bit ADD10.
	I2C_CR2_ADD10 = 0x800
	// The master operates in 7-bit addressing mode
	I2C_CR2_ADD10_Bit7 = 0x0
	// The master operates in 10-bit addressing mode
	I2C_CR2_ADD10_Bit10 = 0x1
	// Position of HEAD10R field.
	I2C_CR2_HEAD10R_Pos = 0xc
	// Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000
	// Bit HEAD10R.
	I2C_CR2_HEAD10R = 0x1000
	// The master sends the complete 10 bit slave address read sequence
	I2C_CR2_HEAD10R_Complete = 0x0
	// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
	I2C_CR2_HEAD10R_Partial = 0x1
	// Position of START field.
	I2C_CR2_START_Pos = 0xd
	// Bit mask of START field.
	I2C_CR2_START_Msk = 0x2000
	// Bit START.
	I2C_CR2_START = 0x2000
	// No Start generation
	I2C_CR2_START_NoStart = 0x0
	// Restart/Start generation
	I2C_CR2_START_Start = 0x1
	// Position of STOP field.
	I2C_CR2_STOP_Pos = 0xe
	// Bit mask of STOP field.
	I2C_CR2_STOP_Msk = 0x4000
	// Bit STOP.
	I2C_CR2_STOP = 0x4000
	// No Stop generation
	I2C_CR2_STOP_NoStop = 0x0
	// Stop generation after current byte transfer
	I2C_CR2_STOP_Stop = 0x1
	// Position of NACK field.
	I2C_CR2_NACK_Pos = 0xf
	// Bit mask of NACK field.
	I2C_CR2_NACK_Msk = 0x8000
	// Bit NACK.
	I2C_CR2_NACK = 0x8000
	// an ACK is sent after current received byte
	I2C_CR2_NACK_Ack = 0x0
	// a NACK is sent after current received byte
	I2C_CR2_NACK_Nack = 0x1
	// Position of NBYTES field.
	I2C_CR2_NBYTES_Pos = 0x10
	// Bit mask of NBYTES field.
	I2C_CR2_NBYTES_Msk = 0xff0000
	// Position of RELOAD field.
	I2C_CR2_RELOAD_Pos = 0x18
	// Bit mask of RELOAD field.
	I2C_CR2_RELOAD_Msk = 0x1000000
	// Bit RELOAD.
	I2C_CR2_RELOAD = 0x1000000
	// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
	I2C_CR2_RELOAD_Completed = 0x0
	// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
	I2C_CR2_RELOAD_NotCompleted = 0x1
	// Position of AUTOEND field.
	I2C_CR2_AUTOEND_Pos = 0x19
	// Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000
	// Bit AUTOEND.
	I2C_CR2_AUTOEND = 0x2000000
	// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
	I2C_CR2_AUTOEND_Software = 0x0
	// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
	I2C_CR2_AUTOEND_Automatic = 0x1
	// Position of PECBYTE field.
	I2C_CR2_PECBYTE_Pos = 0x1a
	// Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000
	// Bit PECBYTE.
	I2C_CR2_PECBYTE = 0x4000000
	// No PEC transfer
	I2C_CR2_PECBYTE_NoPec = 0x0
	// PEC transmission/reception is requested
	I2C_CR2_PECBYTE_Pec = 0x1

	// OAR1: Own address register 1
	// Position of OA1 field.
	I2C_OAR1_OA1_Pos = 0x0
	// Bit mask of OA1 field.
	I2C_OAR1_OA1_Msk = 0x3ff
	// Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Pos = 0xa
	// Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400
	// Bit OA1MODE.
	I2C_OAR1_OA1MODE = 0x400
	// Own address 1 is a 7-bit address
	I2C_OAR1_OA1MODE_Bit7 = 0x0
	// Own address 1 is a 10-bit address
	I2C_OAR1_OA1MODE_Bit10 = 0x1
	// Position of OA1EN field.
	I2C_OAR1_OA1EN_Pos = 0xf
	// Bit mask of OA1EN field.
	I2C_OAR1_OA1EN_Msk = 0x8000
	// Bit OA1EN.
	I2C_OAR1_OA1EN = 0x8000
	// Own address 1 disabled. The received slave address OA1 is NACKed
	I2C_OAR1_OA1EN_Disabled = 0x0
	// Own address 1 enabled. The received slave address OA1 is ACKed
	I2C_OAR1_OA1EN_Enabled = 0x1

	// OAR2: Own address register 2
	// Position of OA2 field.
	I2C_OAR2_OA2_Pos = 0x1
	// Bit mask of OA2 field.
	I2C_OAR2_OA2_Msk = 0xfe
	// Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Pos = 0x8
	// Bit mask of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700
	// No mask
	I2C_OAR2_OA2MSK_NoMask = 0x0
	// OA2[1] is masked and don’t care. Only OA2[7:2] are compared
	I2C_OAR2_OA2MSK_Mask1 = 0x1
	// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
	I2C_OAR2_OA2MSK_Mask2 = 0x2
	// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
	I2C_OAR2_OA2MSK_Mask3 = 0x3
	// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
	I2C_OAR2_OA2MSK_Mask4 = 0x4
	// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
	I2C_OAR2_OA2MSK_Mask5 = 0x5
	// OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
	I2C_OAR2_OA2MSK_Mask6 = 0x6
	// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
	I2C_OAR2_OA2MSK_Mask7 = 0x7
	// Position of OA2EN field.
	I2C_OAR2_OA2EN_Pos = 0xf
	// Bit mask of OA2EN field.
	I2C_OAR2_OA2EN_Msk = 0x8000
	// Bit OA2EN.
	I2C_OAR2_OA2EN = 0x8000
	// Own address 2 disabled. The received slave address OA2 is NACKed
	I2C_OAR2_OA2EN_Disabled = 0x0
	// Own address 2 enabled. The received slave address OA2 is ACKed
	I2C_OAR2_OA2EN_Enabled = 0x1

	// TIMINGR: Timing register
	// Position of SCLL field.
	I2C_TIMINGR_SCLL_Pos = 0x0
	// Bit mask of SCLL field.
	I2C_TIMINGR_SCLL_Msk = 0xff
	// Position of SCLH field.
	I2C_TIMINGR_SCLH_Pos = 0x8
	// Bit mask of SCLH field.
	I2C_TIMINGR_SCLH_Msk = 0xff00
	// Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Pos = 0x10
	// Bit mask of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000
	// Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14
	// Bit mask of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000
	// Position of PRESC field.
	I2C_TIMINGR_PRESC_Pos = 0x1c
	// Bit mask of PRESC field.
	I2C_TIMINGR_PRESC_Msk = 0xf0000000

	// TIMEOUTR: Status register 1
	// Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0
	// Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff
	// Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Pos = 0xc
	// Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk = 0x1000
	// Bit TIDLE.
	I2C_TIMEOUTR_TIDLE = 0x1000
	// TIMEOUTA is used to detect SCL low timeout
	I2C_TIMEOUTR_TIDLE_Disabled = 0x0
	// TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
	I2C_TIMEOUTR_TIDLE_Enabled = 0x1
	// Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf
	// Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000
	// Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMOUTEN = 0x8000
	// SCL timeout detection is disabled
	I2C_TIMEOUTR_TIMOUTEN_Disabled = 0x0
	// SCL timeout detection is enabled
	I2C_TIMEOUTR_TIMOUTEN_Enabled = 0x1
	// Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10
	// Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000
	// Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Pos = 0x1f
	// Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk = 0x80000000
	// Bit TEXTEN.
	I2C_TIMEOUTR_TEXTEN = 0x80000000
	// Extended clock timeout detection is disabled
	I2C_TIMEOUTR_TEXTEN_Disabled = 0x0
	// Extended clock timeout detection is enabled
	I2C_TIMEOUTR_TEXTEN_Enabled = 0x1

	// ISR: Interrupt and Status register
	// Position of ADDCODE field.
	I2C_ISR_ADDCODE_Pos = 0x11
	// Bit mask of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000
	// Position of DIR field.
	I2C_ISR_DIR_Pos = 0x10
	// Bit mask of DIR field.
	I2C_ISR_DIR_Msk = 0x10000
	// Bit DIR.
	I2C_ISR_DIR = 0x10000
	// Write transfer, slave enters receiver mode
	I2C_ISR_DIR_Write = 0x0
	// Read transfer, slave enters transmitter mode
	I2C_ISR_DIR_Read = 0x1
	// Position of BUSY field.
	I2C_ISR_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	I2C_ISR_BUSY_Msk = 0x8000
	// Bit BUSY.
	I2C_ISR_BUSY = 0x8000
	// No communication is in progress on the bus
	I2C_ISR_BUSY_NotBusy = 0x0
	// A communication is in progress on the bus
	I2C_ISR_BUSY_Busy = 0x1
	// Position of ALERT field.
	I2C_ISR_ALERT_Pos = 0xd
	// Bit mask of ALERT field.
	I2C_ISR_ALERT_Msk = 0x2000
	// Bit ALERT.
	I2C_ISR_ALERT = 0x2000
	// SMBA alert is not detected
	I2C_ISR_ALERT_NoAlert = 0x0
	// SMBA alert event is detected on SMBA pin
	I2C_ISR_ALERT_Alert = 0x1
	// Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Pos = 0xc
	// Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000
	// Bit TIMEOUT.
	I2C_ISR_TIMEOUT = 0x1000
	// No timeout occured
	I2C_ISR_TIMEOUT_NoTimeout = 0x0
	// Timeout occured
	I2C_ISR_TIMEOUT_Timeout = 0x1
	// Position of PECERR field.
	I2C_ISR_PECERR_Pos = 0xb
	// Bit mask of PECERR field.
	I2C_ISR_PECERR_Msk = 0x800
	// Bit PECERR.
	I2C_ISR_PECERR = 0x800
	// Received PEC does match with PEC register
	I2C_ISR_PECERR_Match = 0x0
	// Received PEC does not match with PEC register
	I2C_ISR_PECERR_NoMatch = 0x1
	// Position of OVR field.
	I2C_ISR_OVR_Pos = 0xa
	// Bit mask of OVR field.
	I2C_ISR_OVR_Msk = 0x400
	// Bit OVR.
	I2C_ISR_OVR = 0x400
	// No overrun/underrun error occurs
	I2C_ISR_OVR_NoOverrun = 0x0
	// slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
	I2C_ISR_OVR_Overrun = 0x1
	// Position of ARLO field.
	I2C_ISR_ARLO_Pos = 0x9
	// Bit mask of ARLO field.
	I2C_ISR_ARLO_Msk = 0x200
	// Bit ARLO.
	I2C_ISR_ARLO = 0x200
	// No arbitration lost
	I2C_ISR_ARLO_NotLost = 0x0
	// Arbitration lost
	I2C_ISR_ARLO_Lost = 0x1
	// Position of BERR field.
	I2C_ISR_BERR_Pos = 0x8
	// Bit mask of BERR field.
	I2C_ISR_BERR_Msk = 0x100
	// Bit BERR.
	I2C_ISR_BERR = 0x100
	// No bus error
	I2C_ISR_BERR_NoError = 0x0
	// Misplaced Start and Stop condition is detected
	I2C_ISR_BERR_Error = 0x1
	// Position of TCR field.
	I2C_ISR_TCR_Pos = 0x7
	// Bit mask of TCR field.
	I2C_ISR_TCR_Msk = 0x80
	// Bit TCR.
	I2C_ISR_TCR = 0x80
	// Transfer is not complete
	I2C_ISR_TCR_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TCR_Complete = 0x1
	// Position of TC field.
	I2C_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	I2C_ISR_TC_Msk = 0x40
	// Bit TC.
	I2C_ISR_TC = 0x40
	// Transfer is not complete
	I2C_ISR_TC_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TC_Complete = 0x1
	// Position of STOPF field.
	I2C_ISR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	I2C_ISR_STOPF_Msk = 0x20
	// Bit STOPF.
	I2C_ISR_STOPF = 0x20
	// No Stop condition detected
	I2C_ISR_STOPF_NoStop = 0x0
	// Stop condition detected
	I2C_ISR_STOPF_Stop = 0x1
	// Position of NACKF field.
	I2C_ISR_NACKF_Pos = 0x4
	// Bit mask of NACKF field.
	I2C_ISR_NACKF_Msk = 0x10
	// Bit NACKF.
	I2C_ISR_NACKF = 0x10
	// No NACK has been received
	I2C_ISR_NACKF_NoNack = 0x0
	// NACK has been received
	I2C_ISR_NACKF_Nack = 0x1
	// Position of ADDR field.
	I2C_ISR_ADDR_Pos = 0x3
	// Bit mask of ADDR field.
	I2C_ISR_ADDR_Msk = 0x8
	// Bit ADDR.
	I2C_ISR_ADDR = 0x8
	// Adress mismatched or not received
	I2C_ISR_ADDR_NotMatch = 0x0
	// Received slave address matched with one of the enabled slave addresses
	I2C_ISR_ADDR_Match = 0x1
	// Position of RXNE field.
	I2C_ISR_RXNE_Pos = 0x2
	// Bit mask of RXNE field.
	I2C_ISR_RXNE_Msk = 0x4
	// Bit RXNE.
	I2C_ISR_RXNE = 0x4
	// The RXDR register is empty
	I2C_ISR_RXNE_Empty = 0x0
	// Received data is copied into the RXDR register, and is ready to be read
	I2C_ISR_RXNE_NotEmpty = 0x1
	// Position of TXIS field.
	I2C_ISR_TXIS_Pos = 0x1
	// Bit mask of TXIS field.
	I2C_ISR_TXIS_Msk = 0x2
	// Bit TXIS.
	I2C_ISR_TXIS = 0x2
	// The TXDR register is not empty
	I2C_ISR_TXIS_NotEmpty = 0x0
	// The TXDR register is empty and the data to be transmitted must be written in the TXDR register
	I2C_ISR_TXIS_Empty = 0x1
	// Generate a TXIS event
	I2C_ISR_TXIS_Trigger = 0x1
	// Position of TXE field.
	I2C_ISR_TXE_Pos = 0x0
	// Bit mask of TXE field.
	I2C_ISR_TXE_Msk = 0x1
	// Bit TXE.
	I2C_ISR_TXE = 0x1
	// TXDR register not empty
	I2C_ISR_TXE_NotEmpty = 0x0
	// TXDR register empty
	I2C_ISR_TXE_Empty = 0x1
	// Flush the transmit data register
	I2C_ISR_TXE_Flush = 0x1

	// ICR: Interrupt clear register
	// Position of ALERTCF field.
	I2C_ICR_ALERTCF_Pos = 0xd
	// Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF_Msk = 0x2000
	// Bit ALERTCF.
	I2C_ICR_ALERTCF = 0x2000
	// Clears the ALERT flag in ISR register
	I2C_ICR_ALERTCF_Clear = 0x1
	// Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Pos = 0xc
	// Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000
	// Bit TIMOUTCF.
	I2C_ICR_TIMOUTCF = 0x1000
	// Clears the TIMOUT flag in ISR register
	I2C_ICR_TIMOUTCF_Clear = 0x1
	// Position of PECCF field.
	I2C_ICR_PECCF_Pos = 0xb
	// Bit mask of PECCF field.
	I2C_ICR_PECCF_Msk = 0x800
	// Bit PECCF.
	I2C_ICR_PECCF = 0x800
	// Clears the PEC flag in ISR register
	I2C_ICR_PECCF_Clear = 0x1
	// Position of OVRCF field.
	I2C_ICR_OVRCF_Pos = 0xa
	// Bit mask of OVRCF field.
	I2C_ICR_OVRCF_Msk = 0x400
	// Bit OVRCF.
	I2C_ICR_OVRCF = 0x400
	// Clears the OVR flag in ISR register
	I2C_ICR_OVRCF_Clear = 0x1
	// Position of ARLOCF field.
	I2C_ICR_ARLOCF_Pos = 0x9
	// Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF_Msk = 0x200
	// Bit ARLOCF.
	I2C_ICR_ARLOCF = 0x200
	// Clears the ARLO flag in ISR register
	I2C_ICR_ARLOCF_Clear = 0x1
	// Position of BERRCF field.
	I2C_ICR_BERRCF_Pos = 0x8
	// Bit mask of BERRCF field.
	I2C_ICR_BERRCF_Msk = 0x100
	// Bit BERRCF.
	I2C_ICR_BERRCF = 0x100
	// Clears the BERR flag in ISR register
	I2C_ICR_BERRCF_Clear = 0x1
	// Position of STOPCF field.
	I2C_ICR_STOPCF_Pos = 0x5
	// Bit mask of STOPCF field.
	I2C_ICR_STOPCF_Msk = 0x20
	// Bit STOPCF.
	I2C_ICR_STOPCF = 0x20
	// Clears the STOP flag in ISR register
	I2C_ICR_STOPCF_Clear = 0x1
	// Position of NACKCF field.
	I2C_ICR_NACKCF_Pos = 0x4
	// Bit mask of NACKCF field.
	I2C_ICR_NACKCF_Msk = 0x10
	// Bit NACKCF.
	I2C_ICR_NACKCF = 0x10
	// Clears the NACK flag in ISR register
	I2C_ICR_NACKCF_Clear = 0x1
	// Position of ADDRCF field.
	I2C_ICR_ADDRCF_Pos = 0x3
	// Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF_Msk = 0x8
	// Bit ADDRCF.
	I2C_ICR_ADDRCF = 0x8
	// Clears the ADDR flag in ISR register
	I2C_ICR_ADDRCF_Clear = 0x1

	// PECR: PEC register
	// Position of PEC field.
	I2C_PECR_PEC_Pos = 0x0
	// Bit mask of PEC field.
	I2C_PECR_PEC_Msk = 0xff

	// RXDR: Receive data register
	// Position of RXDATA field.
	I2C_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff

	// TXDR: Transmit data register
	// Position of TXDATA field.
	I2C_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff
)

// Constants for IWDG: Independent watchdog
const (
	// KR: Key register
	// Position of KEY field.
	IWDG_KR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	IWDG_KR_KEY_Msk = 0xffff
	// Enable access to PR, RLR and WINR registers
	IWDG_KR_KEY_Unlock = 0x5555
	// Feed watchdog with RLR register value
	IWDG_KR_KEY_Feed = 0xaaaa
	// Start the watchdog
	IWDG_KR_KEY_Start = 0xcccc

	// PR: Prescaler register
	// Position of PR field.
	IWDG_PR_PR_Pos = 0x0
	// Bit mask of PR field.
	IWDG_PR_PR_Msk = 0x7
	// Divider /4
	IWDG_PR_PR_DivideBy4 = 0x0
	// Divider /8
	IWDG_PR_PR_DivideBy8 = 0x1
	// Divider /16
	IWDG_PR_PR_DivideBy16 = 0x2
	// Divider /32
	IWDG_PR_PR_DivideBy32 = 0x3
	// Divider /64
	IWDG_PR_PR_DivideBy64 = 0x4
	// Divider /128
	IWDG_PR_PR_DivideBy128 = 0x5
	// Divider /256
	IWDG_PR_PR_DivideBy256 = 0x6

	// RLR: Reload register
	// Position of RL field.
	IWDG_RLR_RL_Pos = 0x0
	// Bit mask of RL field.
	IWDG_RLR_RL_Msk = 0xfff

	// SR: Status register
	// Position of PVU field.
	IWDG_SR_PVU_Pos = 0x0
	// Bit mask of PVU field.
	IWDG_SR_PVU_Msk = 0x1
	// Bit PVU.
	IWDG_SR_PVU = 0x1
	// Position of RVU field.
	IWDG_SR_RVU_Pos = 0x1
	// Bit mask of RVU field.
	IWDG_SR_RVU_Msk = 0x2
	// Bit RVU.
	IWDG_SR_RVU = 0x2
	// Position of WVU field.
	IWDG_SR_WVU_Pos = 0x2
	// Bit mask of WVU field.
	IWDG_SR_WVU_Msk = 0x4
	// Bit WVU.
	IWDG_SR_WVU = 0x4

	// WINR: Window register
	// Position of WIN field.
	IWDG_WINR_WIN_Pos = 0x0
	// Bit mask of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff
)

// Constants for PWR: Power control
const (
	// CR1: Power control register 1
	// Position of LPR field.
	PWR_CR1_LPR_Pos = 0xe
	// Bit mask of LPR field.
	PWR_CR1_LPR_Msk = 0x4000
	// Bit LPR.
	PWR_CR1_LPR = 0x4000
	// Position of VOS field.
	PWR_CR1_VOS_Pos = 0x9
	// Bit mask of VOS field.
	PWR_CR1_VOS_Msk = 0x600
	// Position of DBP field.
	PWR_CR1_DBP_Pos = 0x8
	// Bit mask of DBP field.
	PWR_CR1_DBP_Msk = 0x100
	// Bit DBP.
	PWR_CR1_DBP = 0x100
	// Position of FPD_LPSLP field.
	PWR_CR1_FPD_LPSLP_Pos = 0x5
	// Bit mask of FPD_LPSLP field.
	PWR_CR1_FPD_LPSLP_Msk = 0x20
	// Bit FPD_LPSLP.
	PWR_CR1_FPD_LPSLP = 0x20
	// Position of FPD_LPRUN field.
	PWR_CR1_FPD_LPRUN_Pos = 0x4
	// Bit mask of FPD_LPRUN field.
	PWR_CR1_FPD_LPRUN_Msk = 0x10
	// Bit FPD_LPRUN.
	PWR_CR1_FPD_LPRUN = 0x10
	// Position of FPD_STOP field.
	PWR_CR1_FPD_STOP_Pos = 0x3
	// Bit mask of FPD_STOP field.
	PWR_CR1_FPD_STOP_Msk = 0x8
	// Bit FPD_STOP.
	PWR_CR1_FPD_STOP = 0x8
	// Position of LPMS field.
	PWR_CR1_LPMS_Pos = 0x0
	// Bit mask of LPMS field.
	PWR_CR1_LPMS_Msk = 0x7

	// CR2: Power control register 2
	// Position of USV field.
	PWR_CR2_USV_Pos = 0xa
	// Bit mask of USV field.
	PWR_CR2_USV_Msk = 0x400
	// Bit USV.
	PWR_CR2_USV = 0x400

	// CR3: Power control register 3
	// Position of EWUP1 field.
	PWR_CR3_EWUP1_Pos = 0x0
	// Bit mask of EWUP1 field.
	PWR_CR3_EWUP1_Msk = 0x1
	// Bit EWUP1.
	PWR_CR3_EWUP1 = 0x1
	// Position of EWUP2 field.
	PWR_CR3_EWUP2_Pos = 0x1
	// Bit mask of EWUP2 field.
	PWR_CR3_EWUP2_Msk = 0x2
	// Bit EWUP2.
	PWR_CR3_EWUP2 = 0x2
	// Position of EWUP3 field.
	PWR_CR3_EWUP3_Pos = 0x2
	// Bit mask of EWUP3 field.
	PWR_CR3_EWUP3_Msk = 0x4
	// Bit EWUP3.
	PWR_CR3_EWUP3 = 0x4
	// Position of EWUP4 field.
	PWR_CR3_EWUP4_Pos = 0x3
	// Bit mask of EWUP4 field.
	PWR_CR3_EWUP4_Msk = 0x8
	// Bit EWUP4.
	PWR_CR3_EWUP4 = 0x8
	// Position of EWUP5 field.
	PWR_CR3_EWUP5_Pos = 0x4
	// Bit mask of EWUP5 field.
	PWR_CR3_EWUP5_Msk = 0x10
	// Bit EWUP5.
	PWR_CR3_EWUP5 = 0x10
	// Position of EWUP6 field.
	PWR_CR3_EWUP6_Pos = 0x5
	// Bit mask of EWUP6 field.
	PWR_CR3_EWUP6_Msk = 0x20
	// Bit EWUP6.
	PWR_CR3_EWUP6 = 0x20
	// Position of APC field.
	PWR_CR3_APC_Pos = 0xa
	// Bit mask of APC field.
	PWR_CR3_APC_Msk = 0x400
	// Bit APC.
	PWR_CR3_APC = 0x400
	// Position of EIWUL field.
	PWR_CR3_EIWUL_Pos = 0xf
	// Bit mask of EIWUL field.
	PWR_CR3_EIWUL_Msk = 0x8000
	// Bit EIWUL.
	PWR_CR3_EIWUL = 0x8000

	// CR4: Power control register 4
	// Position of WP1 field.
	PWR_CR4_WP1_Pos = 0x0
	// Bit mask of WP1 field.
	PWR_CR4_WP1_Msk = 0x1
	// Bit WP1.
	PWR_CR4_WP1 = 0x1
	// Position of WP2 field.
	PWR_CR4_WP2_Pos = 0x1
	// Bit mask of WP2 field.
	PWR_CR4_WP2_Msk = 0x2
	// Bit WP2.
	PWR_CR4_WP2 = 0x2
	// Position of WP3 field.
	PWR_CR4_WP3_Pos = 0x2
	// Bit mask of WP3 field.
	PWR_CR4_WP3_Msk = 0x4
	// Bit WP3.
	PWR_CR4_WP3 = 0x4
	// Position of WP4 field.
	PWR_CR4_WP4_Pos = 0x3
	// Bit mask of WP4 field.
	PWR_CR4_WP4_Msk = 0x8
	// Bit WP4.
	PWR_CR4_WP4 = 0x8
	// Position of WP5 field.
	PWR_CR4_WP5_Pos = 0x4
	// Bit mask of WP5 field.
	PWR_CR4_WP5_Msk = 0x10
	// Bit WP5.
	PWR_CR4_WP5 = 0x10
	// Position of WP6 field.
	PWR_CR4_WP6_Pos = 0x5
	// Bit mask of WP6 field.
	PWR_CR4_WP6_Msk = 0x20
	// Bit WP6.
	PWR_CR4_WP6 = 0x20
	// Position of VBE field.
	PWR_CR4_VBE_Pos = 0x8
	// Bit mask of VBE field.
	PWR_CR4_VBE_Msk = 0x100
	// Bit VBE.
	PWR_CR4_VBE = 0x100
	// Position of VBRS field.
	PWR_CR4_VBRS_Pos = 0x9
	// Bit mask of VBRS field.
	PWR_CR4_VBRS_Msk = 0x200
	// Bit VBRS.
	PWR_CR4_VBRS = 0x200

	// SR1: Power status register 1
	// Position of WUF1 field.
	PWR_SR1_WUF1_Pos = 0x0
	// Bit mask of WUF1 field.
	PWR_SR1_WUF1_Msk = 0x1
	// Bit WUF1.
	PWR_SR1_WUF1 = 0x1
	// Position of WUF2 field.
	PWR_SR1_WUF2_Pos = 0x1
	// Bit mask of WUF2 field.
	PWR_SR1_WUF2_Msk = 0x2
	// Bit WUF2.
	PWR_SR1_WUF2 = 0x2
	// Position of WUF3 field.
	PWR_SR1_WUF3_Pos = 0x2
	// Bit mask of WUF3 field.
	PWR_SR1_WUF3_Msk = 0x4
	// Bit WUF3.
	PWR_SR1_WUF3 = 0x4
	// Position of WUF4 field.
	PWR_SR1_WUF4_Pos = 0x3
	// Bit mask of WUF4 field.
	PWR_SR1_WUF4_Msk = 0x8
	// Bit WUF4.
	PWR_SR1_WUF4 = 0x8
	// Position of WUF5 field.
	PWR_SR1_WUF5_Pos = 0x4
	// Bit mask of WUF5 field.
	PWR_SR1_WUF5_Msk = 0x10
	// Bit WUF5.
	PWR_SR1_WUF5 = 0x10
	// Position of WUF6 field.
	PWR_SR1_WUF6_Pos = 0x5
	// Bit mask of WUF6 field.
	PWR_SR1_WUF6_Msk = 0x20
	// Bit WUF6.
	PWR_SR1_WUF6 = 0x20
	// Position of SBF field.
	PWR_SR1_SBF_Pos = 0x8
	// Bit mask of SBF field.
	PWR_SR1_SBF_Msk = 0x100
	// Bit SBF.
	PWR_SR1_SBF = 0x100
	// Position of WUFI field.
	PWR_SR1_WUFI_Pos = 0xf
	// Bit mask of WUFI field.
	PWR_SR1_WUFI_Msk = 0x8000
	// Bit WUFI.
	PWR_SR1_WUFI = 0x8000

	// SR2: Power status register 2
	// Position of VOSF field.
	PWR_SR2_VOSF_Pos = 0xa
	// Bit mask of VOSF field.
	PWR_SR2_VOSF_Msk = 0x400
	// Bit VOSF.
	PWR_SR2_VOSF = 0x400
	// Position of REGLPF field.
	PWR_SR2_REGLPF_Pos = 0x9
	// Bit mask of REGLPF field.
	PWR_SR2_REGLPF_Msk = 0x200
	// Bit REGLPF.
	PWR_SR2_REGLPF = 0x200
	// Position of REGLPS field.
	PWR_SR2_REGLPS_Pos = 0x8
	// Bit mask of REGLPS field.
	PWR_SR2_REGLPS_Msk = 0x100
	// Bit REGLPS.
	PWR_SR2_REGLPS = 0x100
	// Position of FLASH_RDY field.
	PWR_SR2_FLASH_RDY_Pos = 0x7
	// Bit mask of FLASH_RDY field.
	PWR_SR2_FLASH_RDY_Msk = 0x80
	// Bit FLASH_RDY.
	PWR_SR2_FLASH_RDY = 0x80

	// SCR: Power status clear register
	// Position of CSBF field.
	PWR_SCR_CSBF_Pos = 0x8
	// Bit mask of CSBF field.
	PWR_SCR_CSBF_Msk = 0x100
	// Bit CSBF.
	PWR_SCR_CSBF = 0x100
	// Position of CWUF6 field.
	PWR_SCR_CWUF6_Pos = 0x5
	// Bit mask of CWUF6 field.
	PWR_SCR_CWUF6_Msk = 0x20
	// Bit CWUF6.
	PWR_SCR_CWUF6 = 0x20
	// Position of CWUF5 field.
	PWR_SCR_CWUF5_Pos = 0x4
	// Bit mask of CWUF5 field.
	PWR_SCR_CWUF5_Msk = 0x10
	// Bit CWUF5.
	PWR_SCR_CWUF5 = 0x10
	// Position of CWUF4 field.
	PWR_SCR_CWUF4_Pos = 0x3
	// Bit mask of CWUF4 field.
	PWR_SCR_CWUF4_Msk = 0x8
	// Bit CWUF4.
	PWR_SCR_CWUF4 = 0x8
	// Position of CWUF3 field.
	PWR_SCR_CWUF3_Pos = 0x2
	// Bit mask of CWUF3 field.
	PWR_SCR_CWUF3_Msk = 0x4
	// Bit CWUF3.
	PWR_SCR_CWUF3 = 0x4
	// Position of CWUF2 field.
	PWR_SCR_CWUF2_Pos = 0x1
	// Bit mask of CWUF2 field.
	PWR_SCR_CWUF2_Msk = 0x2
	// Bit CWUF2.
	PWR_SCR_CWUF2 = 0x2
	// Position of CWUF1 field.
	PWR_SCR_CWUF1_Pos = 0x0
	// Bit mask of CWUF1 field.
	PWR_SCR_CWUF1_Msk = 0x1
	// Bit CWUF1.
	PWR_SCR_CWUF1 = 0x1

	// PUCRA: Power Port A pull-up control register
	// Position of PU15 field.
	PWR_PUCRA_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRA_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRA_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRA_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRA_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRA_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRA_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRA_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRA_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRA_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRA_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRA_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRA_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRA_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRA_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRA_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRA_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRA_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRA_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRA_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRA_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRA_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRA_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRA_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRA_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRA_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRA_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRA_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRA_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRA_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRA_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRA_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRA_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRA_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRA_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRA_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRA_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRA_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRA_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRA_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRA_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRA_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRA_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRA_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRA_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRA_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRA_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRA_PU0 = 0x1

	// PDCRA: Power Port A pull-down control register
	// Position of PD15 field.
	PWR_PDCRA_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRA_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRA_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRA_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRA_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRA_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRA_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRA_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRA_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRA_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRA_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRA_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRA_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRA_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRA_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRA_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRA_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRA_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRA_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRA_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRA_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRA_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRA_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRA_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRA_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRA_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRA_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRA_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRA_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRA_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRA_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRA_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRA_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRA_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRA_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRA_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRA_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRA_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRA_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRA_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRA_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRA_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRA_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRA_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRA_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRA_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRA_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRA_PD0 = 0x1

	// PUCRB: Power Port B pull-up control register
	// Position of PU15 field.
	PWR_PUCRB_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRB_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRB_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRB_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRB_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRB_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRB_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRB_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRB_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRB_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRB_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRB_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRB_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRB_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRB_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRB_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRB_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRB_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRB_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRB_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRB_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRB_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRB_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRB_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRB_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRB_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRB_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRB_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRB_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRB_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRB_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRB_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRB_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRB_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRB_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRB_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRB_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRB_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRB_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRB_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRB_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRB_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRB_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRB_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRB_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRB_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRB_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRB_PU0 = 0x1

	// PDCRB: Power Port B pull-down control register
	// Position of PD15 field.
	PWR_PDCRB_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRB_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRB_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRB_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRB_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRB_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRB_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRB_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRB_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRB_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRB_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRB_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRB_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRB_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRB_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRB_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRB_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRB_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRB_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRB_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRB_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRB_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRB_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRB_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRB_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRB_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRB_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRB_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRB_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRB_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRB_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRB_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRB_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRB_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRB_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRB_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRB_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRB_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRB_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRB_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRB_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRB_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRB_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRB_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRB_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRB_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRB_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRB_PD0 = 0x1

	// PUCRC: Power Port C pull-up control register
	// Position of PU15 field.
	PWR_PUCRC_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRC_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRC_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRC_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRC_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRC_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRC_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRC_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRC_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRC_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRC_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRC_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRC_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRC_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRC_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRC_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRC_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRC_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRC_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRC_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRC_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRC_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRC_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRC_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRC_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRC_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRC_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRC_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRC_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRC_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRC_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRC_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRC_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRC_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRC_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRC_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRC_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRC_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRC_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRC_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRC_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRC_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRC_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRC_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRC_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRC_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRC_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRC_PU0 = 0x1

	// PDCRC: Power Port C pull-down control register
	// Position of PD15 field.
	PWR_PDCRC_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRC_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRC_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRC_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRC_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRC_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRC_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRC_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRC_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRC_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRC_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRC_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRC_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRC_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRC_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRC_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRC_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRC_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRC_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRC_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRC_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRC_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRC_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRC_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRC_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRC_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRC_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRC_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRC_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRC_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRC_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRC_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRC_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRC_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRC_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRC_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRC_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRC_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRC_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRC_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRC_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRC_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRC_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRC_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRC_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRC_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRC_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRC_PD0 = 0x1

	// PUCRD: Power Port D pull-up control register
	// Position of PU15 field.
	PWR_PUCRD_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRD_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRD_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRD_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRD_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRD_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRD_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRD_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRD_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRD_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRD_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRD_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRD_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRD_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRD_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRD_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRD_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRD_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRD_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRD_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRD_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRD_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRD_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRD_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRD_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRD_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRD_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRD_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRD_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRD_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRD_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRD_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRD_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRD_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRD_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRD_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRD_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRD_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRD_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRD_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRD_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRD_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRD_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRD_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRD_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRD_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRD_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRD_PU0 = 0x1

	// PDCRD: Power Port D pull-down control register
	// Position of PD15 field.
	PWR_PDCRD_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRD_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRD_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRD_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRD_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRD_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRD_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRD_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRD_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRD_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRD_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRD_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRD_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRD_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRD_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRD_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRD_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRD_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRD_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRD_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRD_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRD_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRD_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRD_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRD_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRD_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRD_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRD_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRD_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRD_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRD_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRD_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRD_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRD_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRD_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRD_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRD_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRD_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRD_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRD_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRD_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRD_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRD_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRD_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRD_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRD_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRD_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRD_PD0 = 0x1

	// PUCRE: Power Port E pull-UP control register
	// Position of PU15 field.
	PWR_PUCRE_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRE_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRE_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRE_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRE_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRE_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRE_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRE_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRE_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRE_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRE_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRE_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRE_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRE_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRE_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRE_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRE_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRE_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRE_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRE_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRE_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRE_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRE_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRE_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRE_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRE_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRE_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRE_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRE_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRE_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRE_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRE_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRE_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRE_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRE_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRE_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRE_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRE_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRE_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRE_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRE_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRE_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRE_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRE_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRE_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRE_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRE_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRE_PU0 = 0x1

	// PDCRE: Power Port E pull-down control register
	// Position of PD15 field.
	PWR_PDCRE_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRE_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRE_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRE_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRE_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRE_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRE_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRE_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRE_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRE_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRE_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRE_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRE_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRE_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRE_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRE_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRE_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRE_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRE_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRE_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRE_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRE_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRE_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRE_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRE_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRE_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRE_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRE_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRE_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRE_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRE_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRE_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRE_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRE_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRE_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRE_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRE_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRE_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRE_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRE_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRE_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRE_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRE_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRE_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRE_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRE_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRE_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRE_PD0 = 0x1

	// PUCRF: Power Port F pull-up control register
	// Position of PU13 field.
	PWR_PUCRF_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRF_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRF_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRF_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRF_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRF_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRF_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRF_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRF_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRF_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRF_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRF_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRF_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRF_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRF_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRF_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRF_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRF_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRF_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRF_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRF_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRF_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRF_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRF_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRF_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRF_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRF_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRF_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRF_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRF_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRF_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRF_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRF_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRF_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRF_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRF_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRF_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRF_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRF_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRF_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRF_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRF_PU0 = 0x1

	// PDCRF: Power Port F pull-down control register
	// Position of PD13 field.
	PWR_PDCRF_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRF_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRF_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRF_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRF_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRF_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRF_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRF_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRF_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRF_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRF_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRF_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRF_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRF_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRF_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRF_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRF_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRF_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRF_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRF_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRF_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRF_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRF_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRF_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRF_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRF_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRF_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRF_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRF_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRF_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRF_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRF_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRF_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRF_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRF_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRF_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRF_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRF_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRF_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRF_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRF_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRF_PD0 = 0x1
)

// Constants for RCC: Reset and clock control
const (
	// CR: Clock control register
	// Position of HSION field.
	RCC_CR_HSION_Pos = 0x8
	// Bit mask of HSION field.
	RCC_CR_HSION_Msk = 0x100
	// Bit HSION.
	RCC_CR_HSION = 0x100
	// HSI oscillator powered off
	RCC_CR_HSION_Disabled = 0x0
	// HSI oscillator enabled
	RCC_CR_HSION_Enabled = 0x1
	// Position of HSIKERON field.
	RCC_CR_HSIKERON_Pos = 0x9
	// Bit mask of HSIKERON field.
	RCC_CR_HSIKERON_Msk = 0x200
	// Bit HSIKERON.
	RCC_CR_HSIKERON = 0x200
	// No effect on HSI16 oscillator
	RCC_CR_HSIKERON_NotForce = 0x0
	// HSI16 oscillator forced on even in Stop modes
	RCC_CR_HSIKERON_Forced = 0x1
	// Position of HSIRDY field.
	RCC_CR_HSIRDY_Pos = 0xa
	// Bit mask of HSIRDY field.
	RCC_CR_HSIRDY_Msk = 0x400
	// Bit HSIRDY.
	RCC_CR_HSIRDY = 0x400
	// HSI oscillator not ready
	RCC_CR_HSIRDY_NotReady = 0x0
	// HSI oscillator ready
	RCC_CR_HSIRDY_Ready = 0x1
	// Position of HSIDIV field.
	RCC_CR_HSIDIV_Pos = 0xb
	// Bit mask of HSIDIV field.
	RCC_CR_HSIDIV_Msk = 0x3800
	// Divide HSI16 by 1
	RCC_CR_HSIDIV_Div1 = 0x0
	// Divide HSI16 by 2
	RCC_CR_HSIDIV_Div2 = 0x1
	// Divide HSI16 by 4
	RCC_CR_HSIDIV_Div4 = 0x2
	// Divide HSI16 by 8
	RCC_CR_HSIDIV_Div8 = 0x3
	// Divide HSI16 by 16
	RCC_CR_HSIDIV_Div16 = 0x4
	// Divide HSI16 by 32
	RCC_CR_HSIDIV_Div32 = 0x5
	// Divide HSI16 by 64
	RCC_CR_HSIDIV_Div64 = 0x6
	// Divide HSI16 by 128
	RCC_CR_HSIDIV_Div128 = 0x7
	// Position of HSEON field.
	RCC_CR_HSEON_Pos = 0x10
	// Bit mask of HSEON field.
	RCC_CR_HSEON_Msk = 0x10000
	// Bit HSEON.
	RCC_CR_HSEON = 0x10000
	// HSE oscillator powered off
	RCC_CR_HSEON_Disabled = 0x0
	// HSE oscillator enabled
	RCC_CR_HSEON_Enabled = 0x1
	// Position of HSERDY field.
	RCC_CR_HSERDY_Pos = 0x11
	// Bit mask of HSERDY field.
	RCC_CR_HSERDY_Msk = 0x20000
	// Bit HSERDY.
	RCC_CR_HSERDY = 0x20000
	// HSE oscillator not ready
	RCC_CR_HSERDY_NotReady = 0x0
	// HSE oscillator ready
	RCC_CR_HSERDY_Ready = 0x1
	// Position of HSEBYP field.
	RCC_CR_HSEBYP_Pos = 0x12
	// Bit mask of HSEBYP field.
	RCC_CR_HSEBYP_Msk = 0x40000
	// Bit HSEBYP.
	RCC_CR_HSEBYP = 0x40000
	// HSE is a crystal oscillator or ceramic resonator
	RCC_CR_HSEBYP_Crystal = 0x0
	// HSE is driven by an external clock
	RCC_CR_HSEBYP_ExtClock = 0x1
	// Position of CSSON field.
	RCC_CR_CSSON_Pos = 0x13
	// Bit mask of CSSON field.
	RCC_CR_CSSON_Msk = 0x80000
	// Bit CSSON.
	RCC_CR_CSSON = 0x80000
	// HSE clock is not monitored
	RCC_CR_CSSON_Disabled = 0x0
	// HSE clock monitor enabled when HSE is ready, otherwise disabled
	RCC_CR_CSSON_Enabled = 0x1
	// Position of PLLON field.
	RCC_CR_PLLON_Pos = 0x18
	// Bit mask of PLLON field.
	RCC_CR_PLLON_Msk = 0x1000000
	// Bit PLLON.
	RCC_CR_PLLON = 0x1000000
	// PLL powered off
	RCC_CR_PLLON_Disabled = 0x0
	// PLL enabled
	RCC_CR_PLLON_Enabled = 0x1
	// Position of PLLRDY field.
	RCC_CR_PLLRDY_Pos = 0x19
	// Bit mask of PLLRDY field.
	RCC_CR_PLLRDY_Msk = 0x2000000
	// Bit PLLRDY.
	RCC_CR_PLLRDY = 0x2000000
	// PLL unlocked
	RCC_CR_PLLRDY_Unlocked = 0x0
	// PLL locked
	RCC_CR_PLLRDY_Locked = 0x1

	// ICSCR: Internal clock sources calibration register
	// Position of HSICAL field.
	RCC_ICSCR_HSICAL_Pos = 0x0
	// Bit mask of HSICAL field.
	RCC_ICSCR_HSICAL_Msk = 0xff
	// Position of HSITRIM field.
	RCC_ICSCR_HSITRIM_Pos = 0x8
	// Bit mask of HSITRIM field.
	RCC_ICSCR_HSITRIM_Msk = 0x7f00

	// CFGR: Clock configuration register
	// Position of MCOPRE field.
	RCC_CFGR_MCOPRE_Pos = 0x1c
	// Bit mask of MCOPRE field.
	RCC_CFGR_MCOPRE_Msk = 0xf0000000
	// Divide by 1
	RCC_CFGR_MCOPRE_Div1 = 0x0
	// Divide by 2
	RCC_CFGR_MCOPRE_Div2 = 0x1
	// Divide by 4
	RCC_CFGR_MCOPRE_Div3 = 0x2
	// Divide by 8
	RCC_CFGR_MCOPRE_Div8 = 0x3
	// Divide by 16
	RCC_CFGR_MCOPRE_Div16 = 0x4
	// Divide by 32
	RCC_CFGR_MCOPRE_Div32 = 0x5
	// Divide by 64
	RCC_CFGR_MCOPRE_Div64 = 0x6
	// Divide by 128
	RCC_CFGR_MCOPRE_Div128 = 0x7
	// Position of MCOSEL field.
	RCC_CFGR_MCOSEL_Pos = 0x18
	// Bit mask of MCOSEL field.
	RCC_CFGR_MCOSEL_Msk = 0xf000000
	// No clock
	RCC_CFGR_MCOSEL_NoClock = 0x0
	// SYSCLK clock selected
	RCC_CFGR_MCOSEL_SYSCLK = 0x1
	// HSI16 oscillator clock selected
	RCC_CFGR_MCOSEL_HSI16 = 0x3
	// HSE oscillator clock selected
	RCC_CFGR_MCOSEL_HSE = 0x4
	// PLLRCLK clock selected
	RCC_CFGR_MCOSEL_PLLR = 0x5
	// LSI oscillator clock selected
	RCC_CFGR_MCOSEL_LSI = 0x6
	// LSE oscillator clock selected
	RCC_CFGR_MCOSEL_LSE = 0x7
	// Position of PPRE field.
	RCC_CFGR_PPRE_Pos = 0xc
	// Bit mask of PPRE field.
	RCC_CFGR_PPRE_Msk = 0x7000
	// Divide by 1
	RCC_CFGR_PPRE_Div1 = 0x0
	// Divide by 2
	RCC_CFGR_PPRE_Div2 = 0x4
	// Divide by 4
	RCC_CFGR_PPRE_Div4 = 0x5
	// Divide by 8
	RCC_CFGR_PPRE_Div8 = 0x6
	// Divide by 16
	RCC_CFGR_PPRE_Div16 = 0x7
	// Position of HPRE field.
	RCC_CFGR_HPRE_Pos = 0x8
	// Bit mask of HPRE field.
	RCC_CFGR_HPRE_Msk = 0xf00
	// Divide by 1
	RCC_CFGR_HPRE_Div1 = 0x0
	// Divide by 2
	RCC_CFGR_HPRE_Div2 = 0x8
	// Divide by 4
	RCC_CFGR_HPRE_Div4 = 0x9
	// Divide by 8
	RCC_CFGR_HPRE_Div8 = 0xa
	// Divide by 16
	RCC_CFGR_HPRE_Div16 = 0xb
	// Divide by 64
	RCC_CFGR_HPRE_Div64 = 0xc
	// Divide by 128
	RCC_CFGR_HPRE_Div128 = 0xd
	// Divide by 256
	RCC_CFGR_HPRE_Div256 = 0xe
	// Divide by 512
	RCC_CFGR_HPRE_Div512 = 0xf
	// Position of SWS field.
	RCC_CFGR_SWS_Pos = 0x3
	// Bit mask of SWS field.
	RCC_CFGR_SWS_Msk = 0x38
	// HSISYS clock selected
	RCC_CFGR_SWS_HSISYS = 0x0
	// HSE clock selected
	RCC_CFGR_SWS_HSE = 0x1
	// PLLRCLK clock selected
	RCC_CFGR_SWS_PLLR = 0x2
	// LSI clock selected
	RCC_CFGR_SWS_LSI = 0x3
	// LSE clock selected
	RCC_CFGR_SWS_LSE = 0x4
	// Position of SW field.
	RCC_CFGR_SW_Pos = 0x0
	// Bit mask of SW field.
	RCC_CFGR_SW_Msk = 0x7
	// HSISYS clock selected
	RCC_CFGR_SW_HSISYS = 0x0
	// HSE clock selected
	RCC_CFGR_SW_HSE = 0x1
	// PLLRCLK clock selected
	RCC_CFGR_SW_PLLR = 0x2
	// LSI clock selected
	RCC_CFGR_SW_LSI = 0x3
	// LSE clock selected
	RCC_CFGR_SW_LSE = 0x4

	// PLLCFGR: PLL configuration register
	// Position of PLLSRC field.
	RCC_PLLCFGR_PLLSRC_Pos = 0x0
	// Bit mask of PLLSRC field.
	RCC_PLLCFGR_PLLSRC_Msk = 0x3
	// No clock selected (saves power)
	RCC_PLLCFGR_PLLSRC_NoClock = 0x0
	// HSI16 clock selected
	RCC_PLLCFGR_PLLSRC_HSI16 = 0x2
	// HSE clock selected
	RCC_PLLCFGR_PLLSRC_HSE = 0x3
	// Position of PLLM field.
	RCC_PLLCFGR_PLLM_Pos = 0x4
	// Bit mask of PLLM field.
	RCC_PLLCFGR_PLLM_Msk = 0x70
	// Position of PLLN field.
	RCC_PLLCFGR_PLLN_Pos = 0x8
	// Bit mask of PLLN field.
	RCC_PLLCFGR_PLLN_Msk = 0xff00
	// Position of PLLPEN field.
	RCC_PLLCFGR_PLLPEN_Pos = 0x10
	// Bit mask of PLLPEN field.
	RCC_PLLCFGR_PLLPEN_Msk = 0x10000
	// Bit PLLPEN.
	RCC_PLLCFGR_PLLPEN = 0x10000
	// PLL output disabled (saves power)
	RCC_PLLCFGR_PLLPEN_Disabled = 0x0
	// PLL output enabled
	RCC_PLLCFGR_PLLPEN_Enabled = 0x1
	// Position of PLLP field.
	RCC_PLLCFGR_PLLP_Pos = 0x11
	// Bit mask of PLLP field.
	RCC_PLLCFGR_PLLP_Msk = 0x3e0000
	// Position of PLLQEN field.
	RCC_PLLCFGR_PLLQEN_Pos = 0x18
	// Bit mask of PLLQEN field.
	RCC_PLLCFGR_PLLQEN_Msk = 0x1000000
	// Bit PLLQEN.
	RCC_PLLCFGR_PLLQEN = 0x1000000
	// PLL output disabled (saves power)
	RCC_PLLCFGR_PLLQEN_Disabled = 0x0
	// PLL output enabled
	RCC_PLLCFGR_PLLQEN_Enabled = 0x1
	// Position of PLLQ field.
	RCC_PLLCFGR_PLLQ_Pos = 0x19
	// Bit mask of PLLQ field.
	RCC_PLLCFGR_PLLQ_Msk = 0xe000000
	// Position of PLLREN field.
	RCC_PLLCFGR_PLLREN_Pos = 0x1c
	// Bit mask of PLLREN field.
	RCC_PLLCFGR_PLLREN_Msk = 0x10000000
	// Bit PLLREN.
	RCC_PLLCFGR_PLLREN = 0x10000000
	// PLL output disabled (saves power)
	RCC_PLLCFGR_PLLREN_Disabled = 0x0
	// PLL output enabled
	RCC_PLLCFGR_PLLREN_Enabled = 0x1
	// Position of PLLR field.
	RCC_PLLCFGR_PLLR_Pos = 0x1d
	// Bit mask of PLLR field.
	RCC_PLLCFGR_PLLR_Msk = 0xe0000000

	// CIER: Clock interrupt enable register
	// Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_CIER_LSIRDYIE = 0x1
	// Interrupt disabled
	RCC_CIER_LSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSIRDYIE_Enabled = 0x1
	// Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_CIER_LSERDYIE = 0x2
	// Interrupt disabled
	RCC_CIER_LSERDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSERDYIE_Enabled = 0x1
	// Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Pos = 0x3
	// Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk = 0x8
	// Bit HSIRDYIE.
	RCC_CIER_HSIRDYIE = 0x8
	// Interrupt disabled
	RCC_CIER_HSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSIRDYIE_Enabled = 0x1
	// Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Pos = 0x4
	// Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk = 0x10
	// Bit HSERDYIE.
	RCC_CIER_HSERDYIE = 0x10
	// Interrupt disabled
	RCC_CIER_HSERDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSERDYIE_Enabled = 0x1
	// Position of PLLSYSRDYIE field.
	RCC_CIER_PLLSYSRDYIE_Pos = 0x5
	// Bit mask of PLLSYSRDYIE field.
	RCC_CIER_PLLSYSRDYIE_Msk = 0x20
	// Bit PLLSYSRDYIE.
	RCC_CIER_PLLSYSRDYIE = 0x20
	// Interrupt disabled
	RCC_CIER_PLLSYSRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLLSYSRDYIE_Enabled = 0x1

	// CIFR: Clock interrupt flag register
	// Position of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Pos = 0x0
	// Bit mask of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Msk = 0x1
	// Bit LSIRDYF.
	RCC_CIFR_LSIRDYF = 0x1
	// Interrupt not triggered
	RCC_CIFR_LSIRDYF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_LSIRDYF_Interrupted = 0x1
	// Position of LSERDYF field.
	RCC_CIFR_LSERDYF_Pos = 0x1
	// Bit mask of LSERDYF field.
	RCC_CIFR_LSERDYF_Msk = 0x2
	// Bit LSERDYF.
	RCC_CIFR_LSERDYF = 0x2
	// Interrupt not triggered
	RCC_CIFR_LSERDYF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_LSERDYF_Interrupted = 0x1
	// Position of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Pos = 0x3
	// Bit mask of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Msk = 0x8
	// Bit HSIRDYF.
	RCC_CIFR_HSIRDYF = 0x8
	// Interrupt not triggered
	RCC_CIFR_HSIRDYF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_HSIRDYF_Interrupted = 0x1
	// Position of HSERDYF field.
	RCC_CIFR_HSERDYF_Pos = 0x4
	// Bit mask of HSERDYF field.
	RCC_CIFR_HSERDYF_Msk = 0x10
	// Bit HSERDYF.
	RCC_CIFR_HSERDYF = 0x10
	// Interrupt not triggered
	RCC_CIFR_HSERDYF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_HSERDYF_Interrupted = 0x1
	// Position of PLLSYSRDYF field.
	RCC_CIFR_PLLSYSRDYF_Pos = 0x5
	// Bit mask of PLLSYSRDYF field.
	RCC_CIFR_PLLSYSRDYF_Msk = 0x20
	// Bit PLLSYSRDYF.
	RCC_CIFR_PLLSYSRDYF = 0x20
	// Interrupt not triggered
	RCC_CIFR_PLLSYSRDYF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_PLLSYSRDYF_Interrupted = 0x1
	// Position of CSSF field.
	RCC_CIFR_CSSF_Pos = 0x8
	// Bit mask of CSSF field.
	RCC_CIFR_CSSF_Msk = 0x100
	// Bit CSSF.
	RCC_CIFR_CSSF = 0x100
	// Interrupt not triggered
	RCC_CIFR_CSSF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_CSSF_Interrupted = 0x1
	// Position of LSECSSF field.
	RCC_CIFR_LSECSSF_Pos = 0x9
	// Bit mask of LSECSSF field.
	RCC_CIFR_LSECSSF_Msk = 0x200
	// Bit LSECSSF.
	RCC_CIFR_LSECSSF = 0x200
	// Interrupt not triggered
	RCC_CIFR_LSECSSF_NotInterrupted = 0x0
	// Interrup triggered
	RCC_CIFR_LSECSSF_Interrupted = 0x1

	// CICR: Clock interrupt clear register
	// Position of LSIRDYC field.
	RCC_CICR_LSIRDYC_Pos = 0x0
	// Bit mask of LSIRDYC field.
	RCC_CICR_LSIRDYC_Msk = 0x1
	// Bit LSIRDYC.
	RCC_CICR_LSIRDYC = 0x1
	// Clear interrupt flag
	RCC_CICR_LSIRDYC_Clear = 0x1
	// Position of LSERDYC field.
	RCC_CICR_LSERDYC_Pos = 0x1
	// Bit mask of LSERDYC field.
	RCC_CICR_LSERDYC_Msk = 0x2
	// Bit LSERDYC.
	RCC_CICR_LSERDYC = 0x2
	// Clear interrupt flag
	RCC_CICR_LSERDYC_Clear = 0x1
	// Position of HSIRDYC field.
	RCC_CICR_HSIRDYC_Pos = 0x3
	// Bit mask of HSIRDYC field.
	RCC_CICR_HSIRDYC_Msk = 0x8
	// Bit HSIRDYC.
	RCC_CICR_HSIRDYC = 0x8
	// Clear interrupt flag
	RCC_CICR_HSIRDYC_Clear = 0x1
	// Position of HSERDYC field.
	RCC_CICR_HSERDYC_Pos = 0x4
	// Bit mask of HSERDYC field.
	RCC_CICR_HSERDYC_Msk = 0x10
	// Bit HSERDYC.
	RCC_CICR_HSERDYC = 0x10
	// Clear interrupt flag
	RCC_CICR_HSERDYC_Clear = 0x1
	// Position of PLLSYSRDYC field.
	RCC_CICR_PLLSYSRDYC_Pos = 0x5
	// Bit mask of PLLSYSRDYC field.
	RCC_CICR_PLLSYSRDYC_Msk = 0x20
	// Bit PLLSYSRDYC.
	RCC_CICR_PLLSYSRDYC = 0x20
	// Clear interrupt flag
	RCC_CICR_PLLSYSRDYC_Clear = 0x1
	// Position of CSSC field.
	RCC_CICR_CSSC_Pos = 0x8
	// Bit mask of CSSC field.
	RCC_CICR_CSSC_Msk = 0x100
	// Bit CSSC.
	RCC_CICR_CSSC = 0x100
	// Clear interrupt flag
	RCC_CICR_CSSC_Clear = 0x1
	// Position of LSECSSC field.
	RCC_CICR_LSECSSC_Pos = 0x9
	// Bit mask of LSECSSC field.
	RCC_CICR_LSECSSC_Msk = 0x200
	// Bit LSECSSC.
	RCC_CICR_LSECSSC = 0x200
	// Clear interrupt flag
	RCC_CICR_LSECSSC_Clear = 0x1

	// IOPRSTR: I/O port reset register
	// Position of GPIOARST field.
	RCC_IOPRSTR_GPIOARST_Pos = 0x0
	// Bit mask of GPIOARST field.
	RCC_IOPRSTR_GPIOARST_Msk = 0x1
	// Bit GPIOARST.
	RCC_IOPRSTR_GPIOARST = 0x1
	// Reset peripheral
	RCC_IOPRSTR_GPIOARST_Reset = 0x1
	// Position of GPIOBRST field.
	RCC_IOPRSTR_GPIOBRST_Pos = 0x1
	// Bit mask of GPIOBRST field.
	RCC_IOPRSTR_GPIOBRST_Msk = 0x2
	// Bit GPIOBRST.
	RCC_IOPRSTR_GPIOBRST = 0x2
	// Reset peripheral
	RCC_IOPRSTR_GPIOBRST_Reset = 0x1
	// Position of GPIOCRST field.
	RCC_IOPRSTR_GPIOCRST_Pos = 0x2
	// Bit mask of GPIOCRST field.
	RCC_IOPRSTR_GPIOCRST_Msk = 0x4
	// Bit GPIOCRST.
	RCC_IOPRSTR_GPIOCRST = 0x4
	// Reset peripheral
	RCC_IOPRSTR_GPIOCRST_Reset = 0x1
	// Position of GPIODRST field.
	RCC_IOPRSTR_GPIODRST_Pos = 0x3
	// Bit mask of GPIODRST field.
	RCC_IOPRSTR_GPIODRST_Msk = 0x8
	// Bit GPIODRST.
	RCC_IOPRSTR_GPIODRST = 0x8
	// Reset peripheral
	RCC_IOPRSTR_GPIODRST_Reset = 0x1
	// Position of GPIOERST field.
	RCC_IOPRSTR_GPIOERST_Pos = 0x4
	// Bit mask of GPIOERST field.
	RCC_IOPRSTR_GPIOERST_Msk = 0x10
	// Bit GPIOERST.
	RCC_IOPRSTR_GPIOERST = 0x10
	// Reset peripheral
	RCC_IOPRSTR_GPIOERST_Reset = 0x1
	// Position of GPIOFRST field.
	RCC_IOPRSTR_GPIOFRST_Pos = 0x5
	// Bit mask of GPIOFRST field.
	RCC_IOPRSTR_GPIOFRST_Msk = 0x20
	// Bit GPIOFRST.
	RCC_IOPRSTR_GPIOFRST = 0x20
	// Reset peripheral
	RCC_IOPRSTR_GPIOFRST_Reset = 0x1

	// AHBRSTR: AHB peripheral reset register
	// Position of DMA1RST field.
	RCC_AHBRSTR_DMA1RST_Pos = 0x0
	// Bit mask of DMA1RST field.
	RCC_AHBRSTR_DMA1RST_Msk = 0x1
	// Bit DMA1RST.
	RCC_AHBRSTR_DMA1RST = 0x1
	// Reset peripheral
	RCC_AHBRSTR_DMA1RST_Reset = 0x1
	// Position of FLASHRST field.
	RCC_AHBRSTR_FLASHRST_Pos = 0x8
	// Bit mask of FLASHRST field.
	RCC_AHBRSTR_FLASHRST_Msk = 0x100
	// Bit FLASHRST.
	RCC_AHBRSTR_FLASHRST = 0x100
	// Reset peripheral
	RCC_AHBRSTR_FLASHRST_Reset = 0x1
	// Position of CRCRST field.
	RCC_AHBRSTR_CRCRST_Pos = 0xc
	// Bit mask of CRCRST field.
	RCC_AHBRSTR_CRCRST_Msk = 0x1000
	// Bit CRCRST.
	RCC_AHBRSTR_CRCRST = 0x1000
	// Reset peripheral
	RCC_AHBRSTR_CRCRST_Reset = 0x1

	// APBRSTR1: APB peripheral reset register 1
	// Position of TIM3RST field.
	RCC_APBRSTR1_TIM3RST_Pos = 0x1
	// Bit mask of TIM3RST field.
	RCC_APBRSTR1_TIM3RST_Msk = 0x2
	// Bit TIM3RST.
	RCC_APBRSTR1_TIM3RST = 0x2
	// Reset peripheral
	RCC_APBRSTR1_TIM3RST_Reset = 0x1
	// Position of TIM6RST field.
	RCC_APBRSTR1_TIM6RST_Pos = 0x4
	// Bit mask of TIM6RST field.
	RCC_APBRSTR1_TIM6RST_Msk = 0x10
	// Bit TIM6RST.
	RCC_APBRSTR1_TIM6RST = 0x10
	// Reset peripheral
	RCC_APBRSTR1_TIM6RST_Reset = 0x1
	// Position of TIM7RST field.
	RCC_APBRSTR1_TIM7RST_Pos = 0x5
	// Bit mask of TIM7RST field.
	RCC_APBRSTR1_TIM7RST_Msk = 0x20
	// Bit TIM7RST.
	RCC_APBRSTR1_TIM7RST = 0x20
	// Reset peripheral
	RCC_APBRSTR1_TIM7RST_Reset = 0x1
	// Position of SPI2RST field.
	RCC_APBRSTR1_SPI2RST_Pos = 0xe
	// Bit mask of SPI2RST field.
	RCC_APBRSTR1_SPI2RST_Msk = 0x4000
	// Bit SPI2RST.
	RCC_APBRSTR1_SPI2RST = 0x4000
	// Reset peripheral
	RCC_APBRSTR1_SPI2RST_Reset = 0x1
	// Position of USART2RST field.
	RCC_APBRSTR1_USART2RST_Pos = 0x11
	// Bit mask of USART2RST field.
	RCC_APBRSTR1_USART2RST_Msk = 0x20000
	// Bit USART2RST.
	RCC_APBRSTR1_USART2RST = 0x20000
	// Reset peripheral
	RCC_APBRSTR1_USART2RST_Reset = 0x1
	// Position of I2C1RST field.
	RCC_APBRSTR1_I2C1RST_Pos = 0x15
	// Bit mask of I2C1RST field.
	RCC_APBRSTR1_I2C1RST_Msk = 0x200000
	// Bit I2C1RST.
	RCC_APBRSTR1_I2C1RST = 0x200000
	// Reset peripheral
	RCC_APBRSTR1_I2C1RST_Reset = 0x1
	// Position of I2C2RST field.
	RCC_APBRSTR1_I2C2RST_Pos = 0x16
	// Bit mask of I2C2RST field.
	RCC_APBRSTR1_I2C2RST_Msk = 0x400000
	// Bit I2C2RST.
	RCC_APBRSTR1_I2C2RST = 0x400000
	// Reset peripheral
	RCC_APBRSTR1_I2C2RST_Reset = 0x1
	// Position of DBGRST field.
	RCC_APBRSTR1_DBGRST_Pos = 0x1b
	// Bit mask of DBGRST field.
	RCC_APBRSTR1_DBGRST_Msk = 0x8000000
	// Bit DBGRST.
	RCC_APBRSTR1_DBGRST = 0x8000000
	// Reset peripheral
	RCC_APBRSTR1_DBGRST_Reset = 0x1
	// Position of PWRRST field.
	RCC_APBRSTR1_PWRRST_Pos = 0x1c
	// Bit mask of PWRRST field.
	RCC_APBRSTR1_PWRRST_Msk = 0x10000000
	// Bit PWRRST.
	RCC_APBRSTR1_PWRRST = 0x10000000
	// Reset peripheral
	RCC_APBRSTR1_PWRRST_Reset = 0x1

	// APBRSTR2: APB peripheral reset register 2
	// Position of SYSCFGRST field.
	RCC_APBRSTR2_SYSCFGRST_Pos = 0x0
	// Bit mask of SYSCFGRST field.
	RCC_APBRSTR2_SYSCFGRST_Msk = 0x1
	// Bit SYSCFGRST.
	RCC_APBRSTR2_SYSCFGRST = 0x1
	// Reset peripheral
	RCC_APBRSTR2_SYSCFGRST_Reset = 0x1
	// Position of TIM1RST field.
	RCC_APBRSTR2_TIM1RST_Pos = 0xb
	// Bit mask of TIM1RST field.
	RCC_APBRSTR2_TIM1RST_Msk = 0x800
	// Bit TIM1RST.
	RCC_APBRSTR2_TIM1RST = 0x800
	// Reset peripheral
	RCC_APBRSTR2_TIM1RST_Reset = 0x1
	// Position of SPI1RST field.
	RCC_APBRSTR2_SPI1RST_Pos = 0xc
	// Bit mask of SPI1RST field.
	RCC_APBRSTR2_SPI1RST_Msk = 0x1000
	// Bit SPI1RST.
	RCC_APBRSTR2_SPI1RST = 0x1000
	// Reset peripheral
	RCC_APBRSTR2_SPI1RST_Reset = 0x1
	// Position of USART1RST field.
	RCC_APBRSTR2_USART1RST_Pos = 0xe
	// Bit mask of USART1RST field.
	RCC_APBRSTR2_USART1RST_Msk = 0x4000
	// Bit USART1RST.
	RCC_APBRSTR2_USART1RST = 0x4000
	// Reset peripheral
	RCC_APBRSTR2_USART1RST_Reset = 0x1
	// Position of TIM14RST field.
	RCC_APBRSTR2_TIM14RST_Pos = 0xf
	// Bit mask of TIM14RST field.
	RCC_APBRSTR2_TIM14RST_Msk = 0x8000
	// Bit TIM14RST.
	RCC_APBRSTR2_TIM14RST = 0x8000
	// Reset peripheral
	RCC_APBRSTR2_TIM14RST_Reset = 0x1
	// Position of TIM15RST field.
	RCC_APBRSTR2_TIM15RST_Pos = 0x10
	// Bit mask of TIM15RST field.
	RCC_APBRSTR2_TIM15RST_Msk = 0x10000
	// Bit TIM15RST.
	RCC_APBRSTR2_TIM15RST = 0x10000
	// Reset peripheral
	RCC_APBRSTR2_TIM15RST_Reset = 0x1
	// Position of TIM16RST field.
	RCC_APBRSTR2_TIM16RST_Pos = 0x11
	// Bit mask of TIM16RST field.
	RCC_APBRSTR2_TIM16RST_Msk = 0x20000
	// Bit TIM16RST.
	RCC_APBRSTR2_TIM16RST = 0x20000
	// Reset peripheral
	RCC_APBRSTR2_TIM16RST_Reset = 0x1
	// Position of TIM17RST field.
	RCC_APBRSTR2_TIM17RST_Pos = 0x12
	// Bit mask of TIM17RST field.
	RCC_APBRSTR2_TIM17RST_Msk = 0x40000
	// Bit TIM17RST.
	RCC_APBRSTR2_TIM17RST = 0x40000
	// Reset peripheral
	RCC_APBRSTR2_TIM17RST_Reset = 0x1
	// Position of ADCRST field.
	RCC_APBRSTR2_ADCRST_Pos = 0x14
	// Bit mask of ADCRST field.
	RCC_APBRSTR2_ADCRST_Msk = 0x100000
	// Bit ADCRST.
	RCC_APBRSTR2_ADCRST = 0x100000
	// Reset peripheral
	RCC_APBRSTR2_ADCRST_Reset = 0x1

	// IOPENR: GPIO clock enable register
	// Position of GPIOAEN field.
	RCC_IOPENR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_IOPENR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_IOPENR_GPIOAEN = 0x1
	// Peripheral disabled (typically saves power)
	RCC_IOPENR_GPIOAEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPENR_GPIOAEN_Enabled = 0x1
	// Position of GPIOBEN field.
	RCC_IOPENR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_IOPENR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_IOPENR_GPIOBEN = 0x2
	// Peripheral disabled (typically saves power)
	RCC_IOPENR_GPIOBEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPENR_GPIOBEN_Enabled = 0x1
	// Position of GPIOCEN field.
	RCC_IOPENR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_IOPENR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_IOPENR_GPIOCEN = 0x4
	// Peripheral disabled (typically saves power)
	RCC_IOPENR_GPIOCEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPENR_GPIOCEN_Enabled = 0x1
	// Position of GPIODEN field.
	RCC_IOPENR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_IOPENR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_IOPENR_GPIODEN = 0x8
	// Peripheral disabled (typically saves power)
	RCC_IOPENR_GPIODEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPENR_GPIODEN_Enabled = 0x1
	// Position of GPIOEEN field.
	RCC_IOPENR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_IOPENR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_IOPENR_GPIOEEN = 0x10
	// Peripheral disabled (typically saves power)
	RCC_IOPENR_GPIOEEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPENR_GPIOEEN_Enabled = 0x1
	// Position of GPIOFEN field.
	RCC_IOPENR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_IOPENR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_IOPENR_GPIOFEN = 0x20
	// Peripheral disabled (typically saves power)
	RCC_IOPENR_GPIOFEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPENR_GPIOFEN_Enabled = 0x1

	// AHBENR: AHB peripheral clock enable register
	// Position of DMA1EN field.
	RCC_AHBENR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_AHBENR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_AHBENR_DMA1EN = 0x1
	// Peripheral disabled (typically saves power)
	RCC_AHBENR_DMA1EN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBENR_DMA1EN_Enabled = 0x1
	// Position of FLASHEN field.
	RCC_AHBENR_FLASHEN_Pos = 0x8
	// Bit mask of FLASHEN field.
	RCC_AHBENR_FLASHEN_Msk = 0x100
	// Bit FLASHEN.
	RCC_AHBENR_FLASHEN = 0x100
	// Peripheral disabled (typically saves power)
	RCC_AHBENR_FLASHEN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBENR_FLASHEN_Enabled = 0x1
	// Position of CRCEN field.
	RCC_AHBENR_CRCEN_Pos = 0xc
	// Bit mask of CRCEN field.
	RCC_AHBENR_CRCEN_Msk = 0x1000
	// Bit CRCEN.
	RCC_AHBENR_CRCEN = 0x1000
	// Peripheral disabled (typically saves power)
	RCC_AHBENR_CRCEN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBENR_CRCEN_Enabled = 0x1

	// APBENR1: APB peripheral clock enable register 1
	// Position of TIM3EN field.
	RCC_APBENR1_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_APBENR1_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_APBENR1_TIM3EN = 0x2
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_TIM3EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_TIM3EN_Enabled = 0x1
	// Position of TIM6EN field.
	RCC_APBENR1_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_APBENR1_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_APBENR1_TIM6EN = 0x10
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_TIM6EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_TIM6EN_Enabled = 0x1
	// Position of TIM7EN field.
	RCC_APBENR1_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_APBENR1_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_APBENR1_TIM7EN = 0x20
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_TIM7EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_TIM7EN_Enabled = 0x1
	// Position of RTCAPBEN field.
	RCC_APBENR1_RTCAPBEN_Pos = 0xa
	// Bit mask of RTCAPBEN field.
	RCC_APBENR1_RTCAPBEN_Msk = 0x400
	// Bit RTCAPBEN.
	RCC_APBENR1_RTCAPBEN = 0x400
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_RTCAPBEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_RTCAPBEN_Enabled = 0x1
	// Position of WWDGEN field.
	RCC_APBENR1_WWDGEN_Pos = 0xb
	// Bit mask of WWDGEN field.
	RCC_APBENR1_WWDGEN_Msk = 0x800
	// Bit WWDGEN.
	RCC_APBENR1_WWDGEN = 0x800
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_WWDGEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_WWDGEN_Enabled = 0x1
	// Position of SPI2EN field.
	RCC_APBENR1_SPI2EN_Pos = 0xe
	// Bit mask of SPI2EN field.
	RCC_APBENR1_SPI2EN_Msk = 0x4000
	// Bit SPI2EN.
	RCC_APBENR1_SPI2EN = 0x4000
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_SPI2EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_SPI2EN_Enabled = 0x1
	// Position of USART2EN field.
	RCC_APBENR1_USART2EN_Pos = 0x11
	// Bit mask of USART2EN field.
	RCC_APBENR1_USART2EN_Msk = 0x20000
	// Bit USART2EN.
	RCC_APBENR1_USART2EN = 0x20000
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_USART2EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_USART2EN_Enabled = 0x1
	// Position of I2C1EN field.
	RCC_APBENR1_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_APBENR1_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_APBENR1_I2C1EN = 0x200000
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_I2C1EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_I2C1EN_Enabled = 0x1
	// Position of I2C2EN field.
	RCC_APBENR1_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_APBENR1_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_APBENR1_I2C2EN = 0x400000
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_I2C2EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_I2C2EN_Enabled = 0x1
	// Position of DBGEN field.
	RCC_APBENR1_DBGEN_Pos = 0x1b
	// Bit mask of DBGEN field.
	RCC_APBENR1_DBGEN_Msk = 0x8000000
	// Bit DBGEN.
	RCC_APBENR1_DBGEN = 0x8000000
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_DBGEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_DBGEN_Enabled = 0x1
	// Position of PWREN field.
	RCC_APBENR1_PWREN_Pos = 0x1c
	// Bit mask of PWREN field.
	RCC_APBENR1_PWREN_Msk = 0x10000000
	// Bit PWREN.
	RCC_APBENR1_PWREN = 0x10000000
	// Peripheral disabled (typically saves power)
	RCC_APBENR1_PWREN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR1_PWREN_Enabled = 0x1

	// APBENR2: APB peripheral clock enable register 2
	// Position of SYSCFGEN field.
	RCC_APBENR2_SYSCFGEN_Pos = 0x0
	// Bit mask of SYSCFGEN field.
	RCC_APBENR2_SYSCFGEN_Msk = 0x1
	// Bit SYSCFGEN.
	RCC_APBENR2_SYSCFGEN = 0x1
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_SYSCFGEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_SYSCFGEN_Enabled = 0x1
	// Position of TIM1EN field.
	RCC_APBENR2_TIM1EN_Pos = 0xb
	// Bit mask of TIM1EN field.
	RCC_APBENR2_TIM1EN_Msk = 0x800
	// Bit TIM1EN.
	RCC_APBENR2_TIM1EN = 0x800
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_TIM1EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_TIM1EN_Enabled = 0x1
	// Position of SPI1EN field.
	RCC_APBENR2_SPI1EN_Pos = 0xc
	// Bit mask of SPI1EN field.
	RCC_APBENR2_SPI1EN_Msk = 0x1000
	// Bit SPI1EN.
	RCC_APBENR2_SPI1EN = 0x1000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_SPI1EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_SPI1EN_Enabled = 0x1
	// Position of USART1EN field.
	RCC_APBENR2_USART1EN_Pos = 0xe
	// Bit mask of USART1EN field.
	RCC_APBENR2_USART1EN_Msk = 0x4000
	// Bit USART1EN.
	RCC_APBENR2_USART1EN = 0x4000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_USART1EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_USART1EN_Enabled = 0x1
	// Position of TIM14EN field.
	RCC_APBENR2_TIM14EN_Pos = 0xf
	// Bit mask of TIM14EN field.
	RCC_APBENR2_TIM14EN_Msk = 0x8000
	// Bit TIM14EN.
	RCC_APBENR2_TIM14EN = 0x8000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_TIM14EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_TIM14EN_Enabled = 0x1
	// Position of TIM15EN field.
	RCC_APBENR2_TIM15EN_Pos = 0x10
	// Bit mask of TIM15EN field.
	RCC_APBENR2_TIM15EN_Msk = 0x10000
	// Bit TIM15EN.
	RCC_APBENR2_TIM15EN = 0x10000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_TIM15EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_TIM15EN_Enabled = 0x1
	// Position of TIM16EN field.
	RCC_APBENR2_TIM16EN_Pos = 0x11
	// Bit mask of TIM16EN field.
	RCC_APBENR2_TIM16EN_Msk = 0x20000
	// Bit TIM16EN.
	RCC_APBENR2_TIM16EN = 0x20000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_TIM16EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_TIM16EN_Enabled = 0x1
	// Position of TIM17EN field.
	RCC_APBENR2_TIM17EN_Pos = 0x12
	// Bit mask of TIM17EN field.
	RCC_APBENR2_TIM17EN_Msk = 0x40000
	// Bit TIM17EN.
	RCC_APBENR2_TIM17EN = 0x40000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_TIM17EN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_TIM17EN_Enabled = 0x1
	// Position of ADCEN field.
	RCC_APBENR2_ADCEN_Pos = 0x14
	// Bit mask of ADCEN field.
	RCC_APBENR2_ADCEN_Msk = 0x100000
	// Bit ADCEN.
	RCC_APBENR2_ADCEN = 0x100000
	// Peripheral disabled (typically saves power)
	RCC_APBENR2_ADCEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBENR2_ADCEN_Enabled = 0x1

	// IOPSMENR: GPIO in Sleep mode clock enable register
	// Position of GPIOASMEN field.
	RCC_IOPSMENR_GPIOASMEN_Pos = 0x0
	// Bit mask of GPIOASMEN field.
	RCC_IOPSMENR_GPIOASMEN_Msk = 0x1
	// Bit GPIOASMEN.
	RCC_IOPSMENR_GPIOASMEN = 0x1
	// Peripheral disabled (typically saves power)
	RCC_IOPSMENR_GPIOASMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPSMENR_GPIOASMEN_Enabled = 0x1
	// Position of GPIOBSMEN field.
	RCC_IOPSMENR_GPIOBSMEN_Pos = 0x1
	// Bit mask of GPIOBSMEN field.
	RCC_IOPSMENR_GPIOBSMEN_Msk = 0x2
	// Bit GPIOBSMEN.
	RCC_IOPSMENR_GPIOBSMEN = 0x2
	// Peripheral disabled (typically saves power)
	RCC_IOPSMENR_GPIOBSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPSMENR_GPIOBSMEN_Enabled = 0x1
	// Position of GPIOCSMEN field.
	RCC_IOPSMENR_GPIOCSMEN_Pos = 0x2
	// Bit mask of GPIOCSMEN field.
	RCC_IOPSMENR_GPIOCSMEN_Msk = 0x4
	// Bit GPIOCSMEN.
	RCC_IOPSMENR_GPIOCSMEN = 0x4
	// Peripheral disabled (typically saves power)
	RCC_IOPSMENR_GPIOCSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPSMENR_GPIOCSMEN_Enabled = 0x1
	// Position of GPIODSMEN field.
	RCC_IOPSMENR_GPIODSMEN_Pos = 0x3
	// Bit mask of GPIODSMEN field.
	RCC_IOPSMENR_GPIODSMEN_Msk = 0x8
	// Bit GPIODSMEN.
	RCC_IOPSMENR_GPIODSMEN = 0x8
	// Peripheral disabled (typically saves power)
	RCC_IOPSMENR_GPIODSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPSMENR_GPIODSMEN_Enabled = 0x1
	// Position of GPIOESMEN field.
	RCC_IOPSMENR_GPIOESMEN_Pos = 0x4
	// Bit mask of GPIOESMEN field.
	RCC_IOPSMENR_GPIOESMEN_Msk = 0x10
	// Bit GPIOESMEN.
	RCC_IOPSMENR_GPIOESMEN = 0x10
	// Peripheral disabled (typically saves power)
	RCC_IOPSMENR_GPIOESMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPSMENR_GPIOESMEN_Enabled = 0x1
	// Position of GPIOFSMEN field.
	RCC_IOPSMENR_GPIOFSMEN_Pos = 0x5
	// Bit mask of GPIOFSMEN field.
	RCC_IOPSMENR_GPIOFSMEN_Msk = 0x20
	// Bit GPIOFSMEN.
	RCC_IOPSMENR_GPIOFSMEN = 0x20
	// Peripheral disabled (typically saves power)
	RCC_IOPSMENR_GPIOFSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_IOPSMENR_GPIOFSMEN_Enabled = 0x1

	// AHBSMENR: AHB peripheral clock enable in Sleep mode register
	// Position of DMA1SMEN field.
	RCC_AHBSMENR_DMA1SMEN_Pos = 0x0
	// Bit mask of DMA1SMEN field.
	RCC_AHBSMENR_DMA1SMEN_Msk = 0x1
	// Bit DMA1SMEN.
	RCC_AHBSMENR_DMA1SMEN = 0x1
	// Peripheral disabled (typically saves power)
	RCC_AHBSMENR_DMA1SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBSMENR_DMA1SMEN_Enabled = 0x1
	// Position of FLASHSMEN field.
	RCC_AHBSMENR_FLASHSMEN_Pos = 0x8
	// Bit mask of FLASHSMEN field.
	RCC_AHBSMENR_FLASHSMEN_Msk = 0x100
	// Bit FLASHSMEN.
	RCC_AHBSMENR_FLASHSMEN = 0x100
	// Peripheral disabled (typically saves power)
	RCC_AHBSMENR_FLASHSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBSMENR_FLASHSMEN_Enabled = 0x1
	// Position of SRAMSMEN field.
	RCC_AHBSMENR_SRAMSMEN_Pos = 0x9
	// Bit mask of SRAMSMEN field.
	RCC_AHBSMENR_SRAMSMEN_Msk = 0x200
	// Bit SRAMSMEN.
	RCC_AHBSMENR_SRAMSMEN = 0x200
	// Peripheral disabled (typically saves power)
	RCC_AHBSMENR_SRAMSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBSMENR_SRAMSMEN_Enabled = 0x1
	// Position of CRCSMEN field.
	RCC_AHBSMENR_CRCSMEN_Pos = 0xc
	// Bit mask of CRCSMEN field.
	RCC_AHBSMENR_CRCSMEN_Msk = 0x1000
	// Bit CRCSMEN.
	RCC_AHBSMENR_CRCSMEN = 0x1000
	// Peripheral disabled (typically saves power)
	RCC_AHBSMENR_CRCSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_AHBSMENR_CRCSMEN_Enabled = 0x1

	// APBSMENR1: APB peripheral clock enable in Sleep mode register 1
	// Position of TIM3SMEN field.
	RCC_APBSMENR1_TIM3SMEN_Pos = 0x1
	// Bit mask of TIM3SMEN field.
	RCC_APBSMENR1_TIM3SMEN_Msk = 0x2
	// Bit TIM3SMEN.
	RCC_APBSMENR1_TIM3SMEN = 0x2
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_TIM3SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_TIM3SMEN_Enabled = 0x1
	// Position of TIM6SMEN field.
	RCC_APBSMENR1_TIM6SMEN_Pos = 0x4
	// Bit mask of TIM6SMEN field.
	RCC_APBSMENR1_TIM6SMEN_Msk = 0x10
	// Bit TIM6SMEN.
	RCC_APBSMENR1_TIM6SMEN = 0x10
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_TIM6SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_TIM6SMEN_Enabled = 0x1
	// Position of TIM7SMEN field.
	RCC_APBSMENR1_TIM7SMEN_Pos = 0x5
	// Bit mask of TIM7SMEN field.
	RCC_APBSMENR1_TIM7SMEN_Msk = 0x20
	// Bit TIM7SMEN.
	RCC_APBSMENR1_TIM7SMEN = 0x20
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_TIM7SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_TIM7SMEN_Enabled = 0x1
	// Position of RTCAPBSMEN field.
	RCC_APBSMENR1_RTCAPBSMEN_Pos = 0xa
	// Bit mask of RTCAPBSMEN field.
	RCC_APBSMENR1_RTCAPBSMEN_Msk = 0x400
	// Bit RTCAPBSMEN.
	RCC_APBSMENR1_RTCAPBSMEN = 0x400
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_RTCAPBSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_RTCAPBSMEN_Enabled = 0x1
	// Position of WWDGSMEN field.
	RCC_APBSMENR1_WWDGSMEN_Pos = 0xb
	// Bit mask of WWDGSMEN field.
	RCC_APBSMENR1_WWDGSMEN_Msk = 0x800
	// Bit WWDGSMEN.
	RCC_APBSMENR1_WWDGSMEN = 0x800
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_WWDGSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_WWDGSMEN_Enabled = 0x1
	// Position of SPI2SMEN field.
	RCC_APBSMENR1_SPI2SMEN_Pos = 0xe
	// Bit mask of SPI2SMEN field.
	RCC_APBSMENR1_SPI2SMEN_Msk = 0x4000
	// Bit SPI2SMEN.
	RCC_APBSMENR1_SPI2SMEN = 0x4000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_SPI2SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_SPI2SMEN_Enabled = 0x1
	// Position of USART2SMEN field.
	RCC_APBSMENR1_USART2SMEN_Pos = 0x11
	// Bit mask of USART2SMEN field.
	RCC_APBSMENR1_USART2SMEN_Msk = 0x20000
	// Bit USART2SMEN.
	RCC_APBSMENR1_USART2SMEN = 0x20000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_USART2SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_USART2SMEN_Enabled = 0x1
	// Position of I2C1SMEN field.
	RCC_APBSMENR1_I2C1SMEN_Pos = 0x15
	// Bit mask of I2C1SMEN field.
	RCC_APBSMENR1_I2C1SMEN_Msk = 0x200000
	// Bit I2C1SMEN.
	RCC_APBSMENR1_I2C1SMEN = 0x200000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_I2C1SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_I2C1SMEN_Enabled = 0x1
	// Position of I2C2SMEN field.
	RCC_APBSMENR1_I2C2SMEN_Pos = 0x16
	// Bit mask of I2C2SMEN field.
	RCC_APBSMENR1_I2C2SMEN_Msk = 0x400000
	// Bit I2C2SMEN.
	RCC_APBSMENR1_I2C2SMEN = 0x400000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_I2C2SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_I2C2SMEN_Enabled = 0x1
	// Position of DBGSMEN field.
	RCC_APBSMENR1_DBGSMEN_Pos = 0x1b
	// Bit mask of DBGSMEN field.
	RCC_APBSMENR1_DBGSMEN_Msk = 0x8000000
	// Bit DBGSMEN.
	RCC_APBSMENR1_DBGSMEN = 0x8000000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_DBGSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_DBGSMEN_Enabled = 0x1
	// Position of PWRSMEN field.
	RCC_APBSMENR1_PWRSMEN_Pos = 0x1c
	// Bit mask of PWRSMEN field.
	RCC_APBSMENR1_PWRSMEN_Msk = 0x10000000
	// Bit PWRSMEN.
	RCC_APBSMENR1_PWRSMEN = 0x10000000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR1_PWRSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR1_PWRSMEN_Enabled = 0x1

	// APBSMENR2: APB peripheral clock enable in Sleep mode register 2
	// Position of SYSCFGSMEN field.
	RCC_APBSMENR2_SYSCFGSMEN_Pos = 0x0
	// Bit mask of SYSCFGSMEN field.
	RCC_APBSMENR2_SYSCFGSMEN_Msk = 0x1
	// Bit SYSCFGSMEN.
	RCC_APBSMENR2_SYSCFGSMEN = 0x1
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_SYSCFGSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_SYSCFGSMEN_Enabled = 0x1
	// Position of TIM1SMEN field.
	RCC_APBSMENR2_TIM1SMEN_Pos = 0xb
	// Bit mask of TIM1SMEN field.
	RCC_APBSMENR2_TIM1SMEN_Msk = 0x800
	// Bit TIM1SMEN.
	RCC_APBSMENR2_TIM1SMEN = 0x800
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_TIM1SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_TIM1SMEN_Enabled = 0x1
	// Position of SPI1SMEN field.
	RCC_APBSMENR2_SPI1SMEN_Pos = 0xc
	// Bit mask of SPI1SMEN field.
	RCC_APBSMENR2_SPI1SMEN_Msk = 0x1000
	// Bit SPI1SMEN.
	RCC_APBSMENR2_SPI1SMEN = 0x1000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_SPI1SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_SPI1SMEN_Enabled = 0x1
	// Position of USART1SMEN field.
	RCC_APBSMENR2_USART1SMEN_Pos = 0xe
	// Bit mask of USART1SMEN field.
	RCC_APBSMENR2_USART1SMEN_Msk = 0x4000
	// Bit USART1SMEN.
	RCC_APBSMENR2_USART1SMEN = 0x4000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_USART1SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_USART1SMEN_Enabled = 0x1
	// Position of TIM14SMEN field.
	RCC_APBSMENR2_TIM14SMEN_Pos = 0xf
	// Bit mask of TIM14SMEN field.
	RCC_APBSMENR2_TIM14SMEN_Msk = 0x8000
	// Bit TIM14SMEN.
	RCC_APBSMENR2_TIM14SMEN = 0x8000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_TIM14SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_TIM14SMEN_Enabled = 0x1
	// Position of TIM15SMEN field.
	RCC_APBSMENR2_TIM15SMEN_Pos = 0x10
	// Bit mask of TIM15SMEN field.
	RCC_APBSMENR2_TIM15SMEN_Msk = 0x10000
	// Bit TIM15SMEN.
	RCC_APBSMENR2_TIM15SMEN = 0x10000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_TIM15SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_TIM15SMEN_Enabled = 0x1
	// Position of TIM16SMEN field.
	RCC_APBSMENR2_TIM16SMEN_Pos = 0x11
	// Bit mask of TIM16SMEN field.
	RCC_APBSMENR2_TIM16SMEN_Msk = 0x20000
	// Bit TIM16SMEN.
	RCC_APBSMENR2_TIM16SMEN = 0x20000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_TIM16SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_TIM16SMEN_Enabled = 0x1
	// Position of TIM17SMEN field.
	RCC_APBSMENR2_TIM17SMEN_Pos = 0x12
	// Bit mask of TIM17SMEN field.
	RCC_APBSMENR2_TIM17SMEN_Msk = 0x40000
	// Bit TIM17SMEN.
	RCC_APBSMENR2_TIM17SMEN = 0x40000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_TIM17SMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_TIM17SMEN_Enabled = 0x1
	// Position of ADCSMEN field.
	RCC_APBSMENR2_ADCSMEN_Pos = 0x14
	// Bit mask of ADCSMEN field.
	RCC_APBSMENR2_ADCSMEN_Msk = 0x100000
	// Bit ADCSMEN.
	RCC_APBSMENR2_ADCSMEN = 0x100000
	// Peripheral disabled (typically saves power)
	RCC_APBSMENR2_ADCSMEN_Disabled = 0x0
	// Peripheral enabled
	RCC_APBSMENR2_ADCSMEN_Enabled = 0x1

	// CCIPR: Peripherals independent clock configuration register
	// Position of USART1SEL field.
	RCC_CCIPR_USART1SEL_Pos = 0x0
	// Bit mask of USART1SEL field.
	RCC_CCIPR_USART1SEL_Msk = 0x3
	// PCLK clock selected
	RCC_CCIPR_USART1SEL_PCLK = 0x0
	// SYSCLK clock selected
	RCC_CCIPR_USART1SEL_SYSCLK = 0x1
	// HSI16 clock selected
	RCC_CCIPR_USART1SEL_HSI16 = 0x2
	// LSE clock selected
	RCC_CCIPR_USART1SEL_LSE = 0x3
	// Position of USART2SEL field.
	RCC_CCIPR_USART2SEL_Pos = 0x2
	// Bit mask of USART2SEL field.
	RCC_CCIPR_USART2SEL_Msk = 0xc
	// PCLK clock selected
	RCC_CCIPR_USART2SEL_PCLK = 0x0
	// SYSCLK clock selected
	RCC_CCIPR_USART2SEL_SYSCLK = 0x1
	// HSI16 clock selected
	RCC_CCIPR_USART2SEL_HSI16 = 0x2
	// LSE clock selected
	RCC_CCIPR_USART2SEL_LSE = 0x3
	// Position of I2C1SEL field.
	RCC_CCIPR_I2C1SEL_Pos = 0xc
	// Bit mask of I2C1SEL field.
	RCC_CCIPR_I2C1SEL_Msk = 0x3000
	// PCLK clock selected
	RCC_CCIPR_I2C1SEL_PCLK = 0x0
	// SYSCLK clock selected
	RCC_CCIPR_I2C1SEL_SYSCLK = 0x1
	// HSI16 clock selected
	RCC_CCIPR_I2C1SEL_HSI16 = 0x2
	// Position of I2S1SEL field.
	RCC_CCIPR_I2S1SEL_Pos = 0xe
	// Bit mask of I2S1SEL field.
	RCC_CCIPR_I2S1SEL_Msk = 0xc000
	// SYSCLK clock selected
	RCC_CCIPR_I2S1SEL_SYSCLK = 0x0
	// PLLPCLK clock selected
	RCC_CCIPR_I2S1SEL_PLLP = 0x1
	// HSI16 clock selected
	RCC_CCIPR_I2S1SEL_HSI16 = 0x2
	// I2S_CKIN clock selected
	RCC_CCIPR_I2S1SEL_CKIN = 0x3
	// Position of TIM1SEL field.
	RCC_CCIPR_TIM1SEL_Pos = 0x16
	// Bit mask of TIM1SEL field.
	RCC_CCIPR_TIM1SEL_Msk = 0x400000
	// Bit TIM1SEL.
	RCC_CCIPR_TIM1SEL = 0x400000
	// TIMPCLK clock selected
	RCC_CCIPR_TIM1SEL_TIMP = 0x0
	// PLLQCLK clock selected
	RCC_CCIPR_TIM1SEL_PLLQ = 0x1
	// Position of TIM15SEL field.
	RCC_CCIPR_TIM15SEL_Pos = 0x18
	// Bit mask of TIM15SEL field.
	RCC_CCIPR_TIM15SEL_Msk = 0x1000000
	// Bit TIM15SEL.
	RCC_CCIPR_TIM15SEL = 0x1000000
	// TIMPCLK clock selected
	RCC_CCIPR_TIM15SEL_TIMP = 0x0
	// PLLQCLK clock selected
	RCC_CCIPR_TIM15SEL_PLLQ = 0x1
	// Position of ADCSEL field.
	RCC_CCIPR_ADCSEL_Pos = 0x1e
	// Bit mask of ADCSEL field.
	RCC_CCIPR_ADCSEL_Msk = 0xc0000000
	// System clock selected
	RCC_CCIPR_ADCSEL_SYSCLK = 0x0
	// PLLPCLK clock selected
	RCC_CCIPR_ADCSEL_PLLP = 0x1
	// HSI16 clock selected
	RCC_CCIPR_ADCSEL_HSI16 = 0x2

	// BDCR: RTC domain control register
	// Position of LSEON field.
	RCC_BDCR_LSEON_Pos = 0x0
	// Bit mask of LSEON field.
	RCC_BDCR_LSEON_Msk = 0x1
	// Bit LSEON.
	RCC_BDCR_LSEON = 0x1
	// LSE oscillator powered off
	RCC_BDCR_LSEON_Disabled = 0x0
	// LSE oscillator enabled
	RCC_BDCR_LSEON_Enabled = 0x1
	// Position of LSERDY field.
	RCC_BDCR_LSERDY_Pos = 0x1
	// Bit mask of LSERDY field.
	RCC_BDCR_LSERDY_Msk = 0x2
	// Bit LSERDY.
	RCC_BDCR_LSERDY = 0x2
	// LSE oscillator not ready
	RCC_BDCR_LSERDY_NotReady = 0x0
	// LSE oscillator ready
	RCC_BDCR_LSERDY_Ready = 0x1
	// Position of LSEBYP field.
	RCC_BDCR_LSEBYP_Pos = 0x2
	// Bit mask of LSEBYP field.
	RCC_BDCR_LSEBYP_Msk = 0x4
	// Bit LSEBYP.
	RCC_BDCR_LSEBYP = 0x4
	// LSE is a crystal oscillator or ceramic resonator
	RCC_BDCR_LSEBYP_Crystal = 0x0
	// LSE is driven by an external clock
	RCC_BDCR_LSEBYP_ExtClock = 0x1
	// Position of LSEDRV field.
	RCC_BDCR_LSEDRV_Pos = 0x3
	// Bit mask of LSEDRV field.
	RCC_BDCR_LSEDRV_Msk = 0x18
	// Xtal mode lower driving capability
	RCC_BDCR_LSEDRV_Low = 0x0
	// Xtal mode medium-low driving capability
	RCC_BDCR_LSEDRV_MedLow = 0x1
	// Xtal mode medium-high driving capability
	RCC_BDCR_LSEDRV_MedHigh = 0x2
	// Xtal mode higher driving capability
	RCC_BDCR_LSEDRV_High = 0x3
	// Position of LSECSSON field.
	RCC_BDCR_LSECSSON_Pos = 0x5
	// Bit mask of LSECSSON field.
	RCC_BDCR_LSECSSON_Msk = 0x20
	// Bit LSECSSON.
	RCC_BDCR_LSECSSON = 0x20
	// LSE clock is not monitored
	RCC_BDCR_LSECSSON_Disabled = 0x0
	// LSE clock monitor enabled
	RCC_BDCR_LSECSSON_Enabled = 0x1
	// Position of LSECSSD field.
	RCC_BDCR_LSECSSD_Pos = 0x6
	// Bit mask of LSECSSD field.
	RCC_BDCR_LSECSSD_Msk = 0x40
	// Bit LSECSSD.
	RCC_BDCR_LSECSSD = 0x40
	// No failure detected
	RCC_BDCR_LSECSSD_NoFailure = 0x0
	// Failure detected
	RCC_BDCR_LSECSSD_Failure = 0x1
	// Position of RTCSEL field.
	RCC_BDCR_RTCSEL_Pos = 0x8
	// Bit mask of RTCSEL field.
	RCC_BDCR_RTCSEL_Msk = 0x300
	// No clock selected
	RCC_BDCR_RTCSEL_NoClock = 0x0
	// LSE clock selected
	RCC_BDCR_RTCSEL_LSE = 0x1
	// LSI clock selected
	RCC_BDCR_RTCSEL_LSI = 0x2
	// HSI clock divided by 32 selected
	RCC_BDCR_RTCSEL_HSE32 = 0x3
	// Position of RTCEN field.
	RCC_BDCR_RTCEN_Pos = 0xf
	// Bit mask of RTCEN field.
	RCC_BDCR_RTCEN_Msk = 0x8000
	// Bit RTCEN.
	RCC_BDCR_RTCEN = 0x8000
	// RTC disabled (saves power)
	RCC_BDCR_RTCEN_Disabled = 0x0
	// RTC enabled
	RCC_BDCR_RTCEN_Enabled = 0x1
	// Position of BDRST field.
	RCC_BDCR_BDRST_Pos = 0x10
	// Bit mask of BDRST field.
	RCC_BDCR_BDRST_Msk = 0x10000
	// Bit BDRST.
	RCC_BDCR_BDRST = 0x10000
	// RTC domain software reset
	RCC_BDCR_BDRST_Reset = 0x1
	// Position of LSCOEN field.
	RCC_BDCR_LSCOEN_Pos = 0x18
	// Bit mask of LSCOEN field.
	RCC_BDCR_LSCOEN_Msk = 0x1000000
	// Bit LSCOEN.
	RCC_BDCR_LSCOEN = 0x1000000
	// Low-speed clock output disabled
	RCC_BDCR_LSCOEN_Disabled = 0x0
	// Low-speed clock output enabled
	RCC_BDCR_LSCOEN_Enabled = 0x1
	// Position of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Pos = 0x19
	// Bit mask of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Msk = 0x2000000
	// Bit LSCOSEL.
	RCC_BDCR_LSCOSEL = 0x2000000
	// LSI clock selected
	RCC_BDCR_LSCOSEL_LSI = 0x0
	// LSE clock selected
	RCC_BDCR_LSCOSEL_LSE = 0x1

	// CSR: Control/status register
	// Position of LSION field.
	RCC_CSR_LSION_Pos = 0x0
	// Bit mask of LSION field.
	RCC_CSR_LSION_Msk = 0x1
	// Bit LSION.
	RCC_CSR_LSION = 0x1
	// LSI oscillator powered off
	RCC_CSR_LSION_Disabled = 0x0
	// LSI oscillator enabled
	RCC_CSR_LSION_Enabled = 0x1
	// Position of LSIRDY field.
	RCC_CSR_LSIRDY_Pos = 0x1
	// Bit mask of LSIRDY field.
	RCC_CSR_LSIRDY_Msk = 0x2
	// Bit LSIRDY.
	RCC_CSR_LSIRDY = 0x2
	// LSI oscillator not ready
	RCC_CSR_LSIRDY_NotReady = 0x0
	// LSI oscillator ready
	RCC_CSR_LSIRDY_Ready = 0x1
	// Position of RMVF field.
	RCC_CSR_RMVF_Pos = 0x17
	// Bit mask of RMVF field.
	RCC_CSR_RMVF_Msk = 0x800000
	// Bit RMVF.
	RCC_CSR_RMVF = 0x800000
	// Clear reset flags
	RCC_CSR_RMVF_Clear = 0x1
	// Position of OBLRSTF field.
	RCC_CSR_OBLRSTF_Pos = 0x19
	// Bit mask of OBLRSTF field.
	RCC_CSR_OBLRSTF_Msk = 0x2000000
	// Bit OBLRSTF.
	RCC_CSR_OBLRSTF = 0x2000000
	// This reset type has not occurred
	RCC_CSR_OBLRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_OBLRSTF_Reset = 0x1
	// Position of PINRSTF field.
	RCC_CSR_PINRSTF_Pos = 0x1a
	// Bit mask of PINRSTF field.
	RCC_CSR_PINRSTF_Msk = 0x4000000
	// Bit PINRSTF.
	RCC_CSR_PINRSTF = 0x4000000
	// This reset type has not occurred
	RCC_CSR_PINRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_PINRSTF_Reset = 0x1
	// Position of PWRRSTF field.
	RCC_CSR_PWRRSTF_Pos = 0x1b
	// Bit mask of PWRRSTF field.
	RCC_CSR_PWRRSTF_Msk = 0x8000000
	// Bit PWRRSTF.
	RCC_CSR_PWRRSTF = 0x8000000
	// This reset type has not occurred
	RCC_CSR_PWRRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_PWRRSTF_Reset = 0x1
	// Position of SFTRSTF field.
	RCC_CSR_SFTRSTF_Pos = 0x1c
	// Bit mask of SFTRSTF field.
	RCC_CSR_SFTRSTF_Msk = 0x10000000
	// Bit SFTRSTF.
	RCC_CSR_SFTRSTF = 0x10000000
	// This reset type has not occurred
	RCC_CSR_SFTRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_SFTRSTF_Reset = 0x1
	// Position of IWDGRSTF field.
	RCC_CSR_IWDGRSTF_Pos = 0x1d
	// Bit mask of IWDGRSTF field.
	RCC_CSR_IWDGRSTF_Msk = 0x20000000
	// Bit IWDGRSTF.
	RCC_CSR_IWDGRSTF = 0x20000000
	// This reset type has not occurred
	RCC_CSR_IWDGRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_IWDGRSTF_Reset = 0x1
	// Position of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Pos = 0x1e
	// Bit mask of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Msk = 0x40000000
	// Bit WWDGRSTF.
	RCC_CSR_WWDGRSTF = 0x40000000
	// This reset type has not occurred
	RCC_CSR_WWDGRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_WWDGRSTF_Reset = 0x1
	// Position of LPWRRSTF field.
	RCC_CSR_LPWRRSTF_Pos = 0x1f
	// Bit mask of LPWRRSTF field.
	RCC_CSR_LPWRRSTF_Msk = 0x80000000
	// Bit LPWRRSTF.
	RCC_CSR_LPWRRSTF = 0x80000000
	// This reset type has not occurred
	RCC_CSR_LPWRRSTF_NoReset = 0x0
	// This reset type has occurred
	RCC_CSR_LPWRRSTF_Reset = 0x1
)

// Constants for RTC: Real-time clock
const (
	// TR: RTC time register
	// Position of SU field.
	RTC_TR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_TR_SU_Msk = 0xf
	// Position of ST field.
	RTC_TR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_TR_ST_Msk = 0x70
	// Position of MNU field.
	RTC_TR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_TR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_TR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_TR_MNT_Msk = 0x7000
	// Position of HU field.
	RTC_TR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_TR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_TR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_TR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_TR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_TR_PM_Msk = 0x400000
	// Bit PM.
	RTC_TR_PM = 0x400000
	// AM or 24-hour format
	RTC_TR_PM_AM = 0x0
	// PM
	RTC_TR_PM_PM = 0x1

	// DR: RTC date register
	// Position of DU field.
	RTC_DR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_DR_DU_Msk = 0xf
	// Position of DT field.
	RTC_DR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_DR_DT_Msk = 0x30
	// Position of MU field.
	RTC_DR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_DR_MU_Msk = 0xf00
	// Position of MT field.
	RTC_DR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_DR_MT_Msk = 0x1000
	// Bit MT.
	RTC_DR_MT = 0x1000
	// Position of WDU field.
	RTC_DR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_DR_WDU_Msk = 0xe000
	// Position of YU field.
	RTC_DR_YU_Pos = 0x10
	// Bit mask of YU field.
	RTC_DR_YU_Msk = 0xf0000
	// Position of YT field.
	RTC_DR_YT_Pos = 0x14
	// Bit mask of YT field.
	RTC_DR_YT_Msk = 0xf00000

	// SSR: RTC sub second register
	// Position of SS field.
	RTC_SSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_SSR_SS_Msk = 0xffff

	// ICSR: RTC initialization control and status register
	// Position of ALRAWF field.
	RTC_ICSR_ALRAWF_Pos = 0x1
	// Bit mask of ALRAWF field.
	RTC_ICSR_ALRAWF_Msk = 0x2
	// Bit ALRAWF.
	RTC_ICSR_ALRAWF = 0x2
	// Position of ALRBWF field.
	RTC_ICSR_ALRBWF_Pos = 0x2
	// Bit mask of ALRBWF field.
	RTC_ICSR_ALRBWF_Msk = 0x4
	// Bit ALRBWF.
	RTC_ICSR_ALRBWF = 0x4
	// Position of WUTWF field.
	RTC_ICSR_WUTWF_Pos = 0x2
	// Bit mask of WUTWF field.
	RTC_ICSR_WUTWF_Msk = 0x4
	// Bit WUTWF.
	RTC_ICSR_WUTWF = 0x4
	// Wakeup timer configuration update not allowed
	RTC_ICSR_WUTWF_UpdateNotAllowed = 0x0
	// Wakeup timer configuration update allowed
	RTC_ICSR_WUTWF_UpdateAllowed = 0x1
	// Position of SHPF field.
	RTC_ICSR_SHPF_Pos = 0x3
	// Bit mask of SHPF field.
	RTC_ICSR_SHPF_Msk = 0x8
	// Bit SHPF.
	RTC_ICSR_SHPF = 0x8
	// No shift operation is pending
	RTC_ICSR_SHPF_NoShiftPending = 0x0
	// A shift operation is pending
	RTC_ICSR_SHPF_ShiftPending = 0x1
	// Position of INITS field.
	RTC_ICSR_INITS_Pos = 0x4
	// Bit mask of INITS field.
	RTC_ICSR_INITS_Msk = 0x10
	// Bit INITS.
	RTC_ICSR_INITS = 0x10
	// Calendar has not been initialized
	RTC_ICSR_INITS_NotInitalized = 0x0
	// Calendar has been initialized
	RTC_ICSR_INITS_Initalized = 0x1
	// Position of RSF field.
	RTC_ICSR_RSF_Pos = 0x5
	// Bit mask of RSF field.
	RTC_ICSR_RSF_Msk = 0x20
	// Bit RSF.
	RTC_ICSR_RSF = 0x20
	// Calendar shadow registers not yet synchronized
	RTC_ICSR_RSF_NotSynced = 0x0
	// Calendar shadow registers synchronized
	RTC_ICSR_RSF_Synced = 0x1
	// This flag is cleared by software by writing 0
	RTC_ICSR_RSF_Clear = 0x0
	// Position of INITF field.
	RTC_ICSR_INITF_Pos = 0x6
	// Bit mask of INITF field.
	RTC_ICSR_INITF_Msk = 0x40
	// Bit INITF.
	RTC_ICSR_INITF = 0x40
	// Calendar registers update is not allowed
	RTC_ICSR_INITF_NotAllowed = 0x0
	// Calendar registers update is allowed
	RTC_ICSR_INITF_Allowed = 0x1
	// Position of INIT field.
	RTC_ICSR_INIT_Pos = 0x7
	// Bit mask of INIT field.
	RTC_ICSR_INIT_Msk = 0x80
	// Bit INIT.
	RTC_ICSR_INIT = 0x80
	// Free running mode
	RTC_ICSR_INIT_FreeRunningMode = 0x0
	// Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
	RTC_ICSR_INIT_InitMode = 0x1
	// Position of RECALPF field.
	RTC_ICSR_RECALPF_Pos = 0x10
	// Bit mask of RECALPF field.
	RTC_ICSR_RECALPF_Msk = 0x10000
	// Bit RECALPF.
	RTC_ICSR_RECALPF = 0x10000
	// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
	RTC_ICSR_RECALPF_Pending = 0x1

	// PRER: RTC prescaler register
	// Position of PREDIV_S field.
	RTC_PRER_PREDIV_S_Pos = 0x0
	// Bit mask of PREDIV_S field.
	RTC_PRER_PREDIV_S_Msk = 0x7fff
	// Position of PREDIV_A field.
	RTC_PRER_PREDIV_A_Pos = 0x10
	// Bit mask of PREDIV_A field.
	RTC_PRER_PREDIV_A_Msk = 0x7f0000

	// WUTR: RTC wakeup timer register
	// Position of WUT field.
	RTC_WUTR_WUT_Pos = 0x0
	// Bit mask of WUT field.
	RTC_WUTR_WUT_Msk = 0xffff

	// CR: control register
	// Position of WUCKSEL field.
	RTC_CR_WUCKSEL_Pos = 0x0
	// Bit mask of WUCKSEL field.
	RTC_CR_WUCKSEL_Msk = 0x7
	// RTC/16 clock is selected
	RTC_CR_WUCKSEL_Div16 = 0x0
	// RTC/8 clock is selected
	RTC_CR_WUCKSEL_Div8 = 0x1
	// RTC/4 clock is selected
	RTC_CR_WUCKSEL_Div4 = 0x2
	// RTC/2 clock is selected
	RTC_CR_WUCKSEL_Div2 = 0x3
	// ck_spre (usually 1 Hz) clock is selected
	RTC_CR_WUCKSEL_ClockSpare = 0x4
	// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
	RTC_CR_WUCKSEL_ClockSpareWithOffset = 0x6
	// Position of TSEDGE field.
	RTC_CR_TSEDGE_Pos = 0x3
	// Bit mask of TSEDGE field.
	RTC_CR_TSEDGE_Msk = 0x8
	// Bit TSEDGE.
	RTC_CR_TSEDGE = 0x8
	// RTC_TS input rising edge generates a time-stamp event
	RTC_CR_TSEDGE_RisingEdge = 0x0
	// RTC_TS input falling edge generates a time-stamp event
	RTC_CR_TSEDGE_FallingEdge = 0x1
	// Position of REFCKON field.
	RTC_CR_REFCKON_Pos = 0x4
	// Bit mask of REFCKON field.
	RTC_CR_REFCKON_Msk = 0x10
	// Bit REFCKON.
	RTC_CR_REFCKON = 0x10
	// RTC_REFIN detection disabled
	RTC_CR_REFCKON_Disabled = 0x0
	// RTC_REFIN detection enabled
	RTC_CR_REFCKON_Enabled = 0x1
	// Position of BYPSHAD field.
	RTC_CR_BYPSHAD_Pos = 0x5
	// Bit mask of BYPSHAD field.
	RTC_CR_BYPSHAD_Msk = 0x20
	// Bit BYPSHAD.
	RTC_CR_BYPSHAD = 0x20
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
	RTC_CR_BYPSHAD_ShadowReg = 0x0
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
	RTC_CR_BYPSHAD_BypassShadowReg = 0x1
	// Position of FMT field.
	RTC_CR_FMT_Pos = 0x6
	// Bit mask of FMT field.
	RTC_CR_FMT_Msk = 0x40
	// Bit FMT.
	RTC_CR_FMT = 0x40
	// 24 hour/day format
	RTC_CR_FMT_TwentyFourHour = 0x0
	// AM/PM hour format
	RTC_CR_FMT_AmPm = 0x1
	// Position of ALRAE field.
	RTC_CR_ALRAE_Pos = 0x9
	// Bit mask of ALRAE field.
	RTC_CR_ALRAE_Msk = 0x200
	// Bit ALRAE.
	RTC_CR_ALRAE = 0x200
	// Alarm disabled
	RTC_CR_ALRAE_Disabled = 0x0
	// Alarm enabled
	RTC_CR_ALRAE_Enabled = 0x1
	// Position of ALRBE field.
	RTC_CR_ALRBE_Pos = 0xa
	// Bit mask of ALRBE field.
	RTC_CR_ALRBE_Msk = 0x400
	// Bit ALRBE.
	RTC_CR_ALRBE = 0x400
	// Alarm disabled
	RTC_CR_ALRBE_Disabled = 0x0
	// Alarm enabled
	RTC_CR_ALRBE_Enabled = 0x1
	// Position of WUTE field.
	RTC_CR_WUTE_Pos = 0xa
	// Bit mask of WUTE field.
	RTC_CR_WUTE_Msk = 0x400
	// Bit WUTE.
	RTC_CR_WUTE = 0x400
	// Wakeup timer disabled
	RTC_CR_WUTE_Disabled = 0x0
	// Wakeup timer enabled
	RTC_CR_WUTE_Enabled = 0x1
	// Position of TSE field.
	RTC_CR_TSE_Pos = 0xb
	// Bit mask of TSE field.
	RTC_CR_TSE_Msk = 0x800
	// Bit TSE.
	RTC_CR_TSE = 0x800
	// Timestamp disabled
	RTC_CR_TSE_Disabled = 0x0
	// Timestamp enabled
	RTC_CR_TSE_Enabled = 0x1
	// Position of ALRAIE field.
	RTC_CR_ALRAIE_Pos = 0xd
	// Bit mask of ALRAIE field.
	RTC_CR_ALRAIE_Msk = 0x2000
	// Bit ALRAIE.
	RTC_CR_ALRAIE = 0x2000
	// Alarm Interrupt disabled
	RTC_CR_ALRAIE_Disabled = 0x0
	// Alarm Interrupt enabled
	RTC_CR_ALRAIE_Enabled = 0x1
	// Position of ALRBIE field.
	RTC_CR_ALRBIE_Pos = 0xe
	// Bit mask of ALRBIE field.
	RTC_CR_ALRBIE_Msk = 0x4000
	// Bit ALRBIE.
	RTC_CR_ALRBIE = 0x4000
	// Alarm Interrupt disabled
	RTC_CR_ALRBIE_Disabled = 0x0
	// Alarm Interrupt enabled
	RTC_CR_ALRBIE_Enabled = 0x1
	// Position of WUTIE field.
	RTC_CR_WUTIE_Pos = 0xe
	// Bit mask of WUTIE field.
	RTC_CR_WUTIE_Msk = 0x4000
	// Bit WUTIE.
	RTC_CR_WUTIE = 0x4000
	// Wakeup timer interrupt disabled
	RTC_CR_WUTIE_Disabled = 0x0
	// Wakeup timer interrupt enabled
	RTC_CR_WUTIE_Enabled = 0x1
	// Position of TSIE field.
	RTC_CR_TSIE_Pos = 0xf
	// Bit mask of TSIE field.
	RTC_CR_TSIE_Msk = 0x8000
	// Bit TSIE.
	RTC_CR_TSIE = 0x8000
	// Time-stamp Interrupt disabled
	RTC_CR_TSIE_Disabled = 0x0
	// Time-stamp Interrupt enabled
	RTC_CR_TSIE_Enabled = 0x1
	// Position of ADD1H field.
	RTC_CR_ADD1H_Pos = 0x10
	// Bit mask of ADD1H field.
	RTC_CR_ADD1H_Msk = 0x10000
	// Bit ADD1H.
	RTC_CR_ADD1H = 0x10000
	// Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
	RTC_CR_ADD1H_Add1 = 0x1
	// Position of SUB1H field.
	RTC_CR_SUB1H_Pos = 0x11
	// Bit mask of SUB1H field.
	RTC_CR_SUB1H_Msk = 0x20000
	// Bit SUB1H.
	RTC_CR_SUB1H = 0x20000
	// Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
	RTC_CR_SUB1H_Sub1 = 0x1
	// Position of BKP field.
	RTC_CR_BKP_Pos = 0x12
	// Bit mask of BKP field.
	RTC_CR_BKP_Msk = 0x40000
	// Bit BKP.
	RTC_CR_BKP = 0x40000
	// Daylight Saving Time change has not been performed
	RTC_CR_BKP_DSTNotChanged = 0x0
	// Daylight Saving Time change has been performed
	RTC_CR_BKP_DSTChanged = 0x1
	// Position of COSEL field.
	RTC_CR_COSEL_Pos = 0x13
	// Bit mask of COSEL field.
	RTC_CR_COSEL_Msk = 0x80000
	// Bit COSEL.
	RTC_CR_COSEL = 0x80000
	// Calibration output is 512 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_512Hz = 0x0
	// Calibration output is 1 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_1Hz = 0x1
	// Position of POL field.
	RTC_CR_POL_Pos = 0x14
	// Bit mask of POL field.
	RTC_CR_POL_Msk = 0x100000
	// Bit POL.
	RTC_CR_POL = 0x100000
	// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_High = 0x0
	// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_Low = 0x1
	// Position of OSEL field.
	RTC_CR_OSEL_Pos = 0x15
	// Bit mask of OSEL field.
	RTC_CR_OSEL_Msk = 0x600000
	// Output disabled
	RTC_CR_OSEL_Disabled = 0x0
	// Alarm A output enabled
	RTC_CR_OSEL_AlarmA = 0x1
	// Alarm B output enabled
	RTC_CR_OSEL_AlarmB = 0x2
	// Wakeup output enabled
	RTC_CR_OSEL_Wakeup = 0x3
	// Position of COE field.
	RTC_CR_COE_Pos = 0x17
	// Bit mask of COE field.
	RTC_CR_COE_Msk = 0x800000
	// Bit COE.
	RTC_CR_COE = 0x800000
	// Calibration output disabled
	RTC_CR_COE_Disabled = 0x0
	// Calibration output enabled
	RTC_CR_COE_Enabled = 0x1
	// Position of ITSE field.
	RTC_CR_ITSE_Pos = 0x18
	// Bit mask of ITSE field.
	RTC_CR_ITSE_Msk = 0x1000000
	// Bit ITSE.
	RTC_CR_ITSE = 0x1000000
	// Internal event timestamp disabled
	RTC_CR_ITSE_Disabled = 0x0
	// Internal event timestamp enabled
	RTC_CR_ITSE_Enabled = 0x1
	// Position of TAMPTS field.
	RTC_CR_TAMPTS_Pos = 0x19
	// Bit mask of TAMPTS field.
	RTC_CR_TAMPTS_Msk = 0x2000000
	// Bit TAMPTS.
	RTC_CR_TAMPTS = 0x2000000
	// Tamper detection event does not cause a RTC timestamp to be saved
	RTC_CR_TAMPTS_Disabled = 0x0
	// Save RTC timestamp on tamper detection event
	RTC_CR_TAMPTS_Enabled = 0x1
	// Position of TAMPOE field.
	RTC_CR_TAMPOE_Pos = 0x1a
	// Bit mask of TAMPOE field.
	RTC_CR_TAMPOE_Msk = 0x4000000
	// Bit TAMPOE.
	RTC_CR_TAMPOE = 0x4000000
	// The tamper flag is not routed on TAMPALRM
	RTC_CR_TAMPOE_Disabled = 0x0
	// The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL
	RTC_CR_TAMPOE_Enabled = 0x1
	// Position of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Pos = 0x1d
	// Bit mask of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Msk = 0x20000000
	// Bit TAMPALRM_PU.
	RTC_CR_TAMPALRM_PU = 0x20000000
	// No pull-up is applied on TAMPALRM output
	RTC_CR_TAMPALRM_PU_NoPullUp = 0x0
	// A pull-up is applied on TAMPALRM output
	RTC_CR_TAMPALRM_PU_PullUp = 0x1
	// Position of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Pos = 0x1e
	// Bit mask of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Msk = 0x40000000
	// Bit TAMPALRM_TYPE.
	RTC_CR_TAMPALRM_TYPE = 0x40000000
	// TAMPALRM is push-pull output
	RTC_CR_TAMPALRM_TYPE_PushPull = 0x0
	// TAMPALRM is open-drain output
	RTC_CR_TAMPALRM_TYPE_OpenDrain = 0x1
	// Position of OUT2EN field.
	RTC_CR_OUT2EN_Pos = 0x1f
	// Bit mask of OUT2EN field.
	RTC_CR_OUT2EN_Msk = 0x80000000
	// Bit OUT2EN.
	RTC_CR_OUT2EN = 0x80000000
	// RTC output 2 disable
	RTC_CR_OUT2EN_Disabled = 0x0
	// RTC output 2 enable
	RTC_CR_OUT2EN_Enabled = 0x1

	// WPR: write protection register
	// Position of KEY field.
	RTC_WPR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	RTC_WPR_KEY_Msk = 0xff
	// Activate write protection (any value that is not the keys)
	RTC_WPR_KEY_Activate = 0x0
	// Key 2
	RTC_WPR_KEY_Deactivate2 = 0x53
	// Key 1
	RTC_WPR_KEY_Deactivate1 = 0xca

	// CALR: RTC calibration register
	// Position of CALM field.
	RTC_CALR_CALM_Pos = 0x0
	// Bit mask of CALM field.
	RTC_CALR_CALM_Msk = 0x1ff
	// Position of CALW16 field.
	RTC_CALR_CALW16_Pos = 0xd
	// Bit mask of CALW16 field.
	RTC_CALR_CALW16_Msk = 0x2000
	// Bit CALW16.
	RTC_CALR_CALW16 = 0x2000
	// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
	RTC_CALR_CALW16_SixteenSeconds = 0x1
	// Position of CALW8 field.
	RTC_CALR_CALW8_Pos = 0xe
	// Bit mask of CALW8 field.
	RTC_CALR_CALW8_Msk = 0x4000
	// Bit CALW8.
	RTC_CALR_CALW8 = 0x4000
	// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
	RTC_CALR_CALW8_EightSeconds = 0x1
	// Position of CALP field.
	RTC_CALR_CALP_Pos = 0xf
	// Bit mask of CALP field.
	RTC_CALR_CALP_Msk = 0x8000
	// Bit CALP.
	RTC_CALR_CALP = 0x8000
	// No RTCCLK pulses are added
	RTC_CALR_CALP_NoChange = 0x0
	// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
	RTC_CALR_CALP_IncreaseFreq = 0x1

	// SHIFTR: RTC shift control register
	// Position of SUBFS field.
	RTC_SHIFTR_SUBFS_Pos = 0x0
	// Bit mask of SUBFS field.
	RTC_SHIFTR_SUBFS_Msk = 0x7fff
	// Position of ADD1S field.
	RTC_SHIFTR_ADD1S_Pos = 0x1f
	// Bit mask of ADD1S field.
	RTC_SHIFTR_ADD1S_Msk = 0x80000000
	// Bit ADD1S.
	RTC_SHIFTR_ADD1S = 0x80000000
	// Add one second to the clock/calendar
	RTC_SHIFTR_ADD1S_Add1 = 0x1

	// ALRMAR: Alarm %s register
	// Position of SU field.
	RTC_ALRMR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_ALRMR_SU_Msk = 0xf
	// Position of ST field.
	RTC_ALRMR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_ALRMR_ST_Msk = 0x70
	// Position of MSK1 field.
	RTC_ALRMR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_ALRMR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_ALRMR_MSK1 = 0x80
	// Alarm set if the date/day match
	RTC_ALRMR_MSK1_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK1_NotMask = 0x1
	// Position of MNU field.
	RTC_ALRMR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_ALRMR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_ALRMR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_ALRMR_MNT_Msk = 0x7000
	// Position of MSK2 field.
	RTC_ALRMR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_ALRMR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_ALRMR_MSK2 = 0x8000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK2_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK2_NotMask = 0x1
	// Position of HU field.
	RTC_ALRMR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_ALRMR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_ALRMR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_ALRMR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_ALRMR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_ALRMR_PM_Msk = 0x400000
	// Bit PM.
	RTC_ALRMR_PM = 0x400000
	// AM or 24-hour format
	RTC_ALRMR_PM_AM = 0x0
	// PM
	RTC_ALRMR_PM_PM = 0x1
	// Position of MSK3 field.
	RTC_ALRMR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_ALRMR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_ALRMR_MSK3 = 0x800000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK3_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK3_NotMask = 0x1
	// Position of DU field.
	RTC_ALRMR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_ALRMR_DU_Msk = 0xf000000
	// Position of DT field.
	RTC_ALRMR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_ALRMR_DT_Msk = 0x30000000
	// Position of WDSEL field.
	RTC_ALRMR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_ALRMR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_ALRMR_WDSEL = 0x40000000
	// DU[3:0] represents the date units
	RTC_ALRMR_WDSEL_DateUnits = 0x0
	// DU[3:0] represents the week day. DT[1:0] is don’t care.
	RTC_ALRMR_WDSEL_WeekDay = 0x1
	// Position of MSK4 field.
	RTC_ALRMR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_ALRMR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_ALRMR_MSK4 = 0x80000000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK4_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK4_NotMask = 0x1

	// ALRMASSR: Alarm %s sub-second register
	// Position of SS field.
	RTC_ALRMSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRMSSR_SS_Msk = 0x7fff
	// Position of MASKSS field.
	RTC_ALRMSSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_ALRMSSR_MASKSS_Msk = 0xf000000

	// SR: RTC status register
	// Position of ALRAF field.
	RTC_SR_ALRAF_Pos = 0x1
	// Bit mask of ALRAF field.
	RTC_SR_ALRAF_Msk = 0x2
	// Bit ALRAF.
	RTC_SR_ALRAF = 0x2
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)
	RTC_SR_ALRAF_Match = 0x1
	// Position of ALRBF field.
	RTC_SR_ALRBF_Pos = 0x2
	// Bit mask of ALRBF field.
	RTC_SR_ALRBF_Msk = 0x4
	// Bit ALRBF.
	RTC_SR_ALRBF = 0x4
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)
	RTC_SR_ALRBF_Match = 0x1
	// Position of WUTF field.
	RTC_SR_WUTF_Pos = 0x2
	// Bit mask of WUTF field.
	RTC_SR_WUTF_Msk = 0x4
	// Bit WUTF.
	RTC_SR_WUTF = 0x4
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_SR_WUTF_Zero = 0x1
	// Position of TSF field.
	RTC_SR_TSF_Pos = 0x3
	// Bit mask of TSF field.
	RTC_SR_TSF_Msk = 0x8
	// Bit TSF.
	RTC_SR_TSF = 0x8
	// This flag is set by hardware when a time-stamp event occurs
	RTC_SR_TSF_TimestampEvent = 0x1
	// Position of TSOVF field.
	RTC_SR_TSOVF_Pos = 0x4
	// Bit mask of TSOVF field.
	RTC_SR_TSOVF_Msk = 0x10
	// Bit TSOVF.
	RTC_SR_TSOVF = 0x10
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_SR_TSOVF_Overflow = 0x1
	// Position of ITSF field.
	RTC_SR_ITSF_Pos = 0x5
	// Bit mask of ITSF field.
	RTC_SR_ITSF_Msk = 0x20
	// Bit ITSF.
	RTC_SR_ITSF = 0x20
	// This flag is set by hardware when a timestamp on the internal event occurs
	RTC_SR_ITSF_TimestampEvent = 0x1

	// MISR: RTC masked interrupt status register
	// Position of ALRAMF field.
	RTC_MISR_ALRAMF_Pos = 0x1
	// Bit mask of ALRAMF field.
	RTC_MISR_ALRAMF_Msk = 0x2
	// Bit ALRAMF.
	RTC_MISR_ALRAMF = 0x2
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
	RTC_MISR_ALRAMF_Match = 0x1
	// Position of ALRBMF field.
	RTC_MISR_ALRBMF_Pos = 0x2
	// Bit mask of ALRBMF field.
	RTC_MISR_ALRBMF_Msk = 0x4
	// Bit ALRBMF.
	RTC_MISR_ALRBMF = 0x4
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
	RTC_MISR_ALRBMF_Match = 0x1
	// Position of WUTMF field.
	RTC_MISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_MISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_MISR_WUTMF = 0x4
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_MISR_WUTMF_Zero = 0x1
	// Position of TSMF field.
	RTC_MISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_MISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_MISR_TSMF = 0x8
	// This flag is set by hardware when a time-stamp event occurs
	RTC_MISR_TSMF_TimestampEvent = 0x1
	// Position of TSOVMF field.
	RTC_MISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_MISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_MISR_TSOVMF = 0x10
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_MISR_TSOVMF_Overflow = 0x1
	// Position of ITSMF field.
	RTC_MISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_MISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_MISR_ITSMF = 0x20
	// This flag is set by hardware when a timestamp on the internal event occurs
	RTC_MISR_ITSMF_TimestampEvent = 0x1

	// SCR: RTC status clear register
	// Position of CALRAF field.
	RTC_SCR_CALRAF_Pos = 0x0
	// Bit mask of CALRAF field.
	RTC_SCR_CALRAF_Msk = 0x1
	// Bit CALRAF.
	RTC_SCR_CALRAF = 0x1
	// Clear interrupt flag
	RTC_SCR_CALRAF_Clear = 0x1
	// Position of CALRBF field.
	RTC_SCR_CALRBF_Pos = 0x1
	// Bit mask of CALRBF field.
	RTC_SCR_CALRBF_Msk = 0x2
	// Bit CALRBF.
	RTC_SCR_CALRBF = 0x2
	// Clear interrupt flag
	RTC_SCR_CALRBF_Clear = 0x1
	// Position of CWUTF field.
	RTC_SCR_CWUTF_Pos = 0x2
	// Bit mask of CWUTF field.
	RTC_SCR_CWUTF_Msk = 0x4
	// Bit CWUTF.
	RTC_SCR_CWUTF = 0x4
	// Clear interrupt flag
	RTC_SCR_CWUTF_Clear = 0x1
	// Position of CTSF field.
	RTC_SCR_CTSF_Pos = 0x3
	// Bit mask of CTSF field.
	RTC_SCR_CTSF_Msk = 0x8
	// Bit CTSF.
	RTC_SCR_CTSF = 0x8
	// Clear interrupt flag
	RTC_SCR_CTSF_Clear = 0x1
	// Position of CTSOVF field.
	RTC_SCR_CTSOVF_Pos = 0x4
	// Bit mask of CTSOVF field.
	RTC_SCR_CTSOVF_Msk = 0x10
	// Bit CTSOVF.
	RTC_SCR_CTSOVF = 0x10
	// Clear interrupt flag
	RTC_SCR_CTSOVF_Clear = 0x1
	// Position of CITSF field.
	RTC_SCR_CITSF_Pos = 0x5
	// Bit mask of CITSF field.
	RTC_SCR_CITSF_Msk = 0x20
	// Bit CITSF.
	RTC_SCR_CITSF = 0x20
	// Clear interrupt flag
	RTC_SCR_CITSF_Clear = 0x1
)

// Constants for SPI1: Serial peripheral interface/Inter-IC sound
const (
	// CR1
	// Position of CPHA field.
	SPI_CR1_CPHA_Pos = 0x0
	// Bit mask of CPHA field.
	SPI_CR1_CPHA_Msk = 0x1
	// Bit CPHA.
	SPI_CR1_CPHA = 0x1
	// The first clock transition is the first data capture edge
	SPI_CR1_CPHA_FirstEdge = 0x0
	// The second clock transition is the first data capture edge
	SPI_CR1_CPHA_SecondEdge = 0x1
	// Position of CPOL field.
	SPI_CR1_CPOL_Pos = 0x1
	// Bit mask of CPOL field.
	SPI_CR1_CPOL_Msk = 0x2
	// Bit CPOL.
	SPI_CR1_CPOL = 0x2
	// CK to 0 when idle
	SPI_CR1_CPOL_IdleLow = 0x0
	// CK to 1 when idle
	SPI_CR1_CPOL_IdleHigh = 0x1
	// Position of MSTR field.
	SPI_CR1_MSTR_Pos = 0x2
	// Bit mask of MSTR field.
	SPI_CR1_MSTR_Msk = 0x4
	// Bit MSTR.
	SPI_CR1_MSTR = 0x4
	// Slave configuration
	SPI_CR1_MSTR_Slave = 0x0
	// Master configuration
	SPI_CR1_MSTR_Master = 0x1
	// Position of BR field.
	SPI_CR1_BR_Pos = 0x3
	// Bit mask of BR field.
	SPI_CR1_BR_Msk = 0x38
	// f_PCLK / 2
	SPI_CR1_BR_Div2 = 0x0
	// f_PCLK / 4
	SPI_CR1_BR_Div4 = 0x1
	// f_PCLK / 8
	SPI_CR1_BR_Div8 = 0x2
	// f_PCLK / 16
	SPI_CR1_BR_Div16 = 0x3
	// f_PCLK / 32
	SPI_CR1_BR_Div32 = 0x4
	// f_PCLK / 64
	SPI_CR1_BR_Div64 = 0x5
	// f_PCLK / 128
	SPI_CR1_BR_Div128 = 0x6
	// f_PCLK / 256
	SPI_CR1_BR_Div256 = 0x7
	// Position of SPE field.
	SPI_CR1_SPE_Pos = 0x6
	// Bit mask of SPE field.
	SPI_CR1_SPE_Msk = 0x40
	// Bit SPE.
	SPI_CR1_SPE = 0x40
	// Peripheral disabled
	SPI_CR1_SPE_Disabled = 0x0
	// Peripheral enabled
	SPI_CR1_SPE_Enabled = 0x1
	// Position of LSBFIRST field.
	SPI_CR1_LSBFIRST_Pos = 0x7
	// Bit mask of LSBFIRST field.
	SPI_CR1_LSBFIRST_Msk = 0x80
	// Bit LSBFIRST.
	SPI_CR1_LSBFIRST = 0x80
	// Data is transmitted/received with the MSB first
	SPI_CR1_LSBFIRST_MSBFirst = 0x0
	// Data is transmitted/received with the LSB first
	SPI_CR1_LSBFIRST_LSBFirst = 0x1
	// Position of SSI field.
	SPI_CR1_SSI_Pos = 0x8
	// Bit mask of SSI field.
	SPI_CR1_SSI_Msk = 0x100
	// Bit SSI.
	SPI_CR1_SSI = 0x100
	// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
	SPI_CR1_SSI_SlaveSelected = 0x0
	// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
	SPI_CR1_SSI_SlaveNotSelected = 0x1
	// Position of SSM field.
	SPI_CR1_SSM_Pos = 0x9
	// Bit mask of SSM field.
	SPI_CR1_SSM_Msk = 0x200
	// Bit SSM.
	SPI_CR1_SSM = 0x200
	// Software slave management disabled
	SPI_CR1_SSM_Disabled = 0x0
	// Software slave management enabled
	SPI_CR1_SSM_Enabled = 0x1
	// Position of RXONLY field.
	SPI_CR1_RXONLY_Pos = 0xa
	// Bit mask of RXONLY field.
	SPI_CR1_RXONLY_Msk = 0x400
	// Bit RXONLY.
	SPI_CR1_RXONLY = 0x400
	// Full duplex (Transmit and receive)
	SPI_CR1_RXONLY_FullDuplex = 0x0
	// Output disabled (Receive-only mode)
	SPI_CR1_RXONLY_OutputDisabled = 0x1
	// Position of CRCL field.
	SPI_CR1_CRCL_Pos = 0xb
	// Bit mask of CRCL field.
	SPI_CR1_CRCL_Msk = 0x800
	// Bit CRCL.
	SPI_CR1_CRCL = 0x800
	// 8-bit CRC length
	SPI_CR1_CRCL_EightBit = 0x0
	// 16-bit CRC length
	SPI_CR1_CRCL_SixteenBit = 0x1
	// Position of CRCNEXT field.
	SPI_CR1_CRCNEXT_Pos = 0xc
	// Bit mask of CRCNEXT field.
	SPI_CR1_CRCNEXT_Msk = 0x1000
	// Bit CRCNEXT.
	SPI_CR1_CRCNEXT = 0x1000
	// Next transmit value is from Tx buffer
	SPI_CR1_CRCNEXT_TxBuffer = 0x0
	// Next transmit value is from Tx CRC register
	SPI_CR1_CRCNEXT_CRC = 0x1
	// Position of CRCEN field.
	SPI_CR1_CRCEN_Pos = 0xd
	// Bit mask of CRCEN field.
	SPI_CR1_CRCEN_Msk = 0x2000
	// Bit CRCEN.
	SPI_CR1_CRCEN = 0x2000
	// CRC calculation disabled
	SPI_CR1_CRCEN_Disabled = 0x0
	// CRC calculation enabled
	SPI_CR1_CRCEN_Enabled = 0x1
	// Position of BIDIOE field.
	SPI_CR1_BIDIOE_Pos = 0xe
	// Bit mask of BIDIOE field.
	SPI_CR1_BIDIOE_Msk = 0x4000
	// Bit BIDIOE.
	SPI_CR1_BIDIOE = 0x4000
	// Output disabled (receive-only mode)
	SPI_CR1_BIDIOE_OutputDisabled = 0x0
	// Output enabled (transmit-only mode)
	SPI_CR1_BIDIOE_OutputEnabled = 0x1
	// Position of BIDIMODE field.
	SPI_CR1_BIDIMODE_Pos = 0xf
	// Bit mask of BIDIMODE field.
	SPI_CR1_BIDIMODE_Msk = 0x8000
	// Bit BIDIMODE.
	SPI_CR1_BIDIMODE = 0x8000
	// 2-line unidirectional data mode selected
	SPI_CR1_BIDIMODE_Unidirectional = 0x0
	// 1-line bidirectional data mode selected
	SPI_CR1_BIDIMODE_Bidirectional = 0x1

	// CR2
	// Position of RXDMAEN field.
	SPI_CR2_RXDMAEN_Pos = 0x0
	// Bit mask of RXDMAEN field.
	SPI_CR2_RXDMAEN_Msk = 0x1
	// Bit RXDMAEN.
	SPI_CR2_RXDMAEN = 0x1
	// Rx buffer DMA disabled
	SPI_CR2_RXDMAEN_Disabled = 0x0
	// Rx buffer DMA enabled
	SPI_CR2_RXDMAEN_Enabled = 0x1
	// Position of TXDMAEN field.
	SPI_CR2_TXDMAEN_Pos = 0x1
	// Bit mask of TXDMAEN field.
	SPI_CR2_TXDMAEN_Msk = 0x2
	// Bit TXDMAEN.
	SPI_CR2_TXDMAEN = 0x2
	// Tx buffer DMA disabled
	SPI_CR2_TXDMAEN_Disabled = 0x0
	// Tx buffer DMA enabled
	SPI_CR2_TXDMAEN_Enabled = 0x1
	// Position of SSOE field.
	SPI_CR2_SSOE_Pos = 0x2
	// Bit mask of SSOE field.
	SPI_CR2_SSOE_Msk = 0x4
	// Bit SSOE.
	SPI_CR2_SSOE = 0x4
	// SS output is disabled in master mode
	SPI_CR2_SSOE_Disabled = 0x0
	// SS output is enabled in master mode
	SPI_CR2_SSOE_Enabled = 0x1
	// Position of NSSP field.
	SPI_CR2_NSSP_Pos = 0x3
	// Bit mask of NSSP field.
	SPI_CR2_NSSP_Msk = 0x8
	// Bit NSSP.
	SPI_CR2_NSSP = 0x8
	// No NSS pulse
	SPI_CR2_NSSP_NoPulse = 0x0
	// NSS pulse generated
	SPI_CR2_NSSP_PulseGenerated = 0x1
	// Position of FRF field.
	SPI_CR2_FRF_Pos = 0x4
	// Bit mask of FRF field.
	SPI_CR2_FRF_Msk = 0x10
	// Bit FRF.
	SPI_CR2_FRF = 0x10
	// SPI Motorola mode
	SPI_CR2_FRF_Motorola = 0x0
	// SPI TI mode
	SPI_CR2_FRF_TI = 0x1
	// Position of ERRIE field.
	SPI_CR2_ERRIE_Pos = 0x5
	// Bit mask of ERRIE field.
	SPI_CR2_ERRIE_Msk = 0x20
	// Bit ERRIE.
	SPI_CR2_ERRIE = 0x20
	// Error interrupt masked
	SPI_CR2_ERRIE_Masked = 0x0
	// Error interrupt not masked
	SPI_CR2_ERRIE_NotMasked = 0x1
	// Position of RXNEIE field.
	SPI_CR2_RXNEIE_Pos = 0x6
	// Bit mask of RXNEIE field.
	SPI_CR2_RXNEIE_Msk = 0x40
	// Bit RXNEIE.
	SPI_CR2_RXNEIE = 0x40
	// RXE interrupt masked
	SPI_CR2_RXNEIE_Masked = 0x0
	// RXE interrupt not masked
	SPI_CR2_RXNEIE_NotMasked = 0x1
	// Position of TXEIE field.
	SPI_CR2_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	SPI_CR2_TXEIE_Msk = 0x80
	// Bit TXEIE.
	SPI_CR2_TXEIE = 0x80
	// TXE interrupt masked
	SPI_CR2_TXEIE_Masked = 0x0
	// TXE interrupt not masked
	SPI_CR2_TXEIE_NotMasked = 0x1
	// Position of DS field.
	SPI_CR2_DS_Pos = 0x8
	// Bit mask of DS field.
	SPI_CR2_DS_Msk = 0xf00
	// 4-bit
	SPI_CR2_DS_FourBit = 0x3
	// 5-bit
	SPI_CR2_DS_FiveBit = 0x4
	// 6-bit
	SPI_CR2_DS_SixBit = 0x5
	// 7-bit
	SPI_CR2_DS_SevenBit = 0x6
	// 8-bit
	SPI_CR2_DS_EightBit = 0x7
	// 9-bit
	SPI_CR2_DS_NineBit = 0x8
	// 10-bit
	SPI_CR2_DS_TenBit = 0x9
	// 11-bit
	SPI_CR2_DS_ElevenBit = 0xa
	// 12-bit
	SPI_CR2_DS_TwelveBit = 0xb
	// 13-bit
	SPI_CR2_DS_ThirteenBit = 0xc
	// 14-bit
	SPI_CR2_DS_FourteenBit = 0xd
	// 15-bit
	SPI_CR2_DS_FifteenBit = 0xe
	// 16-bit
	SPI_CR2_DS_SixteenBit = 0xf
	// Position of FRXTH field.
	SPI_CR2_FRXTH_Pos = 0xc
	// Bit mask of FRXTH field.
	SPI_CR2_FRXTH_Msk = 0x1000
	// Bit FRXTH.
	SPI_CR2_FRXTH = 0x1000
	// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
	SPI_CR2_FRXTH_Half = 0x0
	// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
	SPI_CR2_FRXTH_Quarter = 0x1
	// Position of LDMA_RX field.
	SPI_CR2_LDMA_RX_Pos = 0xd
	// Bit mask of LDMA_RX field.
	SPI_CR2_LDMA_RX_Msk = 0x2000
	// Bit LDMA_RX.
	SPI_CR2_LDMA_RX = 0x2000
	// Number of data to transfer for receive is even
	SPI_CR2_LDMA_RX_Even = 0x0
	// Number of data to transfer for receive is odd
	SPI_CR2_LDMA_RX_Odd = 0x1
	// Position of LDMA_TX field.
	SPI_CR2_LDMA_TX_Pos = 0xe
	// Bit mask of LDMA_TX field.
	SPI_CR2_LDMA_TX_Msk = 0x4000
	// Bit LDMA_TX.
	SPI_CR2_LDMA_TX = 0x4000
	// Number of data to transfer for transmit is even
	SPI_CR2_LDMA_TX_Even = 0x0
	// Number of data to transfer for transmit is odd
	SPI_CR2_LDMA_TX_Odd = 0x1

	// SR
	// Position of RXNE field.
	SPI_SR_RXNE_Pos = 0x0
	// Bit mask of RXNE field.
	SPI_SR_RXNE_Msk = 0x1
	// Bit RXNE.
	SPI_SR_RXNE = 0x1
	// Rx buffer empty
	SPI_SR_RXNE_Empty = 0x0
	// Rx buffer not empty
	SPI_SR_RXNE_NotEmpty = 0x1
	// Position of TXE field.
	SPI_SR_TXE_Pos = 0x1
	// Bit mask of TXE field.
	SPI_SR_TXE_Msk = 0x2
	// Bit TXE.
	SPI_SR_TXE = 0x2
	// Tx buffer not empty
	SPI_SR_TXE_NotEmpty = 0x0
	// Tx buffer empty
	SPI_SR_TXE_Empty = 0x1
	// Position of CHSIDE field.
	SPI_SR_CHSIDE_Pos = 0x2
	// Bit mask of CHSIDE field.
	SPI_SR_CHSIDE_Msk = 0x4
	// Bit CHSIDE.
	SPI_SR_CHSIDE = 0x4
	// Channel left has to be transmitted or has been received
	SPI_SR_CHSIDE_Left = 0x0
	// Channel right has to be transmitted or has been received
	SPI_SR_CHSIDE_Right = 0x1
	// Position of UDR field.
	SPI_SR_UDR_Pos = 0x3
	// Bit mask of UDR field.
	SPI_SR_UDR_Msk = 0x8
	// Bit UDR.
	SPI_SR_UDR = 0x8
	// No underrun occurred
	SPI_SR_UDR_NoUnderrun = 0x0
	// Underrun occurred
	SPI_SR_UDR_Underrun = 0x1
	// Position of CRCERR field.
	SPI_SR_CRCERR_Pos = 0x4
	// Bit mask of CRCERR field.
	SPI_SR_CRCERR_Msk = 0x10
	// Bit CRCERR.
	SPI_SR_CRCERR = 0x10
	// CRC value received matches the SPIx_RXCRCR value
	SPI_SR_CRCERR_Match = 0x0
	// CRC value received does not match the SPIx_RXCRCR value
	SPI_SR_CRCERR_NoMatch = 0x1
	// Clear flag
	SPI_SR_CRCERR_Clear = 0x0
	// Position of MODF field.
	SPI_SR_MODF_Pos = 0x5
	// Bit mask of MODF field.
	SPI_SR_MODF_Msk = 0x20
	// Bit MODF.
	SPI_SR_MODF = 0x20
	// No mode fault occurred
	SPI_SR_MODF_NoFault = 0x0
	// Mode fault occurred
	SPI_SR_MODF_Fault = 0x1
	// Position of OVR field.
	SPI_SR_OVR_Pos = 0x6
	// Bit mask of OVR field.
	SPI_SR_OVR_Msk = 0x40
	// Bit OVR.
	SPI_SR_OVR = 0x40
	// No overrun occurred
	SPI_SR_OVR_NoOverrun = 0x0
	// Overrun occurred
	SPI_SR_OVR_Overrun = 0x1
	// Position of BSY field.
	SPI_SR_BSY_Pos = 0x7
	// Bit mask of BSY field.
	SPI_SR_BSY_Msk = 0x80
	// Bit BSY.
	SPI_SR_BSY = 0x80
	// SPI not busy
	SPI_SR_BSY_NotBusy = 0x0
	// SPI busy
	SPI_SR_BSY_Busy = 0x1
	// Position of FRE field.
	SPI_SR_FRE_Pos = 0x8
	// Bit mask of FRE field.
	SPI_SR_FRE_Msk = 0x100
	// Bit FRE.
	SPI_SR_FRE = 0x100
	// No frame format error
	SPI_SR_FRE_NoError = 0x0
	// A frame format error occurred
	SPI_SR_FRE_Error = 0x1
	// Position of FRLVL field.
	SPI_SR_FRLVL_Pos = 0x9
	// Bit mask of FRLVL field.
	SPI_SR_FRLVL_Msk = 0x600
	// Rx FIFO Empty
	SPI_SR_FRLVL_Empty = 0x0
	// Rx 1/4 FIFO
	SPI_SR_FRLVL_Quarter = 0x1
	// Rx 1/2 FIFO
	SPI_SR_FRLVL_Half = 0x2
	// Rx FIFO full
	SPI_SR_FRLVL_Full = 0x3
	// Position of FTLVL field.
	SPI_SR_FTLVL_Pos = 0xb
	// Bit mask of FTLVL field.
	SPI_SR_FTLVL_Msk = 0x1800
	// Tx FIFO Empty
	SPI_SR_FTLVL_Empty = 0x0
	// Tx 1/4 FIFO
	SPI_SR_FTLVL_Quarter = 0x1
	// Tx 1/2 FIFO
	SPI_SR_FTLVL_Half = 0x2
	// Tx FIFO full
	SPI_SR_FTLVL_Full = 0x3

	// DR
	// Position of DR field.
	SPI_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	SPI_DR_DR_Msk = 0xffff

	// DR8: Direct 8-bit access to data register
	// Position of DR field.
	SPI_DR8_DR_Pos = 0x0
	// Bit mask of DR field.
	SPI_DR8_DR_Msk = 0xff

	// CRCPR
	// Position of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Pos = 0x0
	// Bit mask of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Msk = 0xffff

	// RXCRCR
	// Position of RXCRC field.
	SPI_RXCRCR_RXCRC_Pos = 0x0
	// Bit mask of RXCRC field.
	SPI_RXCRCR_RXCRC_Msk = 0xffff

	// TXCRCR
	// Position of TXCRC field.
	SPI_TXCRCR_TXCRC_Pos = 0x0
	// Bit mask of TXCRC field.
	SPI_TXCRCR_TXCRC_Msk = 0xffff

	// I2SCFGR
	// Position of CHLEN field.
	SPI_I2SCFGR_CHLEN_Pos = 0x0
	// Bit mask of CHLEN field.
	SPI_I2SCFGR_CHLEN_Msk = 0x1
	// Bit CHLEN.
	SPI_I2SCFGR_CHLEN = 0x1
	// 16-bit wide
	SPI_I2SCFGR_CHLEN_SixteenBit = 0x0
	// 32-bit wide
	SPI_I2SCFGR_CHLEN_ThirtyTwoBit = 0x1
	// Position of DATLEN field.
	SPI_I2SCFGR_DATLEN_Pos = 0x1
	// Bit mask of DATLEN field.
	SPI_I2SCFGR_DATLEN_Msk = 0x6
	// 16-bit data length
	SPI_I2SCFGR_DATLEN_SixteenBit = 0x0
	// 24-bit data length
	SPI_I2SCFGR_DATLEN_TwentyFourBit = 0x1
	// 32-bit data length
	SPI_I2SCFGR_DATLEN_ThirtyTwoBit = 0x2
	// Position of CKPOL field.
	SPI_I2SCFGR_CKPOL_Pos = 0x3
	// Bit mask of CKPOL field.
	SPI_I2SCFGR_CKPOL_Msk = 0x8
	// Bit CKPOL.
	SPI_I2SCFGR_CKPOL = 0x8
	// I2S clock inactive state is low level
	SPI_I2SCFGR_CKPOL_IdleLow = 0x0
	// I2S clock inactive state is high level
	SPI_I2SCFGR_CKPOL_IdleHigh = 0x1
	// Position of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Pos = 0x4
	// Bit mask of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Msk = 0x30
	// I2S Philips standard
	SPI_I2SCFGR_I2SSTD_Philips = 0x0
	// MSB justified standard
	SPI_I2SCFGR_I2SSTD_MSB = 0x1
	// LSB justified standard
	SPI_I2SCFGR_I2SSTD_LSB = 0x2
	// PCM standard
	SPI_I2SCFGR_I2SSTD_PCM = 0x3
	// Position of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Pos = 0x7
	// Bit mask of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Msk = 0x80
	// Bit PCMSYNC.
	SPI_I2SCFGR_PCMSYNC = 0x80
	// Short frame synchronisation
	SPI_I2SCFGR_PCMSYNC_Short = 0x0
	// Long frame synchronisation
	SPI_I2SCFGR_PCMSYNC_Long = 0x1
	// Position of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Pos = 0x8
	// Bit mask of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Msk = 0x300
	// Slave - transmit
	SPI_I2SCFGR_I2SCFG_SlaveTx = 0x0
	// Slave - receive
	SPI_I2SCFGR_I2SCFG_SlaveRx = 0x1
	// Master - transmit
	SPI_I2SCFGR_I2SCFG_MasterTx = 0x2
	// Master - receive
	SPI_I2SCFGR_I2SCFG_MasterRx = 0x3
	// Position of I2SE field.
	SPI_I2SCFGR_I2SE_Pos = 0xa
	// Bit mask of I2SE field.
	SPI_I2SCFGR_I2SE_Msk = 0x400
	// Bit I2SE.
	SPI_I2SCFGR_I2SE = 0x400
	// I2S peripheral is disabled
	SPI_I2SCFGR_I2SE_Disabled = 0x0
	// I2S peripheral is enabled
	SPI_I2SCFGR_I2SE_Enabled = 0x1
	// Position of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Pos = 0xb
	// Bit mask of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Msk = 0x800
	// Bit I2SMOD.
	SPI_I2SCFGR_I2SMOD = 0x800
	// SPI mode is selected
	SPI_I2SCFGR_I2SMOD_SPIMode = 0x0
	// I2S mode is selected
	SPI_I2SCFGR_I2SMOD_I2SMode = 0x1
	// Position of ASTRTEN field.
	SPI_I2SCFGR_ASTRTEN_Pos = 0xc
	// Bit mask of ASTRTEN field.
	SPI_I2SCFGR_ASTRTEN_Msk = 0x1000
	// Bit ASTRTEN.
	SPI_I2SCFGR_ASTRTEN = 0x1000
	// Asynchronous start disabled
	SPI_I2SCFGR_ASTRTEN_AsyncStartDisabled = 0x0
	// Asynchronous start enabled
	SPI_I2SCFGR_ASTRTEN_AsyncStartEnabled = 0x1

	// I2SPR
	// Position of I2SDIV field.
	SPI_I2SPR_I2SDIV_Pos = 0x0
	// Bit mask of I2SDIV field.
	SPI_I2SPR_I2SDIV_Msk = 0xff
	// Position of ODD field.
	SPI_I2SPR_ODD_Pos = 0x8
	// Bit mask of ODD field.
	SPI_I2SPR_ODD_Msk = 0x100
	// Bit ODD.
	SPI_I2SPR_ODD = 0x100
	// Real divider value is I2SDIV * 2
	SPI_I2SPR_ODD_Even = 0x0
	// Real divider value is (I2SDIV * 2) + 1
	SPI_I2SPR_ODD_Odd = 0x1
	// Position of MCKOE field.
	SPI_I2SPR_MCKOE_Pos = 0x9
	// Bit mask of MCKOE field.
	SPI_I2SPR_MCKOE_Msk = 0x200
	// Bit MCKOE.
	SPI_I2SPR_MCKOE = 0x200
	// Master clock output is disabled
	SPI_I2SPR_MCKOE_Disabled = 0x0
	// Master clock output is enabled
	SPI_I2SPR_MCKOE_Enabled = 0x1
)

// Constants for SYSCFG: System configuration controller
const (
	// CFGR1: SYSCFG configuration register 1
	// Position of I2C_PBx_FMP field.
	SYSCFG_CFGR1_I2C_PBx_FMP_Pos = 0x10
	// Bit mask of I2C_PBx_FMP field.
	SYSCFG_CFGR1_I2C_PBx_FMP_Msk = 0x10000
	// Bit I2C_PBx_FMP.
	SYSCFG_CFGR1_I2C_PBx_FMP = 0x10000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C_PBx_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C_PBx_FMP_Enabled = 0x1
	// Position of I2C3_FMP field.
	SYSCFG_CFGR1_I2C3_FMP_Pos = 0x18
	// Bit mask of I2C3_FMP field.
	SYSCFG_CFGR1_I2C3_FMP_Msk = 0x1000000
	// Bit I2C3_FMP.
	SYSCFG_CFGR1_I2C3_FMP = 0x1000000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C3_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C3_FMP_Enabled = 0x1
	// Position of I2C_PA10_FMP field.
	SYSCFG_CFGR1_I2C_PA10_FMP_Pos = 0x17
	// Bit mask of I2C_PA10_FMP field.
	SYSCFG_CFGR1_I2C_PA10_FMP_Msk = 0x800000
	// Bit I2C_PA10_FMP.
	SYSCFG_CFGR1_I2C_PA10_FMP = 0x800000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C_PA10_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C_PA10_FMP_Enabled = 0x1
	// Position of I2C_PA9_FMP field.
	SYSCFG_CFGR1_I2C_PA9_FMP_Pos = 0x16
	// Bit mask of I2C_PA9_FMP field.
	SYSCFG_CFGR1_I2C_PA9_FMP_Msk = 0x400000
	// Bit I2C_PA9_FMP.
	SYSCFG_CFGR1_I2C_PA9_FMP = 0x400000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C_PA9_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C_PA9_FMP_Enabled = 0x1
	// Position of I2C2_FMP field.
	SYSCFG_CFGR1_I2C2_FMP_Pos = 0x15
	// Bit mask of I2C2_FMP field.
	SYSCFG_CFGR1_I2C2_FMP_Msk = 0x200000
	// Bit I2C2_FMP.
	SYSCFG_CFGR1_I2C2_FMP = 0x200000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C2_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C2_FMP_Enabled = 0x1
	// Position of I2C1_FMP field.
	SYSCFG_CFGR1_I2C1_FMP_Pos = 0x14
	// Bit mask of I2C1_FMP field.
	SYSCFG_CFGR1_I2C1_FMP_Msk = 0x100000
	// Bit I2C1_FMP.
	SYSCFG_CFGR1_I2C1_FMP = 0x100000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C1_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C1_FMP_Enabled = 0x1
	// Position of I2C_PB9_FMP field.
	SYSCFG_CFGR1_I2C_PB9_FMP_Pos = 0x13
	// Bit mask of I2C_PB9_FMP field.
	SYSCFG_CFGR1_I2C_PB9_FMP_Msk = 0x80000
	// Bit I2C_PB9_FMP.
	SYSCFG_CFGR1_I2C_PB9_FMP = 0x80000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C_PB9_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C_PB9_FMP_Enabled = 0x1
	// Position of I2C_PB8_FMP field.
	SYSCFG_CFGR1_I2C_PB8_FMP_Pos = 0x12
	// Bit mask of I2C_PB8_FMP field.
	SYSCFG_CFGR1_I2C_PB8_FMP_Msk = 0x40000
	// Bit I2C_PB8_FMP.
	SYSCFG_CFGR1_I2C_PB8_FMP = 0x40000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C_PB8_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C_PB8_FMP_Enabled = 0x1
	// Position of I2C_PB7_FMP field.
	SYSCFG_CFGR1_I2C_PB7_FMP_Pos = 0x11
	// Bit mask of I2C_PB7_FMP field.
	SYSCFG_CFGR1_I2C_PB7_FMP_Msk = 0x20000
	// Bit I2C_PB7_FMP.
	SYSCFG_CFGR1_I2C_PB7_FMP = 0x20000
	// Uses normal GPIO drive
	SYSCFG_CFGR1_I2C_PB7_FMP_Disabled = 0x0
	// Uses I2C FastMode+ drive
	SYSCFG_CFGR1_I2C_PB7_FMP_Enabled = 0x1
	// Position of UCPD1_STROBE field.
	SYSCFG_CFGR1_UCPD1_STROBE_Pos = 0x9
	// Bit mask of UCPD1_STROBE field.
	SYSCFG_CFGR1_UCPD1_STROBE_Msk = 0x200
	// Bit UCPD1_STROBE.
	SYSCFG_CFGR1_UCPD1_STROBE = 0x200
	// Disconnect the UCPD pull-down resistors
	SYSCFG_CFGR1_UCPD1_STROBE_Disconnect = 0x1
	// Position of UCPD2_STROBE field.
	SYSCFG_CFGR1_UCPD2_STROBE_Pos = 0xa
	// Bit mask of UCPD2_STROBE field.
	SYSCFG_CFGR1_UCPD2_STROBE_Msk = 0x400
	// Bit UCPD2_STROBE.
	SYSCFG_CFGR1_UCPD2_STROBE = 0x400
	// Disconnect the UCPD pull-down resistors
	SYSCFG_CFGR1_UCPD2_STROBE_Disconnect = 0x1
	// Position of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Pos = 0x8
	// Bit mask of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Msk = 0x100
	// Bit BOOSTEN.
	SYSCFG_CFGR1_BOOSTEN = 0x100
	// supply analog switches from VDD
	SYSCFG_CFGR1_BOOSTEN_VDD = 0x0
	// supply analog switches from dedicated voltage booster
	SYSCFG_CFGR1_BOOSTEN_BOOST = 0x1
	// Position of IR_MOD field.
	SYSCFG_CFGR1_IR_MOD_Pos = 0x6
	// Bit mask of IR_MOD field.
	SYSCFG_CFGR1_IR_MOD_Msk = 0xc0
	// IR modulation envelope from TIM16
	SYSCFG_CFGR1_IR_MOD_TIM16 = 0x0
	// IR modulation envelope from USART1
	SYSCFG_CFGR1_IR_MOD_USART1 = 0x1
	// IR modulation envelope from USART2
	SYSCFG_CFGR1_IR_MOD_USART2 = 0x2
	// Position of IR_POL field.
	SYSCFG_CFGR1_IR_POL_Pos = 0x5
	// Bit mask of IR_POL field.
	SYSCFG_CFGR1_IR_POL_Msk = 0x20
	// Bit IR_POL.
	SYSCFG_CFGR1_IR_POL = 0x20
	// Output of IRTIM is not inverted
	SYSCFG_CFGR1_IR_POL_Normal = 0x0
	// Output of IRTIM is inverted
	SYSCFG_CFGR1_IR_POL_Inverted = 0x1
	// Position of PA12_RMP field.
	SYSCFG_CFGR1_PA12_RMP_Pos = 0x4
	// Bit mask of PA12_RMP field.
	SYSCFG_CFGR1_PA12_RMP_Msk = 0x10
	// Bit PA12_RMP.
	SYSCFG_CFGR1_PA12_RMP = 0x10
	// PA12 pin connected to PA12 GPIO
	SYSCFG_CFGR1_PA12_RMP_Normal = 0x0
	// PA12 pin connected to PA10 GPIO
	SYSCFG_CFGR1_PA12_RMP_Remap = 0x1
	// Position of PA11_RMP field.
	SYSCFG_CFGR1_PA11_RMP_Pos = 0x3
	// Bit mask of PA11_RMP field.
	SYSCFG_CFGR1_PA11_RMP_Msk = 0x8
	// Bit PA11_RMP.
	SYSCFG_CFGR1_PA11_RMP = 0x8
	// PA11 pin connected to PA11 GPIO
	SYSCFG_CFGR1_PA11_RMP_Normal = 0x0
	// PA11 pin connected to PA9 GPIO
	SYSCFG_CFGR1_PA11_RMP_Remap = 0x1
	// Position of MEM_MODE field.
	SYSCFG_CFGR1_MEM_MODE_Pos = 0x0
	// Bit mask of MEM_MODE field.
	SYSCFG_CFGR1_MEM_MODE_Msk = 0x3
	// Main flash memory mapped at zero address
	SYSCFG_CFGR1_MEM_MODE_MainFlash = 0x0
	// System flash memory mapped at zero address
	SYSCFG_CFGR1_MEM_MODE_SystemFlash = 0x2
	// Embedded SRAM mapped at zero address
	SYSCFG_CFGR1_MEM_MODE_SRAM = 0x3

	// CFGR2: SYSCFG configuration register 1
	// Position of LOCKUP_LOCK field.
	SYSCFG_CFGR2_LOCKUP_LOCK_Pos = 0x0
	// Bit mask of LOCKUP_LOCK field.
	SYSCFG_CFGR2_LOCKUP_LOCK_Msk = 0x1
	// Bit LOCKUP_LOCK.
	SYSCFG_CFGR2_LOCKUP_LOCK = 0x1
	// error not connected to timers
	SYSCFG_CFGR2_LOCKUP_LOCK_Disabled = 0x0
	// error triggers TIM1/15/16/17 break input
	SYSCFG_CFGR2_LOCKUP_LOCK_Enabled = 0x1
	// Position of SRAM_PARITY_LOCK field.
	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos = 0x1
	// Bit mask of SRAM_PARITY_LOCK field.
	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk = 0x2
	// Bit SRAM_PARITY_LOCK.
	SYSCFG_CFGR2_SRAM_PARITY_LOCK = 0x2
	// error not connected to timers
	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Disabled = 0x0
	// error triggers TIM1/15/16/17 break input
	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Enabled = 0x1
	// Position of ECC_LOCK field.
	SYSCFG_CFGR2_ECC_LOCK_Pos = 0x3
	// Bit mask of ECC_LOCK field.
	SYSCFG_CFGR2_ECC_LOCK_Msk = 0x8
	// Bit ECC_LOCK.
	SYSCFG_CFGR2_ECC_LOCK = 0x8
	// error not connected to timers
	SYSCFG_CFGR2_ECC_LOCK_Disabled = 0x0
	// error triggers TIM1/15/16/17 break input
	SYSCFG_CFGR2_ECC_LOCK_Enabled = 0x1
	// Position of SRAM_PEF field.
	SYSCFG_CFGR2_SRAM_PEF_Pos = 0x8
	// Bit mask of SRAM_PEF field.
	SYSCFG_CFGR2_SRAM_PEF_Msk = 0x100
	// Bit SRAM_PEF.
	SYSCFG_CFGR2_SRAM_PEF = 0x100
	// No SRAM parity error detected
	SYSCFG_CFGR2_SRAM_PEF_Normal = 0x0
	// SRAM parity error detected
	SYSCFG_CFGR2_SRAM_PEF_Error = 0x1

	// ITLINE0: interrupt line 0 status register
	// Position of WWDG field.
	SYSCFG_ITLINE0_WWDG_Pos = 0x0
	// Bit mask of WWDG field.
	SYSCFG_ITLINE0_WWDG_Msk = 0x1
	// Bit WWDG.
	SYSCFG_ITLINE0_WWDG = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE0_WWDG_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE0_WWDG_Interrupted = 0x1

	// ITLINE2: interrupt line 2 status register
	// Position of TAMP field.
	SYSCFG_ITLINE2_TAMP_Pos = 0x0
	// Bit mask of TAMP field.
	SYSCFG_ITLINE2_TAMP_Msk = 0x1
	// Bit TAMP.
	SYSCFG_ITLINE2_TAMP = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE2_TAMP_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE2_TAMP_Interrupted = 0x1
	// Position of RTC field.
	SYSCFG_ITLINE2_RTC_Pos = 0x1
	// Bit mask of RTC field.
	SYSCFG_ITLINE2_RTC_Msk = 0x2
	// Bit RTC.
	SYSCFG_ITLINE2_RTC = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE2_RTC_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE2_RTC_Interrupted = 0x1

	// ITLINE3: interrupt line 3 status register
	// Position of FLASH_ITF field.
	SYSCFG_ITLINE3_FLASH_ITF_Pos = 0x0
	// Bit mask of FLASH_ITF field.
	SYSCFG_ITLINE3_FLASH_ITF_Msk = 0x1
	// Bit FLASH_ITF.
	SYSCFG_ITLINE3_FLASH_ITF = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE3_FLASH_ITF_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE3_FLASH_ITF_Interrupted = 0x1
	// Position of FLASH_ECC field.
	SYSCFG_ITLINE3_FLASH_ECC_Pos = 0x1
	// Bit mask of FLASH_ECC field.
	SYSCFG_ITLINE3_FLASH_ECC_Msk = 0x2
	// Bit FLASH_ECC.
	SYSCFG_ITLINE3_FLASH_ECC = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE3_FLASH_ECC_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE3_FLASH_ECC_Interrupted = 0x1

	// ITLINE4: interrupt line 4 status register
	// Position of RCC field.
	SYSCFG_ITLINE4_RCC_Pos = 0x0
	// Bit mask of RCC field.
	SYSCFG_ITLINE4_RCC_Msk = 0x1
	// Bit RCC.
	SYSCFG_ITLINE4_RCC = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE4_RCC_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE4_RCC_Interrupted = 0x1

	// ITLINE5: interrupt line 5 status register
	// Position of EXTI0 field.
	SYSCFG_ITLINE5_EXTI0_Pos = 0x0
	// Bit mask of EXTI0 field.
	SYSCFG_ITLINE5_EXTI0_Msk = 0x1
	// Bit EXTI0.
	SYSCFG_ITLINE5_EXTI0 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE5_EXTI0_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE5_EXTI0_Interrupted = 0x1
	// Position of EXTI1 field.
	SYSCFG_ITLINE5_EXTI1_Pos = 0x1
	// Bit mask of EXTI1 field.
	SYSCFG_ITLINE5_EXTI1_Msk = 0x2
	// Bit EXTI1.
	SYSCFG_ITLINE5_EXTI1 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE5_EXTI1_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE5_EXTI1_Interrupted = 0x1

	// ITLINE6: interrupt line 6 status register
	// Position of EXTI2 field.
	SYSCFG_ITLINE6_EXTI2_Pos = 0x0
	// Bit mask of EXTI2 field.
	SYSCFG_ITLINE6_EXTI2_Msk = 0x1
	// Bit EXTI2.
	SYSCFG_ITLINE6_EXTI2 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE6_EXTI2_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE6_EXTI2_Interrupted = 0x1
	// Position of EXTI3 field.
	SYSCFG_ITLINE6_EXTI3_Pos = 0x1
	// Bit mask of EXTI3 field.
	SYSCFG_ITLINE6_EXTI3_Msk = 0x2
	// Bit EXTI3.
	SYSCFG_ITLINE6_EXTI3 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE6_EXTI3_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE6_EXTI3_Interrupted = 0x1

	// ITLINE7: interrupt line 7 status register
	// Position of EXTI4 field.
	SYSCFG_ITLINE7_EXTI4_Pos = 0x0
	// Bit mask of EXTI4 field.
	SYSCFG_ITLINE7_EXTI4_Msk = 0x1
	// Bit EXTI4.
	SYSCFG_ITLINE7_EXTI4 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI4_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI4_Interrupted = 0x1
	// Position of EXTI5 field.
	SYSCFG_ITLINE7_EXTI5_Pos = 0x1
	// Bit mask of EXTI5 field.
	SYSCFG_ITLINE7_EXTI5_Msk = 0x2
	// Bit EXTI5.
	SYSCFG_ITLINE7_EXTI5 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI5_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI5_Interrupted = 0x1
	// Position of EXTI6 field.
	SYSCFG_ITLINE7_EXTI6_Pos = 0x2
	// Bit mask of EXTI6 field.
	SYSCFG_ITLINE7_EXTI6_Msk = 0x4
	// Bit EXTI6.
	SYSCFG_ITLINE7_EXTI6 = 0x4
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI6_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI6_Interrupted = 0x1
	// Position of EXTI7 field.
	SYSCFG_ITLINE7_EXTI7_Pos = 0x3
	// Bit mask of EXTI7 field.
	SYSCFG_ITLINE7_EXTI7_Msk = 0x8
	// Bit EXTI7.
	SYSCFG_ITLINE7_EXTI7 = 0x8
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI7_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI7_Interrupted = 0x1
	// Position of EXTI8 field.
	SYSCFG_ITLINE7_EXTI8_Pos = 0x4
	// Bit mask of EXTI8 field.
	SYSCFG_ITLINE7_EXTI8_Msk = 0x10
	// Bit EXTI8.
	SYSCFG_ITLINE7_EXTI8 = 0x10
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI8_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI8_Interrupted = 0x1
	// Position of EXTI9 field.
	SYSCFG_ITLINE7_EXTI9_Pos = 0x5
	// Bit mask of EXTI9 field.
	SYSCFG_ITLINE7_EXTI9_Msk = 0x20
	// Bit EXTI9.
	SYSCFG_ITLINE7_EXTI9 = 0x20
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI9_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI9_Interrupted = 0x1
	// Position of EXTI10 field.
	SYSCFG_ITLINE7_EXTI10_Pos = 0x6
	// Bit mask of EXTI10 field.
	SYSCFG_ITLINE7_EXTI10_Msk = 0x40
	// Bit EXTI10.
	SYSCFG_ITLINE7_EXTI10 = 0x40
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI10_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI10_Interrupted = 0x1
	// Position of EXTI11 field.
	SYSCFG_ITLINE7_EXTI11_Pos = 0x7
	// Bit mask of EXTI11 field.
	SYSCFG_ITLINE7_EXTI11_Msk = 0x80
	// Bit EXTI11.
	SYSCFG_ITLINE7_EXTI11 = 0x80
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI11_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI11_Interrupted = 0x1
	// Position of EXTI12 field.
	SYSCFG_ITLINE7_EXTI12_Pos = 0x8
	// Bit mask of EXTI12 field.
	SYSCFG_ITLINE7_EXTI12_Msk = 0x100
	// Bit EXTI12.
	SYSCFG_ITLINE7_EXTI12 = 0x100
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI12_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI12_Interrupted = 0x1
	// Position of EXTI13 field.
	SYSCFG_ITLINE7_EXTI13_Pos = 0x9
	// Bit mask of EXTI13 field.
	SYSCFG_ITLINE7_EXTI13_Msk = 0x200
	// Bit EXTI13.
	SYSCFG_ITLINE7_EXTI13 = 0x200
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI13_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI13_Interrupted = 0x1
	// Position of EXTI14 field.
	SYSCFG_ITLINE7_EXTI14_Pos = 0xa
	// Bit mask of EXTI14 field.
	SYSCFG_ITLINE7_EXTI14_Msk = 0x400
	// Bit EXTI14.
	SYSCFG_ITLINE7_EXTI14 = 0x400
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI14_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI14_Interrupted = 0x1
	// Position of EXTI15 field.
	SYSCFG_ITLINE7_EXTI15_Pos = 0xb
	// Bit mask of EXTI15 field.
	SYSCFG_ITLINE7_EXTI15_Msk = 0x800
	// Bit EXTI15.
	SYSCFG_ITLINE7_EXTI15 = 0x800
	// Interrupt not triggered
	SYSCFG_ITLINE7_EXTI15_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE7_EXTI15_Interrupted = 0x1

	// ITLINE8: interrupt line 8 status register
	// Position of USB field.
	SYSCFG_ITLINE8_USB_Pos = 0x2
	// Bit mask of USB field.
	SYSCFG_ITLINE8_USB_Msk = 0x4
	// Bit USB.
	SYSCFG_ITLINE8_USB = 0x4
	// Interrupt not triggered
	SYSCFG_ITLINE8_USB_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE8_USB_Interrupted = 0x1

	// ITLINE9: interrupt line 9 status register
	// Position of DMA1_CH1 field.
	SYSCFG_ITLINE9_DMA1_CH1_Pos = 0x0
	// Bit mask of DMA1_CH1 field.
	SYSCFG_ITLINE9_DMA1_CH1_Msk = 0x1
	// Bit DMA1_CH1.
	SYSCFG_ITLINE9_DMA1_CH1 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE9_DMA1_CH1_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE9_DMA1_CH1_Interrupted = 0x1

	// ITLINE10: interrupt line 10 status register
	// Position of DMA1_CH2 field.
	SYSCFG_ITLINE10_DMA1_CH2_Pos = 0x0
	// Bit mask of DMA1_CH2 field.
	SYSCFG_ITLINE10_DMA1_CH2_Msk = 0x1
	// Bit DMA1_CH2.
	SYSCFG_ITLINE10_DMA1_CH2 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE10_DMA1_CH2_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE10_DMA1_CH2_Interrupted = 0x1
	// Position of DMA1_CH3 field.
	SYSCFG_ITLINE10_DMA1_CH3_Pos = 0x1
	// Bit mask of DMA1_CH3 field.
	SYSCFG_ITLINE10_DMA1_CH3_Msk = 0x2
	// Bit DMA1_CH3.
	SYSCFG_ITLINE10_DMA1_CH3 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE10_DMA1_CH3_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE10_DMA1_CH3_Interrupted = 0x1

	// ITLINE11: interrupt line 11 status register
	// Position of DMAMUX field.
	SYSCFG_ITLINE11_DMAMUX_Pos = 0x0
	// Bit mask of DMAMUX field.
	SYSCFG_ITLINE11_DMAMUX_Msk = 0x1
	// Bit DMAMUX.
	SYSCFG_ITLINE11_DMAMUX = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE11_DMAMUX_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE11_DMAMUX_Interrupted = 0x1
	// Position of DMA1_CH4 field.
	SYSCFG_ITLINE11_DMA1_CH4_Pos = 0x1
	// Bit mask of DMA1_CH4 field.
	SYSCFG_ITLINE11_DMA1_CH4_Msk = 0x2
	// Bit DMA1_CH4.
	SYSCFG_ITLINE11_DMA1_CH4 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE11_DMA1_CH4_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE11_DMA1_CH4_Interrupted = 0x1
	// Position of DMA1_CH5 field.
	SYSCFG_ITLINE11_DMA1_CH5_Pos = 0x2
	// Bit mask of DMA1_CH5 field.
	SYSCFG_ITLINE11_DMA1_CH5_Msk = 0x4
	// Bit DMA1_CH5.
	SYSCFG_ITLINE11_DMA1_CH5 = 0x4
	// Interrupt not triggered
	SYSCFG_ITLINE11_DMA1_CH5_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE11_DMA1_CH5_Interrupted = 0x1
	// Position of DMA1_CH6 field.
	SYSCFG_ITLINE11_DMA1_CH6_Pos = 0x3
	// Bit mask of DMA1_CH6 field.
	SYSCFG_ITLINE11_DMA1_CH6_Msk = 0x8
	// Bit DMA1_CH6.
	SYSCFG_ITLINE11_DMA1_CH6 = 0x8
	// Interrupt not triggered
	SYSCFG_ITLINE11_DMA1_CH6_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE11_DMA1_CH6_Interrupted = 0x1
	// Position of DMA1_CH7 field.
	SYSCFG_ITLINE11_DMA1_CH7_Pos = 0x4
	// Bit mask of DMA1_CH7 field.
	SYSCFG_ITLINE11_DMA1_CH7_Msk = 0x10
	// Bit DMA1_CH7.
	SYSCFG_ITLINE11_DMA1_CH7 = 0x10
	// Interrupt not triggered
	SYSCFG_ITLINE11_DMA1_CH7_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE11_DMA1_CH7_Interrupted = 0x1

	// ITLINE12: interrupt line 12 status register
	// Position of ADC field.
	SYSCFG_ITLINE12_ADC_Pos = 0x0
	// Bit mask of ADC field.
	SYSCFG_ITLINE12_ADC_Msk = 0x1
	// Bit ADC.
	SYSCFG_ITLINE12_ADC = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE12_ADC_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE12_ADC_Interrupted = 0x1

	// ITLINE13: interrupt line 13 status register
	// Position of TIM1_CCU field.
	SYSCFG_ITLINE13_TIM1_CCU_Pos = 0x0
	// Bit mask of TIM1_CCU field.
	SYSCFG_ITLINE13_TIM1_CCU_Msk = 0x1
	// Bit TIM1_CCU.
	SYSCFG_ITLINE13_TIM1_CCU = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE13_TIM1_CCU_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE13_TIM1_CCU_Interrupted = 0x1
	// Position of TIM1_TRG field.
	SYSCFG_ITLINE13_TIM1_TRG_Pos = 0x1
	// Bit mask of TIM1_TRG field.
	SYSCFG_ITLINE13_TIM1_TRG_Msk = 0x2
	// Bit TIM1_TRG.
	SYSCFG_ITLINE13_TIM1_TRG = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE13_TIM1_TRG_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE13_TIM1_TRG_Interrupted = 0x1
	// Position of TIM1_UPD field.
	SYSCFG_ITLINE13_TIM1_UPD_Pos = 0x2
	// Bit mask of TIM1_UPD field.
	SYSCFG_ITLINE13_TIM1_UPD_Msk = 0x4
	// Bit TIM1_UPD.
	SYSCFG_ITLINE13_TIM1_UPD = 0x4
	// Interrupt not triggered
	SYSCFG_ITLINE13_TIM1_UPD_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE13_TIM1_UPD_Interrupted = 0x1
	// Position of TIM1_BRK field.
	SYSCFG_ITLINE13_TIM1_BRK_Pos = 0x3
	// Bit mask of TIM1_BRK field.
	SYSCFG_ITLINE13_TIM1_BRK_Msk = 0x8
	// Bit TIM1_BRK.
	SYSCFG_ITLINE13_TIM1_BRK = 0x8
	// Interrupt not triggered
	SYSCFG_ITLINE13_TIM1_BRK_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE13_TIM1_BRK_Interrupted = 0x1

	// ITLINE14: interrupt line 14 status register
	// Position of TIM1_CC field.
	SYSCFG_ITLINE14_TIM1_CC_Pos = 0x0
	// Bit mask of TIM1_CC field.
	SYSCFG_ITLINE14_TIM1_CC_Msk = 0x1
	// Bit TIM1_CC.
	SYSCFG_ITLINE14_TIM1_CC = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE14_TIM1_CC_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE14_TIM1_CC_Interrupted = 0x1

	// ITLINE16: interrupt line 16 status register
	// Position of TIM3 field.
	SYSCFG_ITLINE16_TIM3_Pos = 0x0
	// Bit mask of TIM3 field.
	SYSCFG_ITLINE16_TIM3_Msk = 0x1
	// Bit TIM3.
	SYSCFG_ITLINE16_TIM3 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE16_TIM3_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE16_TIM3_Interrupted = 0x1
	// Position of TIM4 field.
	SYSCFG_ITLINE16_TIM4_Pos = 0x1
	// Bit mask of TIM4 field.
	SYSCFG_ITLINE16_TIM4_Msk = 0x2
	// Bit TIM4.
	SYSCFG_ITLINE16_TIM4 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE16_TIM4_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE16_TIM4_Interrupted = 0x1

	// ITLINE17: interrupt line 17 status register
	// Position of TIM6 field.
	SYSCFG_ITLINE17_TIM6_Pos = 0x0
	// Bit mask of TIM6 field.
	SYSCFG_ITLINE17_TIM6_Msk = 0x1
	// Bit TIM6.
	SYSCFG_ITLINE17_TIM6 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE17_TIM6_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE17_TIM6_Interrupted = 0x1

	// ITLINE18: interrupt line 18 status register
	// Position of TIM7 field.
	SYSCFG_ITLINE18_TIM7_Pos = 0x0
	// Bit mask of TIM7 field.
	SYSCFG_ITLINE18_TIM7_Msk = 0x1
	// Bit TIM7.
	SYSCFG_ITLINE18_TIM7 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE18_TIM7_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE18_TIM7_Interrupted = 0x1

	// ITLINE19: interrupt line 19 status register
	// Position of TIM14 field.
	SYSCFG_ITLINE19_TIM14_Pos = 0x0
	// Bit mask of TIM14 field.
	SYSCFG_ITLINE19_TIM14_Msk = 0x1
	// Bit TIM14.
	SYSCFG_ITLINE19_TIM14 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE19_TIM14_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE19_TIM14_Interrupted = 0x1

	// ITLINE20: interrupt line 20 status register
	// Position of TIM15 field.
	SYSCFG_ITLINE20_TIM15_Pos = 0x0
	// Bit mask of TIM15 field.
	SYSCFG_ITLINE20_TIM15_Msk = 0x1
	// Bit TIM15.
	SYSCFG_ITLINE20_TIM15 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE20_TIM15_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE20_TIM15_Interrupted = 0x1

	// ITLINE21: interrupt line 21 status register
	// Position of TIM16 field.
	SYSCFG_ITLINE21_TIM16_Pos = 0x0
	// Bit mask of TIM16 field.
	SYSCFG_ITLINE21_TIM16_Msk = 0x1
	// Bit TIM16.
	SYSCFG_ITLINE21_TIM16 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE21_TIM16_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE21_TIM16_Interrupted = 0x1

	// ITLINE22: interrupt line 22 status register
	// Position of TIM17 field.
	SYSCFG_ITLINE22_TIM17_Pos = 0x0
	// Bit mask of TIM17 field.
	SYSCFG_ITLINE22_TIM17_Msk = 0x1
	// Bit TIM17.
	SYSCFG_ITLINE22_TIM17 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE22_TIM17_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE22_TIM17_Interrupted = 0x1

	// ITLINE23: interrupt line 23 status register
	// Position of I2C1 field.
	SYSCFG_ITLINE23_I2C1_Pos = 0x0
	// Bit mask of I2C1 field.
	SYSCFG_ITLINE23_I2C1_Msk = 0x1
	// Bit I2C1.
	SYSCFG_ITLINE23_I2C1 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE23_I2C1_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE23_I2C1_Interrupted = 0x1

	// ITLINE24: interrupt line 24 status register
	// Position of I2C2 field.
	SYSCFG_ITLINE24_I2C2_Pos = 0x0
	// Bit mask of I2C2 field.
	SYSCFG_ITLINE24_I2C2_Msk = 0x1
	// Bit I2C2.
	SYSCFG_ITLINE24_I2C2 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE24_I2C2_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE24_I2C2_Interrupted = 0x1
	// Position of I2C3 field.
	SYSCFG_ITLINE24_I2C3_Pos = 0x1
	// Bit mask of I2C3 field.
	SYSCFG_ITLINE24_I2C3_Msk = 0x2
	// Bit I2C3.
	SYSCFG_ITLINE24_I2C3 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE24_I2C3_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE24_I2C3_Interrupted = 0x1

	// ITLINE25: interrupt line 25 status register
	// Position of SPI1 field.
	SYSCFG_ITLINE25_SPI1_Pos = 0x0
	// Bit mask of SPI1 field.
	SYSCFG_ITLINE25_SPI1_Msk = 0x1
	// Bit SPI1.
	SYSCFG_ITLINE25_SPI1 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE25_SPI1_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE25_SPI1_Interrupted = 0x1

	// ITLINE26: interrupt line 26 status register
	// Position of SPI2 field.
	SYSCFG_ITLINE26_SPI2_Pos = 0x0
	// Bit mask of SPI2 field.
	SYSCFG_ITLINE26_SPI2_Msk = 0x1
	// Bit SPI2.
	SYSCFG_ITLINE26_SPI2 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE26_SPI2_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE26_SPI2_Interrupted = 0x1
	// Position of SPI3 field.
	SYSCFG_ITLINE26_SPI3_Pos = 0xe
	// Bit mask of SPI3 field.
	SYSCFG_ITLINE26_SPI3_Msk = 0x4000
	// Bit SPI3.
	SYSCFG_ITLINE26_SPI3 = 0x4000
	// Interrupt not triggered
	SYSCFG_ITLINE26_SPI3_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE26_SPI3_Interrupted = 0x1

	// ITLINE27: interrupt line 27 status register
	// Position of USART1 field.
	SYSCFG_ITLINE27_USART1_Pos = 0x0
	// Bit mask of USART1 field.
	SYSCFG_ITLINE27_USART1_Msk = 0x1
	// Bit USART1.
	SYSCFG_ITLINE27_USART1 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE27_USART1_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE27_USART1_Interrupted = 0x1

	// ITLINE28: interrupt line 28 status register
	// Position of USART2 field.
	SYSCFG_ITLINE28_USART2_Pos = 0x0
	// Bit mask of USART2 field.
	SYSCFG_ITLINE28_USART2_Msk = 0x1
	// Bit USART2.
	SYSCFG_ITLINE28_USART2 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE28_USART2_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE28_USART2_Interrupted = 0x1

	// ITLINE29: interrupt line 29 status register
	// Position of USART3 field.
	SYSCFG_ITLINE29_USART3_Pos = 0x0
	// Bit mask of USART3 field.
	SYSCFG_ITLINE29_USART3_Msk = 0x1
	// Bit USART3.
	SYSCFG_ITLINE29_USART3 = 0x1
	// Interrupt not triggered
	SYSCFG_ITLINE29_USART3_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE29_USART3_Interrupted = 0x1
	// Position of USART4 field.
	SYSCFG_ITLINE29_USART4_Pos = 0x1
	// Bit mask of USART4 field.
	SYSCFG_ITLINE29_USART4_Msk = 0x2
	// Bit USART4.
	SYSCFG_ITLINE29_USART4 = 0x2
	// Interrupt not triggered
	SYSCFG_ITLINE29_USART4_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE29_USART4_Interrupted = 0x1
	// Position of USART5 field.
	SYSCFG_ITLINE29_USART5_Pos = 0x3
	// Bit mask of USART5 field.
	SYSCFG_ITLINE29_USART5_Msk = 0x8
	// Bit USART5.
	SYSCFG_ITLINE29_USART5 = 0x8
	// Interrupt not triggered
	SYSCFG_ITLINE29_USART5_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE29_USART5_Interrupted = 0x1
	// Position of USART6 field.
	SYSCFG_ITLINE29_USART6_Pos = 0x4
	// Bit mask of USART6 field.
	SYSCFG_ITLINE29_USART6_Msk = 0x10
	// Bit USART6.
	SYSCFG_ITLINE29_USART6 = 0x10
	// Interrupt not triggered
	SYSCFG_ITLINE29_USART6_NotInterrupted = 0x0
	// Interrup triggered
	SYSCFG_ITLINE29_USART6_Interrupted = 0x1
)

// Constants for TAMP: Tamper and backup registers
const (
	// CR1: TAMP control register 1
	// Position of TAMP1E field.
	TAMP_CR1_TAMP1E_Pos = 0x0
	// Bit mask of TAMP1E field.
	TAMP_CR1_TAMP1E_Msk = 0x1
	// Bit TAMP1E.
	TAMP_CR1_TAMP1E = 0x1
	// Position of TAMP2E field.
	TAMP_CR1_TAMP2E_Pos = 0x1
	// Bit mask of TAMP2E field.
	TAMP_CR1_TAMP2E_Msk = 0x2
	// Bit TAMP2E.
	TAMP_CR1_TAMP2E = 0x2
	// Position of TAMP3E field.
	TAMP_CR1_TAMP3E_Pos = 0x2
	// Bit mask of TAMP3E field.
	TAMP_CR1_TAMP3E_Msk = 0x4
	// Bit TAMP3E.
	TAMP_CR1_TAMP3E = 0x4
	// Position of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Pos = 0x12
	// Bit mask of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Msk = 0x40000
	// Bit ITAMP3E.
	TAMP_CR1_ITAMP3E = 0x40000
	// Position of ITAMP4E field.
	TAMP_CR1_ITAMP4E_Pos = 0x13
	// Bit mask of ITAMP4E field.
	TAMP_CR1_ITAMP4E_Msk = 0x80000
	// Bit ITAMP4E.
	TAMP_CR1_ITAMP4E = 0x80000
	// Position of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Pos = 0x14
	// Bit mask of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Msk = 0x100000
	// Bit ITAMP5E.
	TAMP_CR1_ITAMP5E = 0x100000
	// Position of ITAMP6E field.
	TAMP_CR1_ITAMP6E_Pos = 0x15
	// Bit mask of ITAMP6E field.
	TAMP_CR1_ITAMP6E_Msk = 0x200000
	// Bit ITAMP6E.
	TAMP_CR1_ITAMP6E = 0x200000

	// CR2: TAMP control register 2
	// Position of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Pos = 0x0
	// Bit mask of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Msk = 0x1
	// Bit TAMP1NOER.
	TAMP_CR2_TAMP1NOER = 0x1
	// Position of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Pos = 0x1
	// Bit mask of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Msk = 0x2
	// Bit TAMP2NOER.
	TAMP_CR2_TAMP2NOER = 0x2
	// Position of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Pos = 0x2
	// Bit mask of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Msk = 0x4
	// Bit TAMP3NOER.
	TAMP_CR2_TAMP3NOER = 0x4
	// Position of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Pos = 0x10
	// Bit mask of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Msk = 0x10000
	// Bit TAMP1MSK.
	TAMP_CR2_TAMP1MSK = 0x10000
	// Position of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Pos = 0x11
	// Bit mask of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Msk = 0x20000
	// Bit TAMP2MSK.
	TAMP_CR2_TAMP2MSK = 0x20000
	// Position of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Pos = 0x12
	// Bit mask of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Msk = 0x40000
	// Bit TAMP3MSK.
	TAMP_CR2_TAMP3MSK = 0x40000
	// Position of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Pos = 0x18
	// Bit mask of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Msk = 0x1000000
	// Bit TAMP1TRG.
	TAMP_CR2_TAMP1TRG = 0x1000000
	// Position of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Pos = 0x19
	// Bit mask of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Msk = 0x2000000
	// Bit TAMP2TRG.
	TAMP_CR2_TAMP2TRG = 0x2000000
	// Position of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Pos = 0x1a
	// Bit mask of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Msk = 0x4000000
	// Bit TAMP3TRG.
	TAMP_CR2_TAMP3TRG = 0x4000000

	// FLTCR: TAMP filter control register
	// Position of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Pos = 0x0
	// Bit mask of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Msk = 0x7
	// Position of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Pos = 0x3
	// Bit mask of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Msk = 0x18
	// Position of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Pos = 0x5
	// Bit mask of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Msk = 0x60
	// Position of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Pos = 0x7
	// Bit mask of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Msk = 0x80
	// Bit TAMPPUDIS.
	TAMP_FLTCR_TAMPPUDIS = 0x80

	// IER: TAMP interrupt enable register
	// Position of TAMP1IE field.
	TAMP_IER_TAMP1IE_Pos = 0x0
	// Bit mask of TAMP1IE field.
	TAMP_IER_TAMP1IE_Msk = 0x1
	// Bit TAMP1IE.
	TAMP_IER_TAMP1IE = 0x1
	// Position of TAMP2IE field.
	TAMP_IER_TAMP2IE_Pos = 0x1
	// Bit mask of TAMP2IE field.
	TAMP_IER_TAMP2IE_Msk = 0x2
	// Bit TAMP2IE.
	TAMP_IER_TAMP2IE = 0x2
	// Position of TAMP3IE field.
	TAMP_IER_TAMP3IE_Pos = 0x2
	// Bit mask of TAMP3IE field.
	TAMP_IER_TAMP3IE_Msk = 0x4
	// Bit TAMP3IE.
	TAMP_IER_TAMP3IE = 0x4
	// Position of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Pos = 0x12
	// Bit mask of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Msk = 0x40000
	// Bit ITAMP3IE.
	TAMP_IER_ITAMP3IE = 0x40000
	// Position of ITAMP4IE field.
	TAMP_IER_ITAMP4IE_Pos = 0x13
	// Bit mask of ITAMP4IE field.
	TAMP_IER_ITAMP4IE_Msk = 0x80000
	// Bit ITAMP4IE.
	TAMP_IER_ITAMP4IE = 0x80000
	// Position of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Pos = 0x14
	// Bit mask of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Msk = 0x100000
	// Bit ITAMP5IE.
	TAMP_IER_ITAMP5IE = 0x100000
	// Position of ITAMP6IE field.
	TAMP_IER_ITAMP6IE_Pos = 0x15
	// Bit mask of ITAMP6IE field.
	TAMP_IER_ITAMP6IE_Msk = 0x200000
	// Bit ITAMP6IE.
	TAMP_IER_ITAMP6IE = 0x200000

	// SR: TAMP status register
	// Position of TAMP1F field.
	TAMP_SR_TAMP1F_Pos = 0x0
	// Bit mask of TAMP1F field.
	TAMP_SR_TAMP1F_Msk = 0x1
	// Bit TAMP1F.
	TAMP_SR_TAMP1F = 0x1
	// Position of TAMP2F field.
	TAMP_SR_TAMP2F_Pos = 0x1
	// Bit mask of TAMP2F field.
	TAMP_SR_TAMP2F_Msk = 0x2
	// Bit TAMP2F.
	TAMP_SR_TAMP2F = 0x2
	// Position of TAMP3F field.
	TAMP_SR_TAMP3F_Pos = 0x2
	// Bit mask of TAMP3F field.
	TAMP_SR_TAMP3F_Msk = 0x4
	// Bit TAMP3F.
	TAMP_SR_TAMP3F = 0x4
	// Position of ITAMP3F field.
	TAMP_SR_ITAMP3F_Pos = 0x12
	// Bit mask of ITAMP3F field.
	TAMP_SR_ITAMP3F_Msk = 0x40000
	// Bit ITAMP3F.
	TAMP_SR_ITAMP3F = 0x40000
	// Position of ITAMP4F field.
	TAMP_SR_ITAMP4F_Pos = 0x13
	// Bit mask of ITAMP4F field.
	TAMP_SR_ITAMP4F_Msk = 0x80000
	// Bit ITAMP4F.
	TAMP_SR_ITAMP4F = 0x80000
	// Position of ITAMP5F field.
	TAMP_SR_ITAMP5F_Pos = 0x14
	// Bit mask of ITAMP5F field.
	TAMP_SR_ITAMP5F_Msk = 0x100000
	// Bit ITAMP5F.
	TAMP_SR_ITAMP5F = 0x100000
	// Position of ITAMP6F field.
	TAMP_SR_ITAMP6F_Pos = 0x15
	// Bit mask of ITAMP6F field.
	TAMP_SR_ITAMP6F_Msk = 0x200000
	// Bit ITAMP6F.
	TAMP_SR_ITAMP6F = 0x200000

	// MISR: TAMP masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_MISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_MISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_MISR_TAMP3MF = 0x4
	// Position of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_MISR_ITAMP3MF = 0x40000
	// Position of ITAMP4MF field.
	TAMP_MISR_ITAMP4MF_Pos = 0x13
	// Bit mask of ITAMP4MF field.
	TAMP_MISR_ITAMP4MF_Msk = 0x80000
	// Bit ITAMP4MF.
	TAMP_MISR_ITAMP4MF = 0x80000
	// Position of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_MISR_ITAMP5MF = 0x100000
	// Position of ITAMP6MF field.
	TAMP_MISR_ITAMP6MF_Pos = 0x15
	// Bit mask of ITAMP6MF field.
	TAMP_MISR_ITAMP6MF_Msk = 0x200000
	// Bit ITAMP6MF.
	TAMP_MISR_ITAMP6MF = 0x200000

	// SCR: TAMP status clear register
	// Position of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Pos = 0x0
	// Bit mask of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Msk = 0x1
	// Bit CTAMP1F.
	TAMP_SCR_CTAMP1F = 0x1
	// Position of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Pos = 0x1
	// Bit mask of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Msk = 0x2
	// Bit CTAMP2F.
	TAMP_SCR_CTAMP2F = 0x2
	// Position of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Pos = 0x2
	// Bit mask of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Msk = 0x4
	// Bit CTAMP3F.
	TAMP_SCR_CTAMP3F = 0x4
	// Position of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Pos = 0x12
	// Bit mask of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Msk = 0x40000
	// Bit CITAMP3F.
	TAMP_SCR_CITAMP3F = 0x40000
	// Position of CITAMP4F field.
	TAMP_SCR_CITAMP4F_Pos = 0x13
	// Bit mask of CITAMP4F field.
	TAMP_SCR_CITAMP4F_Msk = 0x80000
	// Bit CITAMP4F.
	TAMP_SCR_CITAMP4F = 0x80000
	// Position of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Pos = 0x14
	// Bit mask of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Msk = 0x100000
	// Bit CITAMP5F.
	TAMP_SCR_CITAMP5F = 0x100000
	// Position of CITAMP6F field.
	TAMP_SCR_CITAMP6F_Pos = 0x15
	// Bit mask of CITAMP6F field.
	TAMP_SCR_CITAMP6F_Msk = 0x200000
	// Bit CITAMP6F.
	TAMP_SCR_CITAMP6F = 0x200000

	// BKP0R: TAMP backup %s register
	// Position of BKP field.
	TAMP_BKPR_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_BKPR_BKP_Msk = 0xffffffff
)

// Constants for TIM1: Advanced-timers
const (
	// CR1: control register 1
	// Position of CEN field.
	TIM_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM_CR1_CEN = 0x1
	// Counter disabled
	TIM_CR1_CEN_Disabled = 0x0
	// Counter enabled
	TIM_CR1_CEN_Enabled = 0x1
	// Position of UDIS field.
	TIM_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM_CR1_UDIS = 0x2
	// Update event enabled
	TIM_CR1_UDIS_Enabled = 0x0
	// Update event disabled
	TIM_CR1_UDIS_Disabled = 0x1
	// Position of URS field.
	TIM_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM_CR1_URS = 0x4
	// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
	TIM_CR1_URS_AnyEvent = 0x0
	// Only counter overflow/underflow generates an update interrupt or DMA request
	TIM_CR1_URS_CounterOnly = 0x1
	// Position of OPM field.
	TIM_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM_CR1_OPM = 0x8
	// Counter is not stopped at update event
	TIM_CR1_OPM_Disabled = 0x0
	// Counter stops counting at the next update event (clearing the CEN bit)
	TIM_CR1_OPM_Enabled = 0x1
	// Position of DIR field.
	TIM_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM_CR1_DIR = 0x10
	// Counter used as upcounter
	TIM_CR1_DIR_Up = 0x0
	// Counter used as downcounter
	TIM_CR1_DIR_Down = 0x1
	// Position of CMS field.
	TIM_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM_CR1_CMS_Msk = 0x60
	// The counter counts up or down depending on the direction bit
	TIM_CR1_CMS_EdgeAligned = 0x0
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
	TIM_CR1_CMS_CenterAligned1 = 0x1
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
	TIM_CR1_CMS_CenterAligned2 = 0x2
	// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
	TIM_CR1_CMS_CenterAligned3 = 0x3
	// Position of ARPE field.
	TIM_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM_CR1_ARPE = 0x80
	// TIMx_APRR register is not buffered
	TIM_CR1_ARPE_Disabled = 0x0
	// TIMx_APRR register is buffered
	TIM_CR1_ARPE_Enabled = 0x1
	// Position of CKD field.
	TIM_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM_CR1_CKD_Msk = 0x300
	// t_DTS = t_CK_INT
	TIM_CR1_CKD_Div1 = 0x0
	// t_DTS = 2 × t_CK_INT
	TIM_CR1_CKD_Div2 = 0x1
	// t_DTS = 4 × t_CK_INT
	TIM_CR1_CKD_Div4 = 0x2
	// Position of UIFREMAP field.
	TIM_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM_CR1_UIFREMAP = 0x800

	// CR2: control register 2
	// Position of CCPC field.
	TIM_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM_CR2_CCPC = 0x1
	// CCxE, CCxNE and OCxM bits are not preloaded
	TIM_CR2_CCPC_NotPreloaded = 0x0
	// CCxE, CCxNE and OCxM bits are preloaded
	TIM_CR2_CCPC_Preloaded = 0x1
	// Position of CCUS field.
	TIM_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM_CR2_CCUS = 0x4
	// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
	TIM_CR2_CCUS_Sw = 0x0
	// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
	TIM_CR2_CCUS_SwOrEdge = 0x1
	// Position of CCDS field.
	TIM_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM_CR2_CCDS = 0x8
	// CCx DMA request sent when CCx event occurs
	TIM_CR2_CCDS_OnCompare = 0x0
	// CCx DMA request sent when update event occurs
	TIM_CR2_CCDS_OnUpdate = 0x1
	// Position of MMS field.
	TIM_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM_CR2_TI1S = 0x80
	// The TIMx_CH1 pin is connected to TI1 input
	TIM_CR2_TI1S_Normal = 0x0
	// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
	TIM_CR2_TI1S_XOR = 0x1
	// Position of OIS1 field.
	TIM_CR2_OIS1_Pos = 0xa
	// Bit mask of OIS1 field.
	TIM_CR2_OIS1_Msk = 0x400
	// Bit OIS1.
	TIM_CR2_OIS1 = 0x400
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS1_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS1_Set = 0x1
	// Position of OIS2 field.
	TIM_CR2_OIS2_Pos = 0xc
	// Bit mask of OIS2 field.
	TIM_CR2_OIS2_Msk = 0x1000
	// Bit OIS2.
	TIM_CR2_OIS2 = 0x1000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS2_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS2_Set = 0x1
	// Position of OIS3 field.
	TIM_CR2_OIS3_Pos = 0xe
	// Bit mask of OIS3 field.
	TIM_CR2_OIS3_Msk = 0x4000
	// Bit OIS3.
	TIM_CR2_OIS3 = 0x4000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS3_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS3_Set = 0x1
	// Position of OIS4 field.
	TIM_CR2_OIS4_Pos = 0x10
	// Bit mask of OIS4 field.
	TIM_CR2_OIS4_Msk = 0x10000
	// Bit OIS4.
	TIM_CR2_OIS4 = 0x10000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS4_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS4_Set = 0x1
	// Position of OIS5 field.
	TIM_CR2_OIS5_Pos = 0x12
	// Bit mask of OIS5 field.
	TIM_CR2_OIS5_Msk = 0x40000
	// Bit OIS5.
	TIM_CR2_OIS5 = 0x40000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS5_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS5_Set = 0x1
	// Position of OIS6 field.
	TIM_CR2_OIS6_Pos = 0x14
	// Bit mask of OIS6 field.
	TIM_CR2_OIS6_Msk = 0x100000
	// Bit OIS6.
	TIM_CR2_OIS6 = 0x100000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS6_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS6_Set = 0x1
	// Position of OIS1N field.
	TIM_CR2_OIS1N_Pos = 0xb
	// Bit mask of OIS1N field.
	TIM_CR2_OIS1N_Msk = 0x800
	// Bit OIS1N.
	TIM_CR2_OIS1N = 0x800
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS1N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS1N_Set = 0x1
	// Position of OIS2N field.
	TIM_CR2_OIS2N_Pos = 0xd
	// Bit mask of OIS2N field.
	TIM_CR2_OIS2N_Msk = 0x2000
	// Bit OIS2N.
	TIM_CR2_OIS2N = 0x2000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS2N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS2N_Set = 0x1
	// Position of OIS3N field.
	TIM_CR2_OIS3N_Pos = 0xf
	// Bit mask of OIS3N field.
	TIM_CR2_OIS3N_Msk = 0x8000
	// Bit OIS3N.
	TIM_CR2_OIS3N = 0x8000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS3N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS3N_Set = 0x1
	// Position of MMS2 field.
	TIM_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM_CR2_MMS2_Msk = 0xf00000

	// SMCR: slave mode control register
	// Position of SMS field.
	TIM_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM_SMCR_SMS_Msk = 0x7
	// Position of OCCS field.
	TIM_SMCR_OCCS_Pos = 0x3
	// Bit mask of OCCS field.
	TIM_SMCR_OCCS_Msk = 0x8
	// Bit OCCS.
	TIM_SMCR_OCCS = 0x8
	// Position of TS field.
	TIM_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM_SMCR_MSM = 0x80
	// No action
	TIM_SMCR_MSM_NoSync = 0x0
	// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
	TIM_SMCR_MSM_Sync = 0x1
	// Position of ETF field.
	TIM_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM_SMCR_ETF_Msk = 0xf00
	// No filter, sampling is done at fDTS
	TIM_SMCR_ETF_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_SMCR_ETF_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_SMCR_ETF_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_SMCR_ETF_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_SMCR_ETF_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_SMCR_ETF_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_SMCR_ETF_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_SMCR_ETF_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_SMCR_ETF_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_SMCR_ETF_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_SMCR_ETF_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_SMCR_ETF_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_SMCR_ETF_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_SMCR_ETF_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_SMCR_ETF_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_SMCR_ETF_FDTS_Div32_N8 = 0xf
	// Position of ETPS field.
	TIM_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM_SMCR_ETPS_Msk = 0x3000
	// Prescaler OFF
	TIM_SMCR_ETPS_Div1 = 0x0
	// ETRP frequency divided by 2
	TIM_SMCR_ETPS_Div2 = 0x1
	// ETRP frequency divided by 4
	TIM_SMCR_ETPS_Div4 = 0x2
	// ETRP frequency divided by 8
	TIM_SMCR_ETPS_Div8 = 0x3
	// Position of ECE field.
	TIM_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM_SMCR_ECE = 0x4000
	// External clock mode 2 disabled
	TIM_SMCR_ECE_Disabled = 0x0
	// External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
	TIM_SMCR_ECE_Enabled = 0x1
	// Position of ETP field.
	TIM_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM_SMCR_ETP = 0x8000
	// ETR is noninverted, active at high level or rising edge
	TIM_SMCR_ETP_NotInverted = 0x0
	// ETR is inverted, active at low level or falling edge
	TIM_SMCR_ETP_Inverted = 0x1
	// Position of SMS_3 field.
	TIM_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIM_SMCR_SMS_3 = 0x10000
	// Position of TS2 field.
	TIM_SMCR_TS2_Pos = 0x14
	// Bit mask of TS2 field.
	TIM_SMCR_TS2_Msk = 0x300000

	// DIER: DMA/Interrupt enable register
	// Position of UIE field.
	TIM_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM_DIER_UIE = 0x1
	// Update interrupt disabled
	TIM_DIER_UIE_Disabled = 0x0
	// Update interrupt enabled
	TIM_DIER_UIE_Enabled = 0x1
	// Position of CC1IE field.
	TIM_DIER_CC1IE_Pos = 0x2
	// Bit mask of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x4
	// Bit CC1IE.
	TIM_DIER_CC1IE = 0x4
	// CCx interrupt disabled
	TIM_DIER_CC1IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC1IE_Enabled = 0x1
	// Position of CC2IE field.
	TIM_DIER_CC2IE_Pos = 0x3
	// Bit mask of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x8
	// Bit CC2IE.
	TIM_DIER_CC2IE = 0x8
	// CCx interrupt disabled
	TIM_DIER_CC2IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC2IE_Enabled = 0x1
	// Position of CC3IE field.
	TIM_DIER_CC3IE_Pos = 0x4
	// Bit mask of CC3IE field.
	TIM_DIER_CC3IE_Msk = 0x10
	// Bit CC3IE.
	TIM_DIER_CC3IE = 0x10
	// CCx interrupt disabled
	TIM_DIER_CC3IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC3IE_Enabled = 0x1
	// Position of CC4IE field.
	TIM_DIER_CC4IE_Pos = 0x5
	// Bit mask of CC4IE field.
	TIM_DIER_CC4IE_Msk = 0x20
	// Bit CC4IE.
	TIM_DIER_CC4IE = 0x20
	// CCx interrupt disabled
	TIM_DIER_CC4IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC4IE_Enabled = 0x1
	// Position of COMIE field.
	TIM_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM_DIER_COMIE = 0x20
	// COM interrupt disabled
	TIM_DIER_COMIE_Disabled = 0x0
	// COM interrupt enabled
	TIM_DIER_COMIE_Enabled = 0x1
	// Position of TIE field.
	TIM_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM_DIER_TIE = 0x40
	// Trigger interrupt disabled
	TIM_DIER_TIE_Disabled = 0x0
	// Trigger interrupt enabled
	TIM_DIER_TIE_Enabled = 0x1
	// Position of BIE field.
	TIM_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM_DIER_BIE = 0x80
	// Break interrupt disabled
	TIM_DIER_BIE_Disabled = 0x0
	// Break interrupt enabled
	TIM_DIER_BIE_Enabled = 0x1
	// Position of UDE field.
	TIM_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM_DIER_UDE = 0x100
	// Update DMA request disabled
	TIM_DIER_UDE_Disabled = 0x0
	// Update DMA request enabled
	TIM_DIER_UDE_Enabled = 0x1
	// Position of CC1DE field.
	TIM_DIER_CC1DE_Pos = 0xa
	// Bit mask of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x400
	// Bit CC1DE.
	TIM_DIER_CC1DE = 0x400
	// CCx DMA request disabled
	TIM_DIER_CC1DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC1DE_Enabled = 0x1
	// Position of CC2DE field.
	TIM_DIER_CC2DE_Pos = 0xb
	// Bit mask of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x800
	// Bit CC2DE.
	TIM_DIER_CC2DE = 0x800
	// CCx DMA request disabled
	TIM_DIER_CC2DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC2DE_Enabled = 0x1
	// Position of CC3DE field.
	TIM_DIER_CC3DE_Pos = 0xc
	// Bit mask of CC3DE field.
	TIM_DIER_CC3DE_Msk = 0x1000
	// Bit CC3DE.
	TIM_DIER_CC3DE = 0x1000
	// CCx DMA request disabled
	TIM_DIER_CC3DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC3DE_Enabled = 0x1
	// Position of CC4DE field.
	TIM_DIER_CC4DE_Pos = 0xd
	// Bit mask of CC4DE field.
	TIM_DIER_CC4DE_Msk = 0x2000
	// Bit CC4DE.
	TIM_DIER_CC4DE = 0x2000
	// CCx DMA request disabled
	TIM_DIER_CC4DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC4DE_Enabled = 0x1
	// Position of COMDE field.
	TIM_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM_DIER_COMDE = 0x2000
	// COM DMA request disabled
	TIM_DIER_COMDE_Disabled = 0x0
	// COM DMA request enabled
	TIM_DIER_COMDE_Enabled = 0x1
	// Position of TDE field.
	TIM_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM_DIER_TDE = 0x4000
	// Trigger DMA request disabled
	TIM_DIER_TDE_Disabled = 0x0
	// Trigger DMA request enabled
	TIM_DIER_TDE_Enabled = 0x1

	// SR: status register
	// Position of UIF field.
	TIM_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM_SR_UIF = 0x1
	// No update occurred
	TIM_SR_UIF_NoUpdateOccurred = 0x0
	// Update interrupt pending
	TIM_SR_UIF_UpdatePending = 0x1
	// Clear flag
	TIM_SR_UIF_Clear = 0x0
	// Position of CC1IF field.
	TIM_SR_CC1IF_Pos = 0x2
	// Bit mask of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x4
	// Bit CC1IF.
	TIM_SR_CC1IF = 0x4
	// No campture/compare has been detected
	TIM_SR_CC1IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC1IF_Match = 0x1
	// Clear flag
	TIM_SR_CC1IF_Clear = 0x0
	// Position of CC2IF field.
	TIM_SR_CC2IF_Pos = 0x3
	// Bit mask of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x8
	// Bit CC2IF.
	TIM_SR_CC2IF = 0x8
	// No campture/compare has been detected
	TIM_SR_CC2IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC2IF_Match = 0x1
	// Clear flag
	TIM_SR_CC2IF_Clear = 0x0
	// Position of CC3IF field.
	TIM_SR_CC3IF_Pos = 0x4
	// Bit mask of CC3IF field.
	TIM_SR_CC3IF_Msk = 0x10
	// Bit CC3IF.
	TIM_SR_CC3IF = 0x10
	// No campture/compare has been detected
	TIM_SR_CC3IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC3IF_Match = 0x1
	// Clear flag
	TIM_SR_CC3IF_Clear = 0x0
	// Position of CC4IF field.
	TIM_SR_CC4IF_Pos = 0x5
	// Bit mask of CC4IF field.
	TIM_SR_CC4IF_Msk = 0x20
	// Bit CC4IF.
	TIM_SR_CC4IF = 0x20
	// No campture/compare has been detected
	TIM_SR_CC4IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC4IF_Match = 0x1
	// Clear flag
	TIM_SR_CC4IF_Clear = 0x0
	// Position of COMIF field.
	TIM_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM_SR_COMIF = 0x20
	// No COM event occurred
	TIM_SR_COMIF_NoCOM = 0x0
	// COM interrupt pending
	TIM_SR_COMIF_COM = 0x1
	// Clear flag
	TIM_SR_COMIF_Clear = 0x0
	// Position of TIF field.
	TIM_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM_SR_TIF = 0x40
	// No trigger event occurred
	TIM_SR_TIF_NoTrigger = 0x0
	// Trigger interrupt pending
	TIM_SR_TIF_Trigger = 0x1
	// Clear flag
	TIM_SR_TIF_Clear = 0x0
	// Position of BIF field.
	TIM_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM_SR_BIF = 0x80
	// No break event occurred
	TIM_SR_BIF_NoTrigger = 0x0
	// An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_BIF_Trigger = 0x1
	// Clear flag
	TIM_SR_BIF_Clear = 0x0
	// Position of B2IF field.
	TIM_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM_SR_B2IF = 0x100
	// No break event occurred
	TIM_SR_B2IF_NoTrigger = 0x0
	// An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_B2IF_Trigger = 0x1
	// Clear flag
	TIM_SR_B2IF_Clear = 0x0
	// Position of CC1OF field.
	TIM_SR_CC1OF_Pos = 0xa
	// Bit mask of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x400
	// Bit CC1OF.
	TIM_SR_CC1OF = 0x400
	// No overcapture has been detected
	TIM_SR_CC1OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC1OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC1OF_Clear = 0x0
	// Position of CC2OF field.
	TIM_SR_CC2OF_Pos = 0xb
	// Bit mask of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x800
	// Bit CC2OF.
	TIM_SR_CC2OF = 0x800
	// No overcapture has been detected
	TIM_SR_CC2OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC2OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC2OF_Clear = 0x0
	// Position of CC3OF field.
	TIM_SR_CC3OF_Pos = 0xc
	// Bit mask of CC3OF field.
	TIM_SR_CC3OF_Msk = 0x1000
	// Bit CC3OF.
	TIM_SR_CC3OF = 0x1000
	// No overcapture has been detected
	TIM_SR_CC3OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC3OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC3OF_Clear = 0x0
	// Position of CC4OF field.
	TIM_SR_CC4OF_Pos = 0xd
	// Bit mask of CC4OF field.
	TIM_SR_CC4OF_Msk = 0x2000
	// Bit CC4OF.
	TIM_SR_CC4OF = 0x2000
	// No overcapture has been detected
	TIM_SR_CC4OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC4OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC4OF_Clear = 0x0
	// Position of SBIF field.
	TIM_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM_SR_SBIF = 0x2000
	// No break event occurred
	TIM_SR_SBIF_NoTrigger = 0x0
	// An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_SBIF_Trigger = 0x1
	// Clear flag
	TIM_SR_SBIF_Clear = 0x0
	// Position of CC5IF field.
	TIM_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM_SR_CC5IF = 0x10000
	// No campture/compare has been detected
	TIM_SR_CC5IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC5IF_Match = 0x1
	// Clear flag
	TIM_SR_CC5IF_Clear = 0x0
	// Position of CC6IF field.
	TIM_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM_SR_CC6IF = 0x20000
	// No campture/compare has been detected
	TIM_SR_CC6IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC6IF_Match = 0x1
	// Clear flag
	TIM_SR_CC6IF_Clear = 0x0

	// EGR: event generation register
	// Position of UG field.
	TIM_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM_EGR_UG = 0x1
	// Re-initializes the timer counter and generates an update of the registers.
	TIM_EGR_UG_Update = 0x1
	// Position of CC1G field.
	TIM_EGR_CC1G_Pos = 0x2
	// Bit mask of CC1G field.
	TIM_EGR_CC1G_Msk = 0x4
	// Bit CC1G.
	TIM_EGR_CC1G = 0x4
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC1G_Trigger = 0x1
	// Position of CC2G field.
	TIM_EGR_CC2G_Pos = 0x3
	// Bit mask of CC2G field.
	TIM_EGR_CC2G_Msk = 0x8
	// Bit CC2G.
	TIM_EGR_CC2G = 0x8
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC2G_Trigger = 0x1
	// Position of CC3G field.
	TIM_EGR_CC3G_Pos = 0x4
	// Bit mask of CC3G field.
	TIM_EGR_CC3G_Msk = 0x10
	// Bit CC3G.
	TIM_EGR_CC3G = 0x10
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC3G_Trigger = 0x1
	// Position of CC4G field.
	TIM_EGR_CC4G_Pos = 0x5
	// Bit mask of CC4G field.
	TIM_EGR_CC4G_Msk = 0x20
	// Bit CC4G.
	TIM_EGR_CC4G = 0x20
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC4G_Trigger = 0x1
	// Position of COMG field.
	TIM_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM_EGR_COMG = 0x20
	// When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
	TIM_EGR_COMG_Trigger = 0x1
	// Position of TG field.
	TIM_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM_EGR_TG = 0x40
	// The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
	TIM_EGR_TG_Trigger = 0x1
	// Position of BG field.
	TIM_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM_EGR_BG = 0x80
	// A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
	TIM_EGR_BG_Trigger = 0x1
	// Position of B2G field.
	TIM_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM_EGR_B2G = 0x100
	// A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
	TIM_EGR_B2G_Trigger = 0x1

	// CCMR1_Output: capture/compare mode register 1 (output mode)
	// Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Pos = 0x8
	// Bit mask of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC1S_Output = 0x0
	// Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Pos = 0x10
	// Bit mask of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC2S_Output = 0x0
	// Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Pos = 0xa
	// Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk = 0x400
	// Bit OC1FE.
	TIM_CCMR1_Output_OC1FE = 0x400
	// Fast output disabled
	TIM_CCMR1_Output_OC1FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC1FE_Enabled = 0x1
	// Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Pos = 0x12
	// Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk = 0x40000
	// Bit OC2FE.
	TIM_CCMR1_Output_OC2FE = 0x40000
	// Fast output disabled
	TIM_CCMR1_Output_OC2FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC2FE_Enabled = 0x1
	// Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Pos = 0xb
	// Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk = 0x800
	// Bit OC1PE.
	TIM_CCMR1_Output_OC1PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC1PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC1PE_Enabled = 0x1
	// Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Pos = 0x13
	// Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk = 0x80000
	// Bit OC2PE.
	TIM_CCMR1_Output_OC2PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC2PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC2PE_Enabled = 0x1
	// Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Pos = 0xc
	// Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC1M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC1M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC1M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC1M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC1M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC1M_PwmMode2 = 0x7
	// Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Pos = 0x14
	// Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC2M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC2M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC2M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC2M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC2M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC2M_PwmMode2 = 0x7
	// Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Pos = 0xf
	// Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk = 0x8000
	// Bit OC1CE.
	TIM_CCMR1_Output_OC1CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR1_Output_OC1CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR1_Output_OC1CE_Enabled = 0x1
	// Position of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Pos = 0x17
	// Bit mask of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Msk = 0x800000
	// Bit OC2CE.
	TIM_CCMR1_Output_OC2CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR1_Output_OC2CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR1_Output_OC2CE_Enabled = 0x1
	// Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x18
	// Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x1000000
	// Bit OC1M_3.
	TIM_CCMR1_Output_OC1M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC1M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC1M_3_Extended = 0x1
	// Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Pos = 0x20
	// Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x100000000
	// Bit OC2M_3.
	TIM_CCMR1_Output_OC2M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC2M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC2M_3_Extended = 0x1

	// CCMR1_Input: capture/compare mode register 1 (output mode)
	// Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk = 0x3
	// CC1 channel is configured as input, IC1 is mapped on TI1
	TIM_CCMR1_Input_CC1S_TI1 = 0x1
	// CC1 channel is configured as input, IC1 is mapped on TI2
	TIM_CCMR1_Input_CC1S_TI2 = 0x2
	// CC1 channel is configured as input, IC1 is mapped on TRC
	TIM_CCMR1_Input_CC1S_TRC = 0x3
	// Position of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Pos = 0xa
	// Bit mask of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC1PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC1PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC1PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC1PSC_EightEvents = 0x3
	// Position of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Pos = 0x12
	// Bit mask of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC2PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC2PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC2PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC2PSC_EightEvents = 0x3
	// Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Pos = 0xc
	// Bit mask of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC1F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC1F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC1F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC1F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N8 = 0xf
	// Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Pos = 0x14
	// Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC2F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC2F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC2F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC2F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N8 = 0xf
	// Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk = 0x300
	// CC2 channel is configured as input, IC2 is mapped on TI2
	TIM_CCMR1_Input_CC2S_TI2 = 0x1
	// CC2 channel is configured as input, IC2 is mapped on TI1
	TIM_CCMR1_Input_CC2S_TI1 = 0x2
	// CC2 channel is configured as input, IC2 is mapped on TRC
	TIM_CCMR1_Input_CC2S_TRC = 0x3

	// CCMR2_Output: capture/compare mode register 2 (output mode)
	// Position of CC3S field.
	TIM_CCMR2_Output_CC3S_Pos = 0x8
	// Bit mask of CC3S field.
	TIM_CCMR2_Output_CC3S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC3S_Output = 0x0
	// Position of CC4S field.
	TIM_CCMR2_Output_CC4S_Pos = 0x10
	// Bit mask of CC4S field.
	TIM_CCMR2_Output_CC4S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC4S_Output = 0x0
	// Position of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Pos = 0xa
	// Bit mask of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Msk = 0x400
	// Bit OC3FE.
	TIM_CCMR2_Output_OC3FE = 0x400
	// Fast output disabled
	TIM_CCMR2_Output_OC3FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC3FE_Enabled = 0x1
	// Position of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Pos = 0x12
	// Bit mask of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Msk = 0x40000
	// Bit OC4FE.
	TIM_CCMR2_Output_OC4FE = 0x40000
	// Fast output disabled
	TIM_CCMR2_Output_OC4FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC4FE_Enabled = 0x1
	// Position of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Pos = 0xb
	// Bit mask of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Msk = 0x800
	// Bit OC3PE.
	TIM_CCMR2_Output_OC3PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC3PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC3PE_Enabled = 0x1
	// Position of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Pos = 0x13
	// Bit mask of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Msk = 0x80000
	// Bit OC4PE.
	TIM_CCMR2_Output_OC4PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC4PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC4PE_Enabled = 0x1
	// Position of OC3M field.
	TIM_CCMR2_Output_OC3M_Pos = 0xc
	// Bit mask of OC3M field.
	TIM_CCMR2_Output_OC3M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC3M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC3M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC3M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC3M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC3M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC3M_PwmMode2 = 0x7
	// Position of OC4M field.
	TIM_CCMR2_Output_OC4M_Pos = 0x14
	// Bit mask of OC4M field.
	TIM_CCMR2_Output_OC4M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC4M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC4M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC4M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC4M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC4M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC4M_PwmMode2 = 0x7
	// Position of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Pos = 0xf
	// Bit mask of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Msk = 0x8000
	// Bit OC3CE.
	TIM_CCMR2_Output_OC3CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR2_Output_OC3CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR2_Output_OC3CE_Enabled = 0x1
	// Position of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Pos = 0x17
	// Bit mask of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Msk = 0x800000
	// Bit OC4CE.
	TIM_CCMR2_Output_OC4CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR2_Output_OC4CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR2_Output_OC4CE_Enabled = 0x1
	// Position of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Pos = 0x18
	// Bit mask of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Msk = 0x1000000
	// Bit OC3M_3.
	TIM_CCMR2_Output_OC3M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC3M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC3M_3_Extended = 0x1
	// Position of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Pos = 0x20
	// Bit mask of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Msk = 0x100000000
	// Bit OC4M_3.
	TIM_CCMR2_Output_OC4M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC4M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC4M_3_Extended = 0x1

	// CCMR2_Input: capture/compare mode register 2 (output mode)
	// Position of CC3S field.
	TIM_CCMR2_Input_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM_CCMR2_Input_CC3S_Msk = 0x3
	// CC3 channel is configured as input, IC3 is mapped on TI3
	TIM_CCMR2_Input_CC3S_TI3 = 0x1
	// CC3 channel is configured as input, IC3 is mapped on TI4
	TIM_CCMR2_Input_CC3S_TI4 = 0x2
	// CC3 channel is configured as input, IC3 is mapped on TRC
	TIM_CCMR2_Input_CC3S_TRC = 0x3
	// Position of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Pos = 0xa
	// Bit mask of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC3PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC3PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC3PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC3PSC_EightEvents = 0x3
	// Position of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Pos = 0x12
	// Bit mask of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC4PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC4PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC4PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC4PSC_EightEvents = 0x3
	// Position of IC3F field.
	TIM_CCMR2_Input_IC3F_Pos = 0xc
	// Bit mask of IC3F field.
	TIM_CCMR2_Input_IC3F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC3F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC3F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC3F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC3F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N8 = 0xf
	// Position of IC4F field.
	TIM_CCMR2_Input_IC4F_Pos = 0x14
	// Bit mask of IC4F field.
	TIM_CCMR2_Input_IC4F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC4F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC4F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC4F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC4F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N8 = 0xf
	// Position of CC4S field.
	TIM_CCMR2_Input_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM_CCMR2_Input_CC4S_Msk = 0x300
	// CC4 channel is configured as input, IC4 is mapped on TI4
	TIM_CCMR2_Input_CC4S_TI4 = 0x1
	// CC4 channel is configured as input, IC4 is mapped on TI3
	TIM_CCMR2_Input_CC4S_TI3 = 0x2
	// CC4 channel is configured as input, IC4 is mapped on TRC
	TIM_CCMR2_Input_CC4S_TRC = 0x3

	// CCER: capture/compare enable register
	// Position of CC1E field.
	TIM_CCER_CC1E_Pos = 0x4
	// Bit mask of CC1E field.
	TIM_CCER_CC1E_Msk = 0x10
	// Bit CC1E.
	TIM_CCER_CC1E = 0x10
	// Capture disabled
	TIM_CCER_CC1E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC1E_Enabled = 0x1
	// Position of CC2E field.
	TIM_CCER_CC2E_Pos = 0x8
	// Bit mask of CC2E field.
	TIM_CCER_CC2E_Msk = 0x100
	// Bit CC2E.
	TIM_CCER_CC2E = 0x100
	// Capture disabled
	TIM_CCER_CC2E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC2E_Enabled = 0x1
	// Position of CC3E field.
	TIM_CCER_CC3E_Pos = 0xc
	// Bit mask of CC3E field.
	TIM_CCER_CC3E_Msk = 0x1000
	// Bit CC3E.
	TIM_CCER_CC3E = 0x1000
	// Capture disabled
	TIM_CCER_CC3E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC3E_Enabled = 0x1
	// Position of CC4E field.
	TIM_CCER_CC4E_Pos = 0x10
	// Bit mask of CC4E field.
	TIM_CCER_CC4E_Msk = 0x10000
	// Bit CC4E.
	TIM_CCER_CC4E = 0x10000
	// Capture disabled
	TIM_CCER_CC4E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC4E_Enabled = 0x1
	// Position of CC5E field.
	TIM_CCER_CC5E_Pos = 0x14
	// Bit mask of CC5E field.
	TIM_CCER_CC5E_Msk = 0x100000
	// Bit CC5E.
	TIM_CCER_CC5E = 0x100000
	// Capture disabled
	TIM_CCER_CC5E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC5E_Enabled = 0x1
	// Position of CC6E field.
	TIM_CCER_CC6E_Pos = 0x18
	// Bit mask of CC6E field.
	TIM_CCER_CC6E_Msk = 0x1000000
	// Bit CC6E.
	TIM_CCER_CC6E = 0x1000000
	// Capture disabled
	TIM_CCER_CC6E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC6E_Enabled = 0x1
	// Position of CC1P field.
	TIM_CCER_CC1P_Pos = 0x5
	// Bit mask of CC1P field.
	TIM_CCER_CC1P_Msk = 0x20
	// Bit CC1P.
	TIM_CCER_CC1P = 0x20
	// Noninverted/rising edge
	TIM_CCER_CC1P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC1P_FallingEdge = 0x1
	// Position of CC2P field.
	TIM_CCER_CC2P_Pos = 0x9
	// Bit mask of CC2P field.
	TIM_CCER_CC2P_Msk = 0x200
	// Bit CC2P.
	TIM_CCER_CC2P = 0x200
	// Noninverted/rising edge
	TIM_CCER_CC2P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC2P_FallingEdge = 0x1
	// Position of CC3P field.
	TIM_CCER_CC3P_Pos = 0xd
	// Bit mask of CC3P field.
	TIM_CCER_CC3P_Msk = 0x2000
	// Bit CC3P.
	TIM_CCER_CC3P = 0x2000
	// Noninverted/rising edge
	TIM_CCER_CC3P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC3P_FallingEdge = 0x1
	// Position of CC4P field.
	TIM_CCER_CC4P_Pos = 0x11
	// Bit mask of CC4P field.
	TIM_CCER_CC4P_Msk = 0x20000
	// Bit CC4P.
	TIM_CCER_CC4P = 0x20000
	// Noninverted/rising edge
	TIM_CCER_CC4P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC4P_FallingEdge = 0x1
	// Position of CC5P field.
	TIM_CCER_CC5P_Pos = 0x15
	// Bit mask of CC5P field.
	TIM_CCER_CC5P_Msk = 0x200000
	// Bit CC5P.
	TIM_CCER_CC5P = 0x200000
	// Noninverted/rising edge
	TIM_CCER_CC5P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC5P_FallingEdge = 0x1
	// Position of CC6P field.
	TIM_CCER_CC6P_Pos = 0x19
	// Bit mask of CC6P field.
	TIM_CCER_CC6P_Msk = 0x2000000
	// Bit CC6P.
	TIM_CCER_CC6P = 0x2000000
	// Noninverted/rising edge
	TIM_CCER_CC6P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC6P_FallingEdge = 0x1
	// Position of CC1NE field.
	TIM_CCER_CC1NE_Pos = 0x6
	// Bit mask of CC1NE field.
	TIM_CCER_CC1NE_Msk = 0x40
	// Bit CC1NE.
	TIM_CCER_CC1NE = 0x40
	// Complementary output disabled
	TIM_CCER_CC1NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC1NE_Enabled = 0x1
	// Position of CC2NE field.
	TIM_CCER_CC2NE_Pos = 0xa
	// Bit mask of CC2NE field.
	TIM_CCER_CC2NE_Msk = 0x400
	// Bit CC2NE.
	TIM_CCER_CC2NE = 0x400
	// Complementary output disabled
	TIM_CCER_CC2NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC2NE_Enabled = 0x1
	// Position of CC3NE field.
	TIM_CCER_CC3NE_Pos = 0xe
	// Bit mask of CC3NE field.
	TIM_CCER_CC3NE_Msk = 0x4000
	// Bit CC3NE.
	TIM_CCER_CC3NE = 0x4000
	// Complementary output disabled
	TIM_CCER_CC3NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC3NE_Enabled = 0x1
	// Position of CC1NP field.
	TIM_CCER_CC1NP_Pos = 0x7
	// Bit mask of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x80
	// Bit CC1NP.
	TIM_CCER_CC1NP = 0x80
	// OCxN active high
	TIM_CCER_CC1NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC1NP_ActiveLow = 0x1
	// Position of CC2NP field.
	TIM_CCER_CC2NP_Pos = 0xb
	// Bit mask of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x800
	// Bit CC2NP.
	TIM_CCER_CC2NP = 0x800
	// OCxN active high
	TIM_CCER_CC2NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC2NP_ActiveLow = 0x1
	// Position of CC3NP field.
	TIM_CCER_CC3NP_Pos = 0xf
	// Bit mask of CC3NP field.
	TIM_CCER_CC3NP_Msk = 0x8000
	// Bit CC3NP.
	TIM_CCER_CC3NP = 0x8000
	// OCxN active high
	TIM_CCER_CC3NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC3NP_ActiveLow = 0x1
	// Position of CC4NP field.
	TIM_CCER_CC4NP_Pos = 0x13
	// Bit mask of CC4NP field.
	TIM_CCER_CC4NP_Msk = 0x80000
	// Bit CC4NP.
	TIM_CCER_CC4NP = 0x80000
	// OCxN active high
	TIM_CCER_CC4NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC4NP_ActiveLow = 0x1

	// CNT: counter
	// Position of CNT field.
	TIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM_CNT_UIFCPY = 0x80000000

	// CNT16: 16-bit counter register
	// Position of CNT field.
	TIM_CNT16_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT16_CNT_Msk = 0xffff

	// PSC: prescaler
	// Position of PSC field.
	TIM_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM_PSC_PSC_Msk = 0xffff

	// ARR: auto-reload register
	// Position of ARR field.
	TIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM_ARR_ARR_Msk = 0xffff

	// RCR: repetition counter register
	// Position of REP field.
	TIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM_RCR_REP_Msk = 0xffff

	// CCR1: capture/compare register
	// Position of CCR field.
	TIM_CCR_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR_CCR_Msk = 0xffff

	// BDTR: break and dead-time register
	// Position of DTG field.
	TIM_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM_BDTR_DTG_Msk = 0xff
	// Position of LOCK field.
	TIM_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM_BDTR_LOCK_Msk = 0x300
	// No bit is write protected
	TIM_BDTR_LOCK_Off = 0x0
	// Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
	TIM_BDTR_LOCK_Level1 = 0x1
	// LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
	TIM_BDTR_LOCK_Level2 = 0x2
	// LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
	TIM_BDTR_LOCK_Level3 = 0x3
	// Position of OSSI field.
	TIM_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM_BDTR_OSSI = 0x400
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSI_HiZ = 0x0
	// When inactive, OC/OCN outputs are forced to idle level
	TIM_BDTR_OSSI_IdleLevel = 0x1
	// Position of OSSR field.
	TIM_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM_BDTR_OSSR = 0x800
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSR_HiZ = 0x0
	// When inactive, OC/OCN outputs are enabled with their inactive level
	TIM_BDTR_OSSR_IdleLevel = 0x1
	// Position of BKE field.
	TIM_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM_BDTR_BKE = 0x1000
	// Break function x disabled
	TIM_BDTR_BKE_Disabled = 0x0
	// Break function x enabled
	TIM_BDTR_BKE_Enabled = 0x1
	// Position of BKP field.
	TIM_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM_BDTR_BKP = 0x2000
	// Break input BRKx is active low
	TIM_BDTR_BKP_ActiveLow = 0x0
	// Break input BRKx is active high
	TIM_BDTR_BKP_ActiveHigh = 0x1
	// Position of AOE field.
	TIM_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM_BDTR_AOE = 0x4000
	// MOE can be set only by software
	TIM_BDTR_AOE_Manual = 0x0
	// MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
	TIM_BDTR_AOE_Automatic = 0x1
	// Position of MOE field.
	TIM_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM_BDTR_MOE = 0x8000
	// OC/OCN are disabled or forced idle depending on OSSI
	TIM_BDTR_MOE_DisabledIdle = 0x0
	// OC/OCN are enabled if CCxE/CCxNE are set
	TIM_BDTR_MOE_Enabled = 0x1
	// Position of BKF field.
	TIM_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM_BDTR_BK2E = 0x1000000
	// Break function x disabled
	TIM_BDTR_BK2E_Disabled = 0x0
	// Break function x enabled
	TIM_BDTR_BK2E_Enabled = 0x1
	// Position of BK2P field.
	TIM_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM_BDTR_BK2P = 0x2000000
	// Break input BRKx is active low
	TIM_BDTR_BK2P_ActiveLow = 0x0
	// Break input BRKx is active high
	TIM_BDTR_BK2P_ActiveHigh = 0x1
	// Position of BKDSRM field.
	TIM_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM_BDTR_BK2BID = 0x20000000

	// DCR: DMA control register
	// Position of DBA field.
	TIM_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00

	// DMAR: DMA address for full transfer
	// Position of DMAB field.
	TIM_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffffffff

	// CCMR3_Output: capture/compare mode register 2 (output mode)
	// Position of OC5M_3 field.
	TIM_CCMR3_Output_OC5M_3_Pos = 0x18
	// Bit mask of OC5M_3 field.
	TIM_CCMR3_Output_OC5M_3_Msk = 0x1000000
	// Bit OC5M_3.
	TIM_CCMR3_Output_OC5M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR3_Output_OC5M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR3_Output_OC5M_3_Extended = 0x1
	// Position of OC6M_3 field.
	TIM_CCMR3_Output_OC6M_3_Pos = 0x20
	// Bit mask of OC6M_3 field.
	TIM_CCMR3_Output_OC6M_3_Msk = 0x100000000
	// Bit OC6M_3.
	TIM_CCMR3_Output_OC6M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR3_Output_OC6M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR3_Output_OC6M_3_Extended = 0x1
	// Position of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Pos = 0xf
	// Bit mask of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Msk = 0x8000
	// Bit OC5CE.
	TIM_CCMR3_Output_OC5CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR3_Output_OC5CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR3_Output_OC5CE_Enabled = 0x1
	// Position of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Pos = 0x17
	// Bit mask of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Msk = 0x800000
	// Bit OC6CE.
	TIM_CCMR3_Output_OC6CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR3_Output_OC6CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR3_Output_OC6CE_Enabled = 0x1
	// Position of OC5M field.
	TIM_CCMR3_Output_OC5M_Pos = 0xc
	// Bit mask of OC5M field.
	TIM_CCMR3_Output_OC5M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR3_Output_OC5M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR3_Output_OC5M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR3_Output_OC5M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR3_Output_OC5M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR3_Output_OC5M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR3_Output_OC5M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR3_Output_OC5M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR3_Output_OC5M_PwmMode2 = 0x7
	// Position of OC6M field.
	TIM_CCMR3_Output_OC6M_Pos = 0x14
	// Bit mask of OC6M field.
	TIM_CCMR3_Output_OC6M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR3_Output_OC6M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR3_Output_OC6M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR3_Output_OC6M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR3_Output_OC6M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR3_Output_OC6M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR3_Output_OC6M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR3_Output_OC6M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR3_Output_OC6M_PwmMode2 = 0x7
	// Position of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Pos = 0xb
	// Bit mask of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Msk = 0x800
	// Bit OC5PE.
	TIM_CCMR3_Output_OC5PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR3_Output_OC5PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR3_Output_OC5PE_Enabled = 0x1
	// Position of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Pos = 0x13
	// Bit mask of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Msk = 0x80000
	// Bit OC6PE.
	TIM_CCMR3_Output_OC6PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR3_Output_OC6PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR3_Output_OC6PE_Enabled = 0x1
	// Position of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Pos = 0xa
	// Bit mask of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Msk = 0x400
	// Bit OC5FE.
	TIM_CCMR3_Output_OC5FE = 0x400
	// Fast output disabled
	TIM_CCMR3_Output_OC5FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR3_Output_OC5FE_Enabled = 0x1
	// Position of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Pos = 0x12
	// Bit mask of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Msk = 0x40000
	// Bit OC6FE.
	TIM_CCMR3_Output_OC6FE = 0x40000
	// Fast output disabled
	TIM_CCMR3_Output_OC6FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR3_Output_OC6FE_Enabled = 0x1

	// CCR5: capture/compare register
	// Position of CCR field.
	TIM_CCR5_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR5_CCR_Msk = 0xffff
	// Position of GC5C1 field.
	TIM_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM_CCR5_GC5C3 = 0x80000000

	// CCR6: capture/compare register
	// Position of CCR field.
	TIM_CCR6_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR6_CCR_Msk = 0xffff

	// AF1: TIM1 alternate function option register 1
	// Position of BKINE field.
	TIM_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIM_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIM_AF1_BKINE = 0x1
	// Position of BKINP field.
	TIM_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIM_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIM_AF1_BKINP = 0x200
	// Position of ETRSEL field.
	TIM_AF1_ETRSEL_Pos = 0xe
	// Bit mask of ETRSEL field.
	TIM_AF1_ETRSEL_Msk = 0x3c000

	// AF2: TIM1 alternate function option register 2
	// Position of BK2INE field.
	TIM_AF2_BK2INE_Pos = 0x0
	// Bit mask of BK2INE field.
	TIM_AF2_BK2INE_Msk = 0x1
	// Bit BK2INE.
	TIM_AF2_BK2INE = 0x1
	// Position of BK2INP field.
	TIM_AF2_BK2INP_Pos = 0x9
	// Bit mask of BK2INP field.
	TIM_AF2_BK2INP_Msk = 0x200
	// Bit BK2INP.
	TIM_AF2_BK2INP = 0x200

	// TISEL: TIM1 timer input selection register
	// Position of TI1SEL field.
	TIM_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIM_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM_TISEL_TI2SEL_Msk = 0xf00
	// Position of TI3SEL field.
	TIM_TISEL_TI3SEL_Pos = 0x10
	// Bit mask of TI3SEL field.
	TIM_TISEL_TI3SEL_Msk = 0xf0000
	// Position of TI4SEL field.
	TIM_TISEL_TI4SEL_Pos = 0x18
	// Bit mask of TI4SEL field.
	TIM_TISEL_TI4SEL_Msk = 0xf000000
)

// Constants for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	// Position of UE field.
	USART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	USART_CR1_UE_Msk = 0x1
	// Bit UE.
	USART_CR1_UE = 0x1
	// UART is disabled
	USART_CR1_UE_Disabled = 0x0
	// UART is enabled
	USART_CR1_UE_Enabled = 0x1
	// Position of UESM field.
	USART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	USART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	USART_CR1_UESM = 0x2
	// USART not able to wake up the MCU from Stop mode
	USART_CR1_UESM_Disabled = 0x0
	// USART able to wake up the MCU from Stop mode
	USART_CR1_UESM_Enabled = 0x1
	// Position of RE field.
	USART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	USART_CR1_RE_Msk = 0x4
	// Bit RE.
	USART_CR1_RE = 0x4
	// Receiver is disabled
	USART_CR1_RE_Disabled = 0x0
	// Receiver is enabled
	USART_CR1_RE_Enabled = 0x1
	// Position of TE field.
	USART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	USART_CR1_TE_Msk = 0x8
	// Bit TE.
	USART_CR1_TE = 0x8
	// Transmitter is disabled
	USART_CR1_TE_Disabled = 0x0
	// Transmitter is enabled
	USART_CR1_TE_Enabled = 0x1
	// Position of IDLEIE field.
	USART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	USART_CR1_IDLEIE = 0x10
	// Interrupt is disabled
	USART_CR1_IDLEIE_Disabled = 0x0
	// Interrupt is generated whenever IDLE=1 in the ISR register
	USART_CR1_IDLEIE_Enabled = 0x1
	// Position of RXNEIE field.
	USART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	USART_CR1_RXNEIE = 0x20
	// Interrupt is disabled
	USART_CR1_RXNEIE_Disabled = 0x0
	// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
	USART_CR1_RXNEIE_Enabled = 0x1
	// Position of TCIE field.
	USART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	USART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	USART_CR1_TCIE = 0x40
	// Interrupt is disabled
	USART_CR1_TCIE_Disabled = 0x0
	// Interrupt is generated whenever TC=1 in the ISR register
	USART_CR1_TCIE_Enabled = 0x1
	// Position of TXEIE field.
	USART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	USART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	USART_CR1_TXEIE = 0x80
	// Interrupt is disabled
	USART_CR1_TXEIE_Disabled = 0x0
	// Interrupt is generated whenever TXE=1 in the ISR register
	USART_CR1_TXEIE_Enabled = 0x1
	// Position of PEIE field.
	USART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	USART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	USART_CR1_PEIE = 0x100
	// Interrupt is disabled
	USART_CR1_PEIE_Disabled = 0x0
	// Interrupt is generated whenever PE=1 in the ISR register
	USART_CR1_PEIE_Enabled = 0x1
	// Position of PS field.
	USART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	USART_CR1_PS_Msk = 0x200
	// Bit PS.
	USART_CR1_PS = 0x200
	// Even parity
	USART_CR1_PS_Even = 0x0
	// Odd parity
	USART_CR1_PS_Odd = 0x1
	// Position of PCE field.
	USART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	USART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	USART_CR1_PCE = 0x400
	// Parity control disabled
	USART_CR1_PCE_Disabled = 0x0
	// Parity control enabled
	USART_CR1_PCE_Enabled = 0x1
	// Position of WAKE field.
	USART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	USART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	USART_CR1_WAKE = 0x800
	// Idle line
	USART_CR1_WAKE_Idle = 0x0
	// Address mask
	USART_CR1_WAKE_Address = 0x1
	// Position of M0 field.
	USART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	USART_CR1_M0_Msk = 0x1000
	// Bit M0.
	USART_CR1_M0 = 0x1000
	// 1 start bit, 8 data bits, n stop bits
	USART_CR1_M0_Bit8 = 0x0
	// 1 start bit, 9 data bits, n stop bits
	USART_CR1_M0_Bit9 = 0x1
	// Position of MME field.
	USART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	USART_CR1_MME_Msk = 0x2000
	// Bit MME.
	USART_CR1_MME = 0x2000
	// Receiver in active mode permanently
	USART_CR1_MME_Disabled = 0x0
	// Receiver can switch between mute mode and active mode
	USART_CR1_MME_Enabled = 0x1
	// Position of CMIE field.
	USART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	USART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	USART_CR1_CMIE = 0x4000
	// Interrupt is disabled
	USART_CR1_CMIE_Disabled = 0x0
	// Interrupt is generated when the CMF bit is set in the ISR register
	USART_CR1_CMIE_Enabled = 0x1
	// Position of OVER8 field.
	USART_CR1_OVER8_Pos = 0xf
	// Bit mask of OVER8 field.
	USART_CR1_OVER8_Msk = 0x8000
	// Bit OVER8.
	USART_CR1_OVER8 = 0x8000
	// Oversampling by 16
	USART_CR1_OVER8_Oversampling16 = 0x0
	// Oversampling by 8
	USART_CR1_OVER8_Oversampling8 = 0x1
	// Position of DEDT field.
	USART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	USART_CR1_DEDT_Msk = 0x1f0000
	// Position of DEAT field.
	USART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	USART_CR1_DEAT_Msk = 0x3e00000
	// Position of RTOIE field.
	USART_CR1_RTOIE_Pos = 0x1a
	// Bit mask of RTOIE field.
	USART_CR1_RTOIE_Msk = 0x4000000
	// Bit RTOIE.
	USART_CR1_RTOIE = 0x4000000
	// Interrupt is inhibited
	USART_CR1_RTOIE_Disabled = 0x0
	// An USART interrupt is generated when the RTOF bit is set in the ISR register
	USART_CR1_RTOIE_Enabled = 0x1
	// Position of EOBIE field.
	USART_CR1_EOBIE_Pos = 0x1b
	// Bit mask of EOBIE field.
	USART_CR1_EOBIE_Msk = 0x8000000
	// Bit EOBIE.
	USART_CR1_EOBIE = 0x8000000
	// Interrupt is inhibited
	USART_CR1_EOBIE_Disabled = 0x0
	// A USART interrupt is generated when the EOBF flag is set in the ISR register
	USART_CR1_EOBIE_Enabled = 0x1
	// Position of M1 field.
	USART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	USART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	USART_CR1_M1 = 0x10000000
	// Use M0 to set the data bits
	USART_CR1_M1_M0 = 0x0
	// 1 start bit, 7 data bits, n stop bits
	USART_CR1_M1_Bit7 = 0x1
	// Position of FIFOEN field.
	USART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	USART_CR1_FIFOEN = 0x20000000
	// FIFO mode is disabled
	USART_CR1_FIFOEN_Disabled = 0x0
	// FIFO mode is enabled
	USART_CR1_FIFOEN_Enabled = 0x1
	// Position of TXFEIE field.
	USART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	USART_CR1_TXFEIE = 0x40000000
	// Interrupt inhibited
	USART_CR1_TXFEIE_Disabled = 0x0
	// USART interrupt generated when TXFE = 1 in the USART_ISR register
	USART_CR1_TXFEIE_Enabled = 0x1
	// Position of RXFFIE field.
	USART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	USART_CR1_RXFFIE = 0x80000000
	// Interrupt inhibited
	USART_CR1_RXFFIE_Disabled = 0x0
	// USART interrupt generated when RXFF = 1 in the USART_ISR register
	USART_CR1_RXFFIE_Enabled = 0x1

	// CR2: Control register 2
	// Position of SLVEN field.
	USART_CR2_SLVEN_Pos = 0x0
	// Bit mask of SLVEN field.
	USART_CR2_SLVEN_Msk = 0x1
	// Bit SLVEN.
	USART_CR2_SLVEN = 0x1
	// Slave mode disabled
	USART_CR2_SLVEN_Disabled = 0x0
	// Slave mode enabled
	USART_CR2_SLVEN_Enabled = 0x1
	// Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Pos = 0x3
	// Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk = 0x8
	// Bit DIS_NSS.
	USART_CR2_DIS_NSS = 0x8
	// SPI slave selection depends on NSS input pin
	USART_CR2_DIS_NSS_Disabled = 0x0
	// SPI slave is always selected and NSS input pin is ignored
	USART_CR2_DIS_NSS_Enabled = 0x1
	// Position of ADDM7 field.
	USART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	USART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	USART_CR2_ADDM7 = 0x10
	// 4-bit address detection
	USART_CR2_ADDM7_Bit4 = 0x0
	// 7-bit address detection
	USART_CR2_ADDM7_Bit7 = 0x1
	// Position of LBDL field.
	USART_CR2_LBDL_Pos = 0x5
	// Bit mask of LBDL field.
	USART_CR2_LBDL_Msk = 0x20
	// Bit LBDL.
	USART_CR2_LBDL = 0x20
	// 10-bit break detection
	USART_CR2_LBDL_Bit10 = 0x0
	// 11-bit break detection
	USART_CR2_LBDL_Bit11 = 0x1
	// Position of LBDIE field.
	USART_CR2_LBDIE_Pos = 0x6
	// Bit mask of LBDIE field.
	USART_CR2_LBDIE_Msk = 0x40
	// Bit LBDIE.
	USART_CR2_LBDIE = 0x40
	// Interrupt is inhibited
	USART_CR2_LBDIE_Disabled = 0x0
	// An interrupt is generated whenever LBDF=1 in the ISR register
	USART_CR2_LBDIE_Enabled = 0x1
	// Position of LBCL field.
	USART_CR2_LBCL_Pos = 0x8
	// Bit mask of LBCL field.
	USART_CR2_LBCL_Msk = 0x100
	// Bit LBCL.
	USART_CR2_LBCL = 0x100
	// The clock pulse of the last data bit is not output to the CK pin
	USART_CR2_LBCL_NotOutput = 0x0
	// The clock pulse of the last data bit is output to the CK pin
	USART_CR2_LBCL_Output = 0x1
	// Position of CPHA field.
	USART_CR2_CPHA_Pos = 0x9
	// Bit mask of CPHA field.
	USART_CR2_CPHA_Msk = 0x200
	// Bit CPHA.
	USART_CR2_CPHA = 0x200
	// The first clock transition is the first data capture edge
	USART_CR2_CPHA_First = 0x0
	// The second clock transition is the first data capture edge
	USART_CR2_CPHA_Second = 0x1
	// Position of CPOL field.
	USART_CR2_CPOL_Pos = 0xa
	// Bit mask of CPOL field.
	USART_CR2_CPOL_Msk = 0x400
	// Bit CPOL.
	USART_CR2_CPOL = 0x400
	// Steady low value on CK pin outside transmission window
	USART_CR2_CPOL_Low = 0x0
	// Steady high value on CK pin outside transmission window
	USART_CR2_CPOL_High = 0x1
	// Position of CLKEN field.
	USART_CR2_CLKEN_Pos = 0xb
	// Bit mask of CLKEN field.
	USART_CR2_CLKEN_Msk = 0x800
	// Bit CLKEN.
	USART_CR2_CLKEN = 0x800
	// CK pin disabled
	USART_CR2_CLKEN_Disabled = 0x0
	// CK pin enabled
	USART_CR2_CLKEN_Enabled = 0x1
	// Position of STOP field.
	USART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	USART_CR2_STOP_Msk = 0x3000
	// 1 stop bit
	USART_CR2_STOP_Stop1 = 0x0
	// 0.5 stop bit
	USART_CR2_STOP_Stop0p5 = 0x1
	// 2 stop bit
	USART_CR2_STOP_Stop2 = 0x2
	// 1.5 stop bit
	USART_CR2_STOP_Stop1p5 = 0x3
	// Position of LINEN field.
	USART_CR2_LINEN_Pos = 0xe
	// Bit mask of LINEN field.
	USART_CR2_LINEN_Msk = 0x4000
	// Bit LINEN.
	USART_CR2_LINEN = 0x4000
	// LIN mode disabled
	USART_CR2_LINEN_Disabled = 0x0
	// LIN mode enabled
	USART_CR2_LINEN_Enabled = 0x1
	// Position of SWAP field.
	USART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	USART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	USART_CR2_SWAP = 0x8000
	// TX/RX pins are used as defined in standard pinout
	USART_CR2_SWAP_Standard = 0x0
	// The TX and RX pins functions are swapped
	USART_CR2_SWAP_Swapped = 0x1
	// Position of RXINV field.
	USART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	USART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	USART_CR2_RXINV = 0x10000
	// RX pin signal works using the standard logic levels
	USART_CR2_RXINV_Standard = 0x0
	// RX pin signal values are inverted
	USART_CR2_RXINV_Inverted = 0x1
	// Position of TXINV field.
	USART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	USART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	USART_CR2_TXINV = 0x20000
	// TX pin signal works using the standard logic levels
	USART_CR2_TXINV_Standard = 0x0
	// TX pin signal values are inverted
	USART_CR2_TXINV_Inverted = 0x1
	// Position of DATAINV field.
	USART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	USART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	USART_CR2_DATAINV = 0x40000
	// Logical data from the data register are send/received in positive/direct logic
	USART_CR2_DATAINV_Positive = 0x0
	// Logical data from the data register are send/received in negative/inverse logic
	USART_CR2_DATAINV_Negative = 0x1
	// Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	USART_CR2_MSBFIRST = 0x80000
	// data is transmitted/received with data bit 0 first, following the start bit
	USART_CR2_MSBFIRST_LSB = 0x0
	// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
	USART_CR2_MSBFIRST_MSB = 0x1
	// Position of ABREN field.
	USART_CR2_ABREN_Pos = 0x14
	// Bit mask of ABREN field.
	USART_CR2_ABREN_Msk = 0x100000
	// Bit ABREN.
	USART_CR2_ABREN = 0x100000
	// Auto baud rate detection is disabled
	USART_CR2_ABREN_Disabled = 0x0
	// Auto baud rate detection is enabled
	USART_CR2_ABREN_Enabled = 0x1
	// Position of ABRMOD field.
	USART_CR2_ABRMOD_Pos = 0x15
	// Bit mask of ABRMOD field.
	USART_CR2_ABRMOD_Msk = 0x600000
	// Measurement of the start bit is used to detect the baud rate
	USART_CR2_ABRMOD_Start = 0x0
	// Falling edge to falling edge measurement
	USART_CR2_ABRMOD_Edge = 0x1
	// 0x7F frame detection
	USART_CR2_ABRMOD_Frame7F = 0x2
	// 0x55 frame detection
	USART_CR2_ABRMOD_Frame55 = 0x3
	// Position of RTOEN field.
	USART_CR2_RTOEN_Pos = 0x17
	// Bit mask of RTOEN field.
	USART_CR2_RTOEN_Msk = 0x800000
	// Bit RTOEN.
	USART_CR2_RTOEN = 0x800000
	// Receiver timeout feature disabled
	USART_CR2_RTOEN_Disabled = 0x0
	// Receiver timeout feature enabled
	USART_CR2_RTOEN_Enabled = 0x1
	// Position of ADD field.
	USART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	USART_CR2_ADD_Msk = 0xff000000

	// CR3: Control register 3
	// Position of EIE field.
	USART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	USART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	USART_CR3_EIE = 0x1
	// Interrupt is inhibited
	USART_CR3_EIE_Disabled = 0x0
	// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
	USART_CR3_EIE_Enabled = 0x1
	// Position of IREN field.
	USART_CR3_IREN_Pos = 0x1
	// Bit mask of IREN field.
	USART_CR3_IREN_Msk = 0x2
	// Bit IREN.
	USART_CR3_IREN = 0x2
	// IrDA disabled
	USART_CR3_IREN_Disabled = 0x0
	// IrDA enabled
	USART_CR3_IREN_Enabled = 0x1
	// Position of IRLP field.
	USART_CR3_IRLP_Pos = 0x2
	// Bit mask of IRLP field.
	USART_CR3_IRLP_Msk = 0x4
	// Bit IRLP.
	USART_CR3_IRLP = 0x4
	// Normal mode
	USART_CR3_IRLP_Normal = 0x0
	// Low-power mode
	USART_CR3_IRLP_LowPower = 0x1
	// Position of HDSEL field.
	USART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	USART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	USART_CR3_HDSEL = 0x8
	// Half duplex mode is not selected
	USART_CR3_HDSEL_NotSelected = 0x0
	// Half duplex mode is selected
	USART_CR3_HDSEL_Selected = 0x1
	// Position of NACK field.
	USART_CR3_NACK_Pos = 0x4
	// Bit mask of NACK field.
	USART_CR3_NACK_Msk = 0x10
	// Bit NACK.
	USART_CR3_NACK = 0x10
	// NACK transmission in case of parity error is disabled
	USART_CR3_NACK_Disabled = 0x0
	// NACK transmission during parity error is enabled
	USART_CR3_NACK_Enabled = 0x1
	// Position of SCEN field.
	USART_CR3_SCEN_Pos = 0x5
	// Bit mask of SCEN field.
	USART_CR3_SCEN_Msk = 0x20
	// Bit SCEN.
	USART_CR3_SCEN = 0x20
	// Smartcard Mode disabled
	USART_CR3_SCEN_Disabled = 0x0
	// Smartcard Mode enabled
	USART_CR3_SCEN_Enabled = 0x1
	// Position of DMAR field.
	USART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	USART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	USART_CR3_DMAR = 0x40
	// DMA mode is disabled for reception
	USART_CR3_DMAR_Disabled = 0x0
	// DMA mode is enabled for reception
	USART_CR3_DMAR_Enabled = 0x1
	// Position of DMAT field.
	USART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	USART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	USART_CR3_DMAT = 0x80
	// DMA mode is disabled for transmission
	USART_CR3_DMAT_Disabled = 0x0
	// DMA mode is enabled for transmission
	USART_CR3_DMAT_Enabled = 0x1
	// Position of RTSE field.
	USART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	USART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	USART_CR3_RTSE = 0x100
	// RTS hardware flow control disabled
	USART_CR3_RTSE_Disabled = 0x0
	// RTS output enabled, data is only requested when there is space in the receive buffer
	USART_CR3_RTSE_Enabled = 0x1
	// Position of CTSE field.
	USART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	USART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	USART_CR3_CTSE = 0x200
	// CTS hardware flow control disabled
	USART_CR3_CTSE_Disabled = 0x0
	// CTS mode enabled, data is only transmitted when the CTS input is asserted
	USART_CR3_CTSE_Enabled = 0x1
	// Position of CTSIE field.
	USART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	USART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	USART_CR3_CTSIE = 0x400
	// Interrupt is inhibited
	USART_CR3_CTSIE_Disabled = 0x0
	// An interrupt is generated whenever CTSIF=1 in the ISR register
	USART_CR3_CTSIE_Enabled = 0x1
	// Position of ONEBIT field.
	USART_CR3_ONEBIT_Pos = 0xb
	// Bit mask of ONEBIT field.
	USART_CR3_ONEBIT_Msk = 0x800
	// Bit ONEBIT.
	USART_CR3_ONEBIT = 0x800
	// Three sample bit method
	USART_CR3_ONEBIT_Sample3 = 0x0
	// One sample bit method
	USART_CR3_ONEBIT_Sample1 = 0x1
	// Position of OVRDIS field.
	USART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	USART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	USART_CR3_OVRDIS = 0x1000
	// Overrun Error Flag, ORE, is set when received data is not read before receiving new data
	USART_CR3_OVRDIS_Enabled = 0x0
	// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
	USART_CR3_OVRDIS_Disabled = 0x1
	// Position of DDRE field.
	USART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	USART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	USART_CR3_DDRE = 0x2000
	// DMA is not disabled in case of reception error
	USART_CR3_DDRE_NotDisabled = 0x0
	// DMA is disabled following a reception error
	USART_CR3_DDRE_Disabled = 0x1
	// Position of DEM field.
	USART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	USART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	USART_CR3_DEM = 0x4000
	// DE function is disabled
	USART_CR3_DEM_Disabled = 0x0
	// The DE signal is output on the RTS pin
	USART_CR3_DEM_Enabled = 0x1
	// Position of DEP field.
	USART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	USART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	USART_CR3_DEP = 0x8000
	// DE signal is active high
	USART_CR3_DEP_High = 0x0
	// DE signal is active low
	USART_CR3_DEP_Low = 0x1
	// Position of SCARCNT field.
	USART_CR3_SCARCNT_Pos = 0x11
	// Bit mask of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000
	// Position of WUS field.
	USART_CR3_WUS_Pos = 0x14
	// Bit mask of WUS field.
	USART_CR3_WUS_Msk = 0x300000
	// WUF active on address match
	USART_CR3_WUS_Address = 0x0
	// WuF active on Start bit detection
	USART_CR3_WUS_Start = 0x2
	// WUF active on RXNE
	USART_CR3_WUS_RXNE = 0x3
	// Position of WUFIE field.
	USART_CR3_WUFIE_Pos = 0x16
	// Bit mask of WUFIE field.
	USART_CR3_WUFIE_Msk = 0x400000
	// Bit WUFIE.
	USART_CR3_WUFIE = 0x400000
	// Interrupt is inhibited
	USART_CR3_WUFIE_Disabled = 0x0
	// An USART interrupt is generated whenever WUF=1 in the ISR register
	USART_CR3_WUFIE_Enabled = 0x1
	// Position of TXFTIE field.
	USART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	USART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	USART_CR3_TXFTIE = 0x800000
	// Interrupt inhibited
	USART_CR3_TXFTIE_Disabled = 0x0
	// USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
	USART_CR3_TXFTIE_Enabled = 0x1
	// Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Pos = 0x18
	// Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000
	// Bit TCBGTIE.
	USART_CR3_TCBGTIE = 0x1000000
	// Interrupt inhibited
	USART_CR3_TCBGTIE_Disabled = 0x0
	// USART interrupt generated whenever TCBGT=1 in the USART_ISR register
	USART_CR3_TCBGTIE_Enabled = 0x1
	// Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000
	// RXFIFO reaches 1/8 of its depth
	USART_CR3_RXFTCFG_Depth_1_8 = 0x0
	// RXFIFO reaches 1/4 of its depth
	USART_CR3_RXFTCFG_Depth_1_4 = 0x1
	// RXFIFO reaches 1/2 of its depth
	USART_CR3_RXFTCFG_Depth_1_2 = 0x2
	// RXFIFO reaches 3/4 of its depth
	USART_CR3_RXFTCFG_Depth_3_4 = 0x3
	// RXFIFO reaches 7/8 of its depth
	USART_CR3_RXFTCFG_Depth_7_8 = 0x4
	// RXFIFO becomes full
	USART_CR3_RXFTCFG_Full = 0x5
	// Position of RXFTIE field.
	USART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	USART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	USART_CR3_RXFTIE = 0x10000000
	// Interrupt inhibited
	USART_CR3_RXFTIE_Disabled = 0x0
	// USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
	USART_CR3_RXFTIE_Enabled = 0x1
	// Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000
	// TXFIFO reaches 1/8 of its depth
	USART_CR3_TXFTCFG_Depth_1_8 = 0x0
	// TXFIFO reaches 1/4 of its depth
	USART_CR3_TXFTCFG_Depth_1_4 = 0x1
	// TXFIFO reaches 1/2 of its depth
	USART_CR3_TXFTCFG_Depth_1_2 = 0x2
	// TXFIFO reaches 3/4 of its depth
	USART_CR3_TXFTCFG_Depth_3_4 = 0x3
	// TXFIFO reaches 7/8 of its depth
	USART_CR3_TXFTCFG_Depth_7_8 = 0x4
	// TXFIFO becomes empty
	USART_CR3_TXFTCFG_Empty = 0x5

	// BRR: Baud rate register
	// Position of BRR field.
	USART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	USART_BRR_BRR_Msk = 0xffff

	// GTPR: Guard time and prescaler register
	// Position of PSC field.
	USART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	USART_GTPR_PSC_Msk = 0xff
	// Position of GT field.
	USART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	USART_GTPR_GT_Msk = 0xff00

	// RTOR: Receiver timeout register
	// Position of RTO field.
	USART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	USART_RTOR_RTO_Msk = 0xffffff
	// Position of BLEN field.
	USART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000

	// RQR: Request register
	// Position of ABRRQ field.
	USART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	USART_RQR_ABRRQ = 0x1
	// resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
	USART_RQR_ABRRQ_Request = 0x1
	// Position of SBKRQ field.
	USART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	USART_RQR_SBKRQ = 0x2
	// sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
	USART_RQR_SBKRQ_Break = 0x1
	// Position of MMRQ field.
	USART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	USART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	USART_RQR_MMRQ = 0x4
	// Puts the USART in mute mode and sets the RWU flag
	USART_RQR_MMRQ_Mute = 0x1
	// Position of RXFRQ field.
	USART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	USART_RQR_RXFRQ = 0x8
	// clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
	USART_RQR_RXFRQ_Discard = 0x1
	// Position of TXFRQ field.
	USART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	USART_RQR_TXFRQ = 0x10
	// Set the TXE flags. This allows to discard the transmit data
	USART_RQR_TXFRQ_Discard = 0x1

	// ISR: Interrupt & status register
	// Position of PE field.
	USART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	USART_ISR_PE_Msk = 0x1
	// Bit PE.
	USART_ISR_PE = 0x1
	// No parity error
	USART_ISR_PE_NoError = 0x0
	// Parity error
	USART_ISR_PE_Error = 0x1
	// Position of FE field.
	USART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	USART_ISR_FE_Msk = 0x2
	// Bit FE.
	USART_ISR_FE = 0x2
	// No Framing error is detected
	USART_ISR_FE_NoError = 0x0
	// Framing error or break character is detected
	USART_ISR_FE_Error = 0x1
	// Position of NE field.
	USART_ISR_NE_Pos = 0x2
	// Bit mask of NE field.
	USART_ISR_NE_Msk = 0x4
	// Bit NE.
	USART_ISR_NE = 0x4
	// No noise is detected
	USART_ISR_NE_NoNoise = 0x0
	// Noise is detected
	USART_ISR_NE_Noise = 0x1
	// Position of ORE field.
	USART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	USART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	USART_ISR_ORE = 0x8
	// No Overrun error
	USART_ISR_ORE_NoOverrun = 0x0
	// Overrun error is detected
	USART_ISR_ORE_Overrun = 0x1
	// Position of IDLE field.
	USART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	USART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	USART_ISR_IDLE = 0x10
	// No Idle Line is detected
	USART_ISR_IDLE_NoIdle = 0x0
	// Idle Line is detected
	USART_ISR_IDLE_Idle = 0x1
	// Position of RXFNE field.
	USART_ISR_RXFNE_Pos = 0x5
	// Bit mask of RXFNE field.
	USART_ISR_RXFNE_Msk = 0x20
	// Bit RXFNE.
	USART_ISR_RXFNE = 0x20
	// Data is not received
	USART_ISR_RXFNE_NoData = 0x0
	// Received data is ready to be read
	USART_ISR_RXFNE_DataReady = 0x1
	// Position of TC field.
	USART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	USART_ISR_TC_Msk = 0x40
	// Bit TC.
	USART_ISR_TC = 0x40
	// Transmission is not complete
	USART_ISR_TC_TxNotComplete = 0x0
	// Transmission is complete
	USART_ISR_TC_TxComplete = 0x1
	// Position of TXFNF field.
	USART_ISR_TXFNF_Pos = 0x7
	// Bit mask of TXFNF field.
	USART_ISR_TXFNF_Msk = 0x80
	// Bit TXFNF.
	USART_ISR_TXFNF = 0x80
	// Bit TXE. (added by gen-device-svd)
	USART_ISR_TXE = 0x80
	// Transmit FIFO is full
	USART_ISR_TXFNF_Full = 0x0
	// Transmit FIFO is not full
	USART_ISR_TXFNF_NotFull = 0x1
	// Position of LBDF field.
	USART_ISR_LBDF_Pos = 0x8
	// Bit mask of LBDF field.
	USART_ISR_LBDF_Msk = 0x100
	// Bit LBDF.
	USART_ISR_LBDF = 0x100
	// LIN break not detected
	USART_ISR_LBDF_NotDetected = 0x0
	// LIN break detected
	USART_ISR_LBDF_Detected = 0x1
	// Position of CTSIF field.
	USART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	USART_ISR_CTSIF = 0x200
	// No change occurred on the CTS status line
	USART_ISR_CTSIF_NotChanged = 0x0
	// A change occurred on the CTS status line
	USART_ISR_CTSIF_Changed = 0x1
	// Position of CTS field.
	USART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	USART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	USART_ISR_CTS = 0x400
	// CTS line set
	USART_ISR_CTS_Set = 0x0
	// CTS line reset
	USART_ISR_CTS_Reset = 0x1
	// Position of RTOF field.
	USART_ISR_RTOF_Pos = 0xb
	// Bit mask of RTOF field.
	USART_ISR_RTOF_Msk = 0x800
	// Bit RTOF.
	USART_ISR_RTOF = 0x800
	// Timeout value not reached
	USART_ISR_RTOF_NotReached = 0x0
	// Timeout value reached without any data reception
	USART_ISR_RTOF_Reached = 0x1
	// Position of EOBF field.
	USART_ISR_EOBF_Pos = 0xc
	// Bit mask of EOBF field.
	USART_ISR_EOBF_Msk = 0x1000
	// Bit EOBF.
	USART_ISR_EOBF = 0x1000
	// End of Block not reached
	USART_ISR_EOBF_NotReached = 0x0
	// End of Block (number of characters) reached
	USART_ISR_EOBF_Reached = 0x1
	// Position of UDR field.
	USART_ISR_UDR_Pos = 0xd
	// Bit mask of UDR field.
	USART_ISR_UDR_Msk = 0x2000
	// Bit UDR.
	USART_ISR_UDR = 0x2000
	// No underrun error
	USART_ISR_UDR_NoUnderrun = 0x0
	// underrun error
	USART_ISR_UDR_Underrun = 0x1
	// Position of ABRE field.
	USART_ISR_ABRE_Pos = 0xe
	// Bit mask of ABRE field.
	USART_ISR_ABRE_Msk = 0x4000
	// Bit ABRE.
	USART_ISR_ABRE = 0x4000
	// Position of ABRF field.
	USART_ISR_ABRF_Pos = 0xf
	// Bit mask of ABRF field.
	USART_ISR_ABRF_Msk = 0x8000
	// Bit ABRF.
	USART_ISR_ABRF = 0x8000
	// Position of BUSY field.
	USART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	USART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	USART_ISR_BUSY = 0x10000
	// USART is idle (no reception)
	USART_ISR_BUSY_Idle = 0x0
	// Reception on going
	USART_ISR_BUSY_Busy = 0x1
	// Position of CMF field.
	USART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	USART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	USART_ISR_CMF = 0x20000
	// No Character match detected
	USART_ISR_CMF_NoMatch = 0x0
	// Character match detected
	USART_ISR_CMF_Match = 0x1
	// Position of SBKF field.
	USART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	USART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	USART_ISR_SBKF = 0x40000
	// No break character transmitted
	USART_ISR_SBKF_NoBreak = 0x0
	// Break character transmitted
	USART_ISR_SBKF_Break = 0x1
	// Position of RWU field.
	USART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	USART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	USART_ISR_RWU = 0x80000
	// Receiver in Active mode
	USART_ISR_RWU_Active = 0x0
	// Receiver in Mute mode
	USART_ISR_RWU_Mute = 0x1
	// Position of WUF field.
	USART_ISR_WUF_Pos = 0x14
	// Bit mask of WUF field.
	USART_ISR_WUF_Msk = 0x100000
	// Bit WUF.
	USART_ISR_WUF = 0x100000
	// Position of TEACK field.
	USART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	USART_ISR_TEACK = 0x200000
	// Position of REACK field.
	USART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	USART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	USART_ISR_REACK = 0x400000
	// Position of TXFE field.
	USART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	USART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	USART_ISR_TXFE = 0x800000
	// TXFIFO not empty.
	USART_ISR_TXFE_NotEmpty = 0x0
	// TXFIFO empty.
	USART_ISR_TXFE_Empty = 0x1
	// Position of RXFF field.
	USART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	USART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	USART_ISR_RXFF = 0x1000000
	// RXFIFO not full.
	USART_ISR_RXFF_NotFull = 0x0
	// RXFIFO Full.
	USART_ISR_RXFF_Full = 0x1
	// Position of TCBGT field.
	USART_ISR_TCBGT_Pos = 0x19
	// Bit mask of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000
	// Bit TCBGT.
	USART_ISR_TCBGT = 0x2000000
	// Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
	USART_ISR_TCBGT_NotCompleted = 0x0
	// Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
	USART_ISR_TCBGT_Completed = 0x1
	// Position of RXFT field.
	USART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	USART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	USART_ISR_RXFT = 0x4000000
	// Receive FIFO does not reach the programmed threshold.
	USART_ISR_RXFT_NotReached = 0x0
	// Receive FIFO reached the programmed threshold.
	USART_ISR_RXFT_Reached = 0x1
	// Position of TXFT field.
	USART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	USART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	USART_ISR_TXFT = 0x8000000
	// TXFIFO does not reach the programmed threshold.
	USART_ISR_TXFT_NotReached = 0x0
	// TXFIFO reached the programmed threshold.
	USART_ISR_TXFT_Reached = 0x1

	// ICR: Interrupt flag clear register
	// Position of PECF field.
	USART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	USART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	USART_ICR_PECF = 0x1
	// Clears the PE flag in the ISR register
	USART_ICR_PECF_Clear = 0x1
	// Position of FECF field.
	USART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	USART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	USART_ICR_FECF = 0x2
	// Clears the FE flag in the ISR register
	USART_ICR_FECF_Clear = 0x1
	// Position of NECF field.
	USART_ICR_NECF_Pos = 0x2
	// Bit mask of NECF field.
	USART_ICR_NECF_Msk = 0x4
	// Bit NECF.
	USART_ICR_NECF = 0x4
	// Clears the NF flag in the ISR register
	USART_ICR_NECF_Clear = 0x1
	// Position of ORECF field.
	USART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	USART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	USART_ICR_ORECF = 0x8
	// Clears the ORE flag in the ISR register
	USART_ICR_ORECF_Clear = 0x1
	// Position of IDLECF field.
	USART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	USART_ICR_IDLECF = 0x10
	// Clears the IDLE flag in the ISR register
	USART_ICR_IDLECF_Clear = 0x1
	// Position of TXFECF field.
	USART_ICR_TXFECF_Pos = 0x5
	// Bit mask of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20
	// Bit TXFECF.
	USART_ICR_TXFECF = 0x20
	// Clear the TXFE flag in the ISR register
	USART_ICR_TXFECF_Clear = 0x1
	// Position of TCCF field.
	USART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	USART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	USART_ICR_TCCF = 0x40
	// Clears the TC flag in the ISR register
	USART_ICR_TCCF_Clear = 0x1
	// Position of TCBGTCF field.
	USART_ICR_TCBGTCF_Pos = 0x7
	// Bit mask of TCBGTCF field.
	USART_ICR_TCBGTCF_Msk = 0x80
	// Bit TCBGTCF.
	USART_ICR_TCBGTCF = 0x80
	// Clear the TCBGT flag in the ISR register
	USART_ICR_TCBGTCF_Clear = 0x1
	// Position of LBDCF field.
	USART_ICR_LBDCF_Pos = 0x8
	// Bit mask of LBDCF field.
	USART_ICR_LBDCF_Msk = 0x100
	// Bit LBDCF.
	USART_ICR_LBDCF = 0x100
	// Clears the LBDF flag in the ISR register
	USART_ICR_LBDCF_Clear = 0x1
	// Position of CTSCF field.
	USART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	USART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	USART_ICR_CTSCF = 0x200
	// Clears the CTSIF flag in the ISR register
	USART_ICR_CTSCF_Clear = 0x1
	// Position of RTOCF field.
	USART_ICR_RTOCF_Pos = 0xb
	// Bit mask of RTOCF field.
	USART_ICR_RTOCF_Msk = 0x800
	// Bit RTOCF.
	USART_ICR_RTOCF = 0x800
	// Clears the RTOF flag in the ISR register
	USART_ICR_RTOCF_Clear = 0x1
	// Position of EOBCF field.
	USART_ICR_EOBCF_Pos = 0xc
	// Bit mask of EOBCF field.
	USART_ICR_EOBCF_Msk = 0x1000
	// Bit EOBCF.
	USART_ICR_EOBCF = 0x1000
	// Clears the EOBF flag in the ISR register
	USART_ICR_EOBCF_Clear = 0x1
	// Position of UDRCF field.
	USART_ICR_UDRCF_Pos = 0xd
	// Bit mask of UDRCF field.
	USART_ICR_UDRCF_Msk = 0x2000
	// Bit UDRCF.
	USART_ICR_UDRCF = 0x2000
	// Clear the UDR flag in the ISR register
	USART_ICR_UDRCF_Clear = 0x1
	// Position of CMCF field.
	USART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	USART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	USART_ICR_CMCF = 0x20000
	// Clears the CMF flag in the ISR register
	USART_ICR_CMCF_Clear = 0x1
	// Position of WUCF field.
	USART_ICR_WUCF_Pos = 0x14
	// Bit mask of WUCF field.
	USART_ICR_WUCF_Msk = 0x100000
	// Bit WUCF.
	USART_ICR_WUCF = 0x100000
	// Clears the WUF flag in the ISR register
	USART_ICR_WUCF_Clear = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	USART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	USART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	USART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	USART_TDR_TDR_Msk = 0x1ff

	// PRESC: Prescaler register
	// Position of PRESCALER field.
	USART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf
	// Input clock divided by 1
	USART_PRESC_PRESCALER_Div1 = 0x0
	// Input clock divided by 2
	USART_PRESC_PRESCALER_Div2 = 0x1
	// Input clock divided by 4
	USART_PRESC_PRESCALER_Div4 = 0x2
	// Input clock divided by 6
	USART_PRESC_PRESCALER_Div6 = 0x3
	// Input clock divided by 8
	USART_PRESC_PRESCALER_Div8 = 0x4
	// Input clock divided by 10
	USART_PRESC_PRESCALER_Div10 = 0x5
	// Input clock divided by 12
	USART_PRESC_PRESCALER_Div12 = 0x6
	// Input clock divided by 16
	USART_PRESC_PRESCALER_Div16 = 0x7
	// Input clock divided by 32
	USART_PRESC_PRESCALER_Div32 = 0x8
	// Input clock divided by 64
	USART_PRESC_PRESCALER_Div64 = 0x9
	// Input clock divided by 128
	USART_PRESC_PRESCALER_Div128 = 0xa
	// Input clock divided by 256
	USART_PRESC_PRESCALER_Div256 = 0xb
)

// Constants for WWDG: System window watchdog
const (
	// CR: Control register
	// Position of T field.
	WWDG_CR_T_Pos = 0x0
	// Bit mask of T field.
	WWDG_CR_T_Msk = 0x7f
	// Position of WDGA field.
	WWDG_CR_WDGA_Pos = 0x7
	// Bit mask of WDGA field.
	WWDG_CR_WDGA_Msk = 0x80
	// Bit WDGA.
	WWDG_CR_WDGA = 0x80
	// Watchdog disabled
	WWDG_CR_WDGA_Disabled = 0x0
	// Watchdog enabled
	WWDG_CR_WDGA_Enabled = 0x1

	// CFR: Configuration register
	// Position of W field.
	WWDG_CFR_W_Pos = 0x0
	// Bit mask of W field.
	WWDG_CFR_W_Msk = 0x7f
	// Position of EWI field.
	WWDG_CFR_EWI_Pos = 0x9
	// Bit mask of EWI field.
	WWDG_CFR_EWI_Msk = 0x200
	// Bit EWI.
	WWDG_CFR_EWI = 0x200
	// interrupt occurs whenever the counter reaches the value 0x40
	WWDG_CFR_EWI_Enable = 0x1
	// Position of WDGTB field.
	WWDG_CFR_WDGTB_Pos = 0xb
	// Bit mask of WDGTB field.
	WWDG_CFR_WDGTB_Msk = 0x3800
	// Counter clock (PCLK1 div 4096) div 1
	WWDG_CFR_WDGTB_Div1 = 0x0
	// Counter clock (PCLK1 div 4096) div 2
	WWDG_CFR_WDGTB_Div2 = 0x1
	// Counter clock (PCLK1 div 4096) div 4
	WWDG_CFR_WDGTB_Div4 = 0x2
	// Counter clock (PCLK1 div 4096) div 8
	WWDG_CFR_WDGTB_Div8 = 0x3
	// Counter clock (PCLK1 div 4096) div 16
	WWDG_CFR_WDGTB_Div16 = 0x4
	// Counter clock (PCLK1 div 4096) div 32
	WWDG_CFR_WDGTB_Div32 = 0x5
	// Counter clock (PCLK1 div 4096) div 64
	WWDG_CFR_WDGTB_Div64 = 0x6
	// Counter clock (PCLK1 div 4096) div 128
	WWDG_CFR_WDGTB_Div128 = 0x7

	// SR: Status register
	// Position of EWIF field.
	WWDG_SR_EWIF_Pos = 0x0
	// Bit mask of EWIF field.
	WWDG_SR_EWIF_Msk = 0x1
	// Bit EWIF.
	WWDG_SR_EWIF = 0x1
	// The EWI Interrupt Service Routine has been serviced
	WWDG_SR_EWIF_Finished = 0x0
	// The EWI Interrupt Service Routine has been triggered
	WWDG_SR_EWIF_Pending = 0x1
)
